A low-loss, reversely conducting silicon carbide field effect power transistor device

Abstract

The application belongs to the technical field of semiconductors, and specifically provides a low-loss reversible-conductance silicon carbide field effect power transistor device; the application adopts a polysilicon / silicon carbide heterojunction, a silicon / silicon carbide heterojunction, a nickel oxide / silicon carbide heterojunction or an integrated Schottky diode structure to improve the reverse recovery characteristic of a silicon carbide MOSFET, realize self-reversible conductance, further realize lower reverse recovery loss and higher reverse recovery performance, finally reduce the reverse recovery loss and avoid using an off-chip freewheeling diode, and reduce the application cost and the volume of a system; at the same time, a high-k insulator and / or a super-junction structure, a nickel oxide / silicon carbide heterojunction super-junction structure and a nickel oxide / insulating layer / silicon carbide super-junction structure are further introduced; these new structures can effectively reduce the specific on-resistance while increasing the breakdown voltage, thereby reducing the on-loss and greatly improving the performance of the device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a low-loss reversible-conductance silicon carbide field effect power transistor device. BACKGROUND

[0002] As a third-generation semiconductor material, silicon carbide has more stable performance in more harsh working environments such as high temperature due to its super-wide band gap (3.26eV) which is about 3 times of that of silicon (1.1eV), and can withstand greater voltage resistance; and the theoretical critical breakdown field of silicon carbide material is 3MV / cm, which is much higher than 0.3MV / cm of silicon, so the silicon carbide device has higher voltage resistance level; the intrinsic carrier concentration of silicon carbide is much lower than that of silicon, and the smaller the intrinsic carrier concentration, the smaller the leakage current of the device under the same conditions; the thermal conductivity of silicon carbide is much higher than that of silicon, so the heat dissipation characteristic is better; the electron saturation rate of silicon carbide is close to twice that of silicon, so the silicon carbide device has higher switching speed. As can be seen, the power device based on silicon carbide material has excellent application prospect.

[0003] However, there are some problems in silicon carbide metal-oxide-semiconductor field effect transistor (SiC MOSFET), one is that the trade-off relationship between specific on-resistance and breakdown voltage is far from the "silicon carbide limit", and still needs to be further optimized, that is, while ensuring the voltage resistance of the device, the specific on-resistance is as low as possible; another important problem is that the opening voltage drop of the body PN junction diode of SiC MOSFET itself is large (about 2.8V), and the body PN junction diode has minority carrier storage effect and bipolar degradation effect, which leads to poor reverse recovery performance, large reverse recovery loss, and usually needs a piece of external anti-parallel freewheeling diode, which increases the application cost and the volume of the system. Finding a solution to these problems has become a difficult problem to be solved. SUMMARY

[0004] The present application aims at the defects in the background art, and provides a low-loss reversible-conductance silicon carbide field effect power transistor device; the present application uses polycrystalline silicon / silicon carbide heterojunction, silicon / silicon carbide heterojunction, nickel oxide / silicon carbide heterojunction or integrated Schottky diode structure to improve the reverse recovery characteristics of silicon carbide MOSFET, realize self-reversible conductance, reduce reverse recovery loss and avoid using external freewheeling diode, so as to reduce the application cost and the volume of the system; at the same time, part of the structure in the present application adopts high dielectric constant (high-k) insulator and super-junction structure, which can increase the breakdown voltage while reducing the specific on-resistance, thereby reducing the on-state loss of the device and improving the figure of merit of the device.

[0005] To achieve the above-mentioned purpose, the technical scheme adopted by the present application is as follows:

[0006] A low-loss reversible conducting silicon carbide field effect power transistor device, comprising: a first conductive type heavily doped silicon carbide substrate region 1, a metallized drain 11 disposed under the first conductive type heavily doped silicon carbide substrate region 1, and a first conductive type doped silicon carbide drift region 2 disposed on the first conductive type heavily doped silicon carbide substrate region 1; characterized in that,

[0007] The first conductive type doped silicon carbide drift region 2 is provided with a second conductive type doped silicon carbide base region 7, and a semiconductor hetero region 3 and a slot gate on both sides of the second conductive type doped silicon carbide base region 7, the second conductive type doped silicon carbide base region 7 is provided with a second conductive type heavily doped silicon carbide source contact region 5 and a first conductive type heavily doped silicon carbide source contact region 6, the semiconductor hetero region 3, the second conductive type heavily doped silicon carbide source contact region 5 and the first conductive type heavily doped silicon carbide source contact region 6 are all covered with a source metal 4, the slot gate is composed of an oxide layer 9 on the slot wall and a polysilicon gate 8 filled in the slot, and a second conductive type heavily doped silicon carbide shielding region 10 is further disposed under the slot gate; the semiconductor hetero region 3 is a first conductive type heavily doped polysilicon region, a second conductive type heavily doped polysilicon region, a first conductive type heavily doped silicon region, a second conductive type heavily doped silicon region or a second conductive type heavily doped nickel oxide region, and the corresponding semiconductor hetero region 3 and the first conductive type doped silicon carbide drift region 2 form a polysilicon / silicon carbide heterojunction, a silicon / silicon carbide heterojunction or a nickel oxide / silicon carbide heterojunction structure.

[0008] Preferably, the above-mentioned two silicon carbide field effect power transistor devices are further provided with a high-k insulator 12 disposed between the semiconductor hetero region 3 and the first conductive type heavily doped silicon carbide substrate region 1.

[0009] Preferably, the above-mentioned two silicon carbide field effect power transistor devices are further provided with a silicon dioxide body 13 and a second conductive type doped silicon carbide drift region 14, which are disposed side by side between the semiconductor hetero region 3 and the first conductive type heavily doped silicon carbide substrate region 1, and the second conductive type doped silicon carbide drift region 14 is located on one side of the first conductive type doped silicon carbide drift region 2.

[0010] Preferably, the above-mentioned two silicon carbide field effect power transistor devices are further provided with a high-k insulator 12 and a second conductive type doped silicon carbide drift region 14, which are disposed side by side between the semiconductor hetero region 3 and the first conductive type heavily doped silicon carbide substrate region 1, and the second conductive type doped silicon carbide drift region 14 is located on one side of the first conductive type doped silicon carbide drift region 2.

[0011] Preferably, the two silicon carbide field effect power transistor devices described above are further provided with a second conductive type doped nickel oxide drift region 15, which is arranged between the semiconductor hetero region 3 and the first conductive type heavily doped silicon carbide substrate region 1, and forms a nickel oxide / silicon carbide heterojunction structure with the first conductive type doped silicon carbide drift region 2.

[0012] Preferably, the two silicon carbide field effect power transistor devices described above are further provided with a second conductive type doped nickel oxide drift region 15 and an insulating layer 16, the second conductive type doped nickel oxide drift region is arranged below the semiconductor hetero region 3, and the insulating layer is arranged between the second conductive type doped nickel oxide drift region and the first conductive type heavily doped silicon carbide substrate region 1 and the first conductive type doped silicon carbide drift region 2, and the second conductive type doped nickel oxide drift region, the insulating layer and the first conductive type doped silicon carbide drift region form a nickel oxide / insulating layer / silicon carbide super junction structure.

[0013] Further, in the above-mentioned five preferred technical solutions, the semiconductor hetero region 3 is replaced with a source groove filled with a source metal 4, and the source metal 4, the first conductive type doped silicon carbide drift region 2, the first conductive type heavily doped silicon carbide substrate region 1 and the metalized drain 11 together form a Schottky diode structure.

[0014] Further, in the two silicon carbide field effect power transistor devices described above, the first conductive type is N type and the second conductive type is P type, and it is worth pointing out that the first conductive type and the second conductive type can be switched with each other according to design needs.

[0015] Compared with the prior art, the beneficial effects of the present application are as follows:

[0016] The present application provides a low-loss reversible conduction silicon carbide field effect power transistor device, which adopts integrated polysilicon / silicon carbide heterojunction, silicon / silicon carbide heterojunction, nickel oxide / silicon carbide heterojunction diode or integrated Schottky diode structure to improve the reverse recovery characteristics of the silicon carbide MOSFET, realize self-reversible conduction, and thus realize lower reverse recovery loss and higher reverse recovery performance, finally reduce the reverse recovery loss and avoid the use of off-chip freewheeling diode, reduce the application cost and the size of the system; at the same time, further introduce high-k insulator and / or super junction structure, nickel oxide / silicon carbide heterojunction super junction structure, and nickel oxide / insulating layer / silicon carbide super junction structure, which can effectively reduce the specific on-resistance while increasing the breakdown voltage, thereby reducing the on-state loss and greatly improving the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1A low-loss reversible-conductance polysilicon (silicon or nickel oxide) / silicon carbide heterojunction field effect transistor power device schematic diagram provided for the embodiment 1 of the present application.

[0018] Figure 2 A low-loss reversible-conductance polysilicon (silicon or nickel oxide) / silicon carbide heterojunction field effect transistor power device schematic diagram provided for the embodiment 2 of the present application with high-k insulator.

[0019] Figure 3 A low-loss reversible-conductance polysilicon (silicon or nickel oxide) / silicon carbide heterojunction field effect transistor power device schematic diagram provided for the embodiment 3 of the present application with super-junction structure.

[0020] Figure 4 A low-loss reversible-conductance polysilicon (silicon or nickel oxide) / silicon carbide heterojunction field effect transistor power device schematic diagram provided for the embodiment 4 of the present application with high-k insulator and super-junction structure.

[0021] Figure 5 A low-loss reversible-conductance polysilicon (silicon or nickel oxide) / silicon carbide heterojunction field effect transistor power device schematic diagram provided for the embodiment 5 of the present application with nickel oxide / silicon carbide heterojunction super-junction structure.

[0022] Figure 6 A low-loss reversible-conductance polysilicon (silicon or nickel oxide) / silicon carbide heterojunction field effect transistor power device schematic diagram provided for the embodiment 6 of the present application with nickel oxide / insulating layer / silicon carbide super-junction structure.

[0023] Figure 7 A low-loss reversible-conductance silicon carbide field effect transistor power device schematic diagram provided for the embodiment 7 of the present application with high-k insulator and super-junction structure and integrated Schottky diode. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and beneficial effects of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings and embodiments. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0025] Embodiment 1

[0026] The embodiment provides a low-loss reversible-conductance polysilicon (silicon or nickel oxide) / silicon carbide heterojunction field effect transistor power device, and a structure thereof is as shown in Figure 1 wherein, N type is a first conductive type, and P type is a second conductive type; specifically comprising:

[0027] a first conductive type heavily doped silicon carbide substrate region 1, a metallized drain 11 (forming ohmic contact) disposed under the first conductive type heavily doped silicon carbide substrate region 1, a first conductive type doped silicon carbide drift region 2 disposed on the first conductive type heavily doped silicon carbide substrate region 1;

[0028] The first conductive type doped silicon carbide drift region 2 is provided with a second conductive type doped silicon carbide base region 7, and a semiconductor heterojunction region 3 and a slot gate on both sides of the second conductive type doped silicon carbide base region 7, the second conductive type doped silicon carbide base region 7 is provided with a second conductive type heavily doped silicon carbide source contact region 5 and a first conductive type heavily doped silicon carbide source contact region 6, the semiconductor heterojunction region 3, the second conductive type heavily doped silicon carbide source contact region 5 and the first conductive type heavily doped silicon carbide source contact region 6 are all covered with a source metal 4 (forming ohmic contact), the slot gate is composed of an oxide layer 9 on the slot wall and a polysilicon gate 8 filled in the slot, and a second conductive type heavily doped silicon carbide shielding region 10 is further disposed under the slot gate; the semiconductor heterojunction region 3 is a first conductive type heavily doped polysilicon region, a second conductive type heavily doped polysilicon region, a first conductive type heavily doped silicon region, a second conductive type heavily doped silicon region or a second conductive type heavily doped nickel oxide region, and the corresponding semiconductor heterojunction region 3 and the first conductive type doped silicon carbide drift region 2 form a polysilicon / silicon carbide heterojunction, a silicon / silicon carbide heterojunction or a nickel oxide / silicon carbide heterojunction structure.

[0029] The working principle of the embodiment is as follows:

[0030] The electrode connection mode of the MOSFET power device in the embodiment when forward conducting is that the metallized drain (D) 11 is connected to a high potential, the metallized source (S) 4 is connected to a reference zero potential, and the polysilicon gate (G) 8 is connected to a high potential relative to the metallized source (S) 4; when the MOSFET device is forward conducting, the polysilicon gate (G) 8 applies a bias voltage greater than the threshold voltage to form an inversion layer on the side wall of the second conductive type doped silicon carbide base region 7 close to the oxide layer 9, and when a positive voltage is applied between the metallized drain (D) 11 and the metallized source (S) 4, electrons pass from the metallized source (S) 4 to the metallized drain (D) 11 through the first conductive type heavily doped silicon carbide region 6, the second conductive type doped silicon carbide base region 7, the first conductive type doped silicon carbide drift region 2 and the first conductive type heavily doped silicon carbide substrate region 1 to form a forward conducting current;

[0031] The electrode connection mode when the device is in forward blocking state is: the metalized drain (D) 11 is connected to high potential, the metalized source (S) 4 is connected to reference zero point, and the polysilicon gate (G) 8 is connected to zero or negative potential relative to the metalized source (S) 4; at this time, no inversion layer is formed in the second conductive type doped silicon carbide base region 7, that is, no conductive channel is formed; the PN junction formed by the semiconductor hetero region 3, the second conductive type heavily doped silicon carbide region 10 and the first conductive type doped silicon carbide drift region 2 together withstands voltage, the depletion region extends downward and may be depleted to the first conductive type heavily doped silicon carbide substrate region 1; the second conductive type heavily doped silicon carbide region 10 is located at the bottom of the oxide layer 9, which can prevent breakdown of the bottom of the oxide layer;

[0032] At the moment when the device is in the process of turning from the on state to the forward blocking state, the potential of the metalized drain (D) 11 relative to the metalized source (S) 4 is negative under the action of the induced reverse electromotive force of the inductive load; at this time, the polysilicon / silicon carbide heterojunction, silicon / silicon carbide heterojunction or nickel oxide / silicon carbide heterojunction structure formed by the semiconductor hetero region 3 and the first conductive type doped silicon carbide drift region 2 generates tunneling electron current, which can extract the carriers stored in the first conductive type doped silicon carbide drift region 2 when the device is in forward conduction, realizes self-reverse conduction of the device, and reduces the reverse recovery time and loss.

[0033] Embodiment 2

[0034] This embodiment provides a polysilicon (silicon or nickel oxide) / silicon carbide heterojunction field effect transistor power device with low loss reversible conduction and high-k insulator, the structure of which is shown in Figure 2 The difference between this embodiment and embodiment 1 is that the power device is further provided with a high-k insulator 12, which is arranged between the semiconductor hetero region 3 and the first conductive type heavily doped silicon carbide substrate region 1.

[0035] The working principle of this embodiment is as follows:

[0036] The working principle of the MOSFET power device in the embodiment is the same as that of the embodiment 1 when it is forward conducting and when it is in the process of transition from the conducting state to the forward blocking state; while in the forward blocking state of the device, the electrode connection mode is: the metallized drain (D) 11 is connected to the high potential, the metallized source (S) 4 is connected to the reference zero point, and the polysilicon gate (G) 8 is connected to the zero or negative potential relative to the metallized source (S) 4; at this time, no inversion layer is formed in the second conductive type doped silicon carbide base region 7, that is, no conductive channel is formed; at the same time, the electric lines emitted by the ionized donors in the first conductive type doped silicon carbide drift region 2 will enter the high-k insulator 12 laterally and be compensated by the ionized acceptors in the semiconductor hetero region 3, so that the electric field distribution is optimized; in addition, due to the mutual compensation of charges, the doping concentration of the first conductive type doped silicon carbide drift region 2 can be greatly improved, thereby reducing the specific on-resistance and the on-state loss when forward conducting.

[0037] Embodiment 3

[0038] The embodiment provides a low-loss reversible conducting polysilicon (silicon or nickel oxide) / silicon carbide heterojunction field effect transistor power device with a super-junction structure, and a structure thereof is shown in Figure 3 The difference between the power device and the embodiment 1 is that the power device is further provided with a silicon dioxide body 13 and a second conductive type doped silicon carbide drift region 14, the silicon dioxide body 13 and the second conductive type doped silicon carbide drift region 14 are arranged side by side between the semiconductor hetero region 3 and the first conductive type heavily doped silicon carbide substrate region 1, and the second conductive type doped silicon carbide drift region 14 is located on one side of the first conductive type doped silicon carbide drift region 2.

[0039] The working principle of the embodiment is as follows:

[0040] The working principle of the MOSFET power device in the embodiment is the same as that of the embodiment 1 when it is forward conducting and when it is changing from the conducting state to the forward blocking state; while in the forward blocking state of the device, the electrode connection mode is: the metalized drain (D) 11 is connected to the high potential, the metalized source (S) 4 is connected to the reference zero point, and the polysilicon gate (G) 8 is connected to the zero or negative potential relative to the metalized source (S) 4; at this time, no inversion layer is formed in the second-conductivity-type doped silicon carbide base region 7, i.e. no conductive channel is formed; at the same time, the electric lines emitted by the ionized donors in the first-conductivity-type doped silicon carbide drift region 2 will enter the second-conductivity-type doped silicon carbide drift region 14 laterally and be compensated by the ionized acceptors in the second-conductivity-type doped silicon carbide drift region 14, so that the electric field distribution is optimized; in addition, due to the mutual compensation of charges, the doping concentration of the first-conductivity-type doped silicon carbide drift region 2 can be greatly improved, thereby reducing the specific on-resistance and reducing the on-state loss when forward conducting. The function of the silicon dioxide body 13 is to simplify the process flow, because the trench is dug first, then the second-conductivity-type doped silicon carbide drift region 14 is formed by ion implantation, and then the silicon dioxide body 13 is deposited, which can greatly simplify the process flow.

[0041] Embodiment 4

[0042] The embodiment provides a low-loss reversible conducting polysilicon (silicon or nickel oxide) / silicon carbide heterojunction field effect transistor power device with a high-k insulator and a super-junction structure, which has a structure as shown in Figure 4 The difference between the power device and the embodiment 1 is that the power device is further provided with a high-k insulator 12 and a second-conductivity-type doped silicon carbide drift region 14, the high-k insulator 12 and the second-conductivity-type doped silicon carbide drift region 14 are arranged side by side between the semiconductor heterojunction region 3 and the first-conductivity-type heavily doped silicon carbide substrate region 1, and the second-conductivity-type doped silicon carbide drift region 14 is located on one side of the first-conductivity-type doped silicon carbide drift region 2.

[0043] The working principle of the embodiment is as follows:

[0044] The working principle of the MOSFET power device in the embodiment is the same as that of the embodiment 1 when it is forward conducting and when it is in the process of transition from the conducting state to the forward blocking state; while in the forward blocking state of the device, the electrode connection mode is: the metallized drain (D) 11 is connected to the high potential, the metallized source (S) 4 is connected to the reference zero potential, and the polysilicon gate (G) 8 is connected to the zero or negative potential relative to the metallized source (S) 4; at this time, no inversion layer is formed in the second-conductivity-type doped silicon carbide base region 7, that is, no conductive channel is formed; at the same time, the ionized donors in the first-conductivity-type doped silicon carbide drift region 2 will enter the second-conductivity-type doped silicon carbide drift region 14 laterally through the generated electric lines of force, and are compensated with the ionized acceptors in the second-conductivity-type doped silicon carbide drift region 14, so that the electric field distribution is optimized; and the ionized donors in the first-conductivity-type heavily doped silicon carbide substrate region 1 will generate electric lines of force through the high-k insulator 12, then enter the second-conductivity-type doped silicon carbide drift region 14 laterally, and are compensated with the ionized acceptors in the second-conductivity-type doped silicon carbide drift region 14, also so that the electric field distribution is optimized; in addition, due to the mutual compensation of charges, the doping concentration of the first-conductivity-type doped silicon carbide drift region 2 can be greatly improved, thereby reducing the specific on-resistance and the on-state loss when forward conducting.

[0045] Embodiment 5

[0046] The embodiment provides a low-loss reversible conducting polysilicon (silicon or nickel oxide) / silicon carbide heterojunction field effect transistor power device with a nickel oxide / silicon carbide heterojunction super-junction structure, the structure of which is shown in Figure 5 The difference between the power device and the embodiment 1 is that the power device is further provided with a second-conductivity-type doped nickel oxide drift region 15, the second-conductivity-type doped nickel oxide drift region 15 is arranged between the semiconductor heterojunction region 3 and the first-conductivity-type heavily doped silicon carbide substrate region 1, and the second-conductivity-type doped nickel oxide drift region 15 and the first-conductivity-type doped silicon carbide drift region 2 form a nickel oxide / silicon carbide heterojunction structure.

[0047] The working principle of the embodiment is as follows:

[0048] The working principle of the MOSFET power device in the embodiment is the same as that of the embodiment 1 when it is forward conducting; when the device is forward blocking, the electrode connection mode is: the metalized drain (D) 11 is connected to a high potential, the metalized source (S) 4 is connected to a reference zero potential, and the polysilicon gate (G) 8 is connected to zero or negative potential relative to the metalized source (S) 4; at this time, no inversion layer is formed in the second-conductivity-type doped silicon carbide base region 7, that is, no conductive channel is formed; at the same time, the ionized donors in the first-conductivity-type doped silicon carbide drift region 2 will enter the second-conductivity-type doped nickel oxide drift region 15 laterally through the generated electric lines, and are compensated with the ionized acceptors in the second-conductivity-type doped nickel oxide drift region 15, so that the electric field distribution is optimized; in addition, due to the mutual compensation of charges, the doping concentration of the first-conductivity-type doped silicon carbide drift region 2 can be greatly improved, thereby reducing the specific on-resistance and reducing the on-state loss when forward conducting;

[0049] At the moment when the device is switched from the on state to the forward blocking state, the potential of the metalized drain (D) 11 relative to the metalized source (S) 4 is negative under the action of the induced reverse electromotive force of the inductive load; at this time, the semiconductor hetero region 3 and the first-conductivity-type doped silicon carbide drift region 2 form a polysilicon / silicon carbide heterojunction, a silicon / silicon carbide heterojunction or a nickel oxide / silicon carbide heterojunction to generate tunneling current, and at the same time, the second-conductivity-type doped nickel oxide drift region 15 and the first-conductivity-type doped silicon carbide drift region 2 form a nickel oxide / silicon carbide heterojunction to generate tunneling current, both of which can extract the carriers stored in the first-conductivity-type doped silicon carbide drift region 2 when forward conducting, thereby realizing self-reverse conduction of the device and reducing the reverse recovery time and loss.

[0050] Embodiment 6

[0051] The embodiment provides a polysilicon (silicon or nickel oxide) / silicon carbide heterojunction field effect transistor power device with a nickel oxide / insulating layer / silicon carbide super-junction structure and low-loss reverse conduction, and the structure is as shown in Figure 6As shown, the difference between the embodiment 1 and the embodiment 2 is that the power device is further provided with a second-conductivity-type doped nickel oxide drift region 15 and an insulation layer 16, the second-conductivity-type doped nickel oxide drift region is arranged below the semiconductor hetero region 3, and the insulation layer is arranged between the second-conductivity-type doped nickel oxide drift region and the first-conductivity-type heavily doped silicon carbide substrate region 1 and between the second-conductivity-type doped nickel oxide drift region and the first-conductivity-type doped silicon carbide drift region 2; that is, the insulation layer semi-surrounds the second-conductivity-type doped nickel oxide drift region, so as to separate the second-conductivity-type doped nickel oxide drift region from the first-conductivity-type heavily doped silicon carbide substrate region 1 and the first-conductivity-type doped silicon carbide drift region 2 through the insulation layer; the second-conductivity-type doped nickel oxide drift region 15, the insulation layer 16 and the first-conductivity-type doped silicon carbide drift region 2 form a nickel oxide / insulation layer / silicon carbide super-junction structure.

[0052] The working principle of the embodiment is as follows:

[0053] The working principle of the MOSFET power device in the embodiment when conducting in the forward direction is the same as that of the embodiment 1; while when blocking in the forward direction, the electrode connection mode is that the metalized drain (D) 11 is connected to a high potential, the metalized source (S) 4 is connected to a reference zero potential, and the polysilicon gate (G) 8 is connected to a zero or negative potential relative to the metalized source (S) 4; at this time, no inversion layer is formed in the second-conductivity-type doped silicon carbide base region 7, that is, no conductive channel is formed; at the same time, the electric lines generated by the ionized donors in the first-conductivity-type doped silicon carbide drift region 2 will enter the second-conductivity-type doped nickel oxide drift region 15 laterally through the insulation layer 16 and be compensated by the ionized acceptors in the second-conductivity-type doped nickel oxide drift region 15, so that the electric field distribution is optimized; in addition, since the insulation layer 16 prevents the impurities in the second-conductivity-type doped nickel oxide drift region 15 and the first-conductivity-type doped silicon carbide drift region 2 from diffusing into each other, the cell can be further reduced in size, and since the doping concentration can be higher when the cell width is smaller under the same withstand voltage, the doping concentration of the first-conductivity-type doped silicon carbide drift region 2 can be greatly improved, so as to reduce the specific on-resistance and the on-state loss when conducting in the forward direction;

[0054] In the moment when the device is transited from the on state to the forward blocking state, the potential of the metalized drain (D) 11 is negative relative to the potential of the metalized source (S) 4 under the action of the induced reverse electromotive force of the inductive load, at this time, the semiconductor hetero region 3 and the first conductive type doped silicon carbide drift region 2 form a polysilicon / silicon carbide heterojunction, a silicon / silicon carbide heterojunction or a nickel oxide / silicon carbide heterojunction to generate a tunneling current, at the same time, the second conductive type doped nickel oxide drift region 15, the insulating layer 16 and the first conductive type doped silicon carbide drift region 2 form a nickel oxide / insulating layer / silicon carbide structure to generate a tunneling current, both of which can extract the carriers stored in the first conductive type doped silicon carbide drift region 2 during the forward conduction, thus realizing the self-reverse conduction of the device and reducing the reverse recovery time and loss.

[0055] Embodiment 7

[0056] The embodiment provides a low-loss reversible-conduction silicon carbide field effect transistor power device with a high-k insulator and a super-junction structure and an integrated Schottky diode, and the structure is as shown in Figure 6 The embodiment specifically comprises the following steps:

[0057] The first conductive type heavily doped silicon carbide substrate region 1 is provided with the metalized drain 11 (forming an ohmic contact) below the first conductive type heavily doped silicon carbide substrate region 1, and the first conductive type doped silicon carbide drift region 2, the high-k insulator 12 and the second conductive type doped silicon carbide drift region 14 above the first conductive type heavily doped silicon carbide substrate region 1.

[0058] The first conductive type doped silicon carbide drift region 2 is provided with the second conductive type doped silicon carbide base region 7 and the source slot and the slot gate on both sides of the second conductive type doped silicon carbide base region 7, the source slot is filled with the source metal 4, the second conductive type doped silicon carbide base region 7 is provided with the second conductive type heavily doped silicon carbide source contact region 5 and the first conductive type heavily doped silicon carbide source contact region 6, the second conductive type heavily doped silicon carbide source contact region 5 and the first conductive type heavily doped silicon carbide source contact region 6 are covered with the source metal 4 (forming an ohmic contact), the slot gate is composed of the oxide layer 9 on the slot wall and the polysilicon gate 8 filled in the slot, and the second conductive type heavily doped silicon carbide shielding region 10 is further provided below the slot gate; the high-k insulator 12 and the second conductive type doped silicon carbide drift region 14 are provided between the source metal 4 and the first conductive type heavily doped silicon carbide substrate region 1 in parallel, and the second conductive type doped silicon carbide drift region 14 is located on one side of the first conductive type doped silicon carbide drift region 2; the source metal 4, the first conductive type doped silicon carbide drift region 2, the first conductive type heavily doped silicon carbide substrate region 1 and the metalized drain 11 jointly form a Schottky diode structure.

[0059] The working principle of the embodiment is as follows:

[0060] The electrode connection mode of the MOSFET power device in the forward conduction is that the metalized drain (D) 11 is connected to a high potential, the metalized source (S) 4 is connected to a reference zero potential, and the polysilicon gate (G) 8 is connected to a high potential relative to the metalized source (S) 4. When the MOSFET device is in the forward conduction, the polysilicon gate (G) 8 is biased at a voltage greater than the threshold voltage to form an inversion layer in the second-conductivity-type doped silicon carbide base region 7 close to the sidewall of the oxide layer 9. When a positive voltage is applied between the metalized drain (D) 11 and the metalized source (S) 4, electrons flow from the metalized source (S) 4 through the first-conductivity-type heavily doped silicon carbide region 6, the second-conductivity-type doped silicon carbide base region 7, the first-conductivity-type doped silicon carbide drift region 2, and the first-conductivity-type heavily doped silicon carbide substrate region 1 to the metalized drain (D) 11 to form a forward conduction current.

[0061] The electrode connection mode of the device in the forward blocking state is that the metalized drain (D) 11 is connected to a high potential, the metalized source (S) 4 is connected to a reference zero potential, and the polysilicon gate (G) 8 is connected to a zero or negative potential relative to the metalized source (S) 4. At this time, no inversion layer is formed in the second-conductivity-type doped silicon carbide base region 7, i.e., no conductive channel is formed. At the same time, the ionized donors in the first-conductivity-type doped silicon carbide drift region 2 enter the second-conductivity-type doped silicon carbide drift region 14 through the generated electric lines and are compensated by the ionized acceptors in the second-conductivity-type doped silicon carbide drift region 14, so that the electric field distribution is optimized. Moreover, the electric lines generated by the ionized donors in the first-conductivity-type heavily doped silicon carbide substrate region 1 pass through the high-k insulator 12 and then enter the second-conductivity-type doped silicon carbide drift region 14 laterally and are compensated by the ionized acceptors in the second-conductivity-type doped silicon carbide drift region 14, also optimizing the electric field distribution. In addition, due to the mutual compensation of charges, the doping concentration of the first-conductivity-type doped silicon carbide drift region 2 can be greatly improved, thereby reducing the specific on-resistance and the conduction loss in the forward conduction.

[0062] At the moment when the device changes from the on state to the forward blocking state, the potential of the metalized drain (D) 11 relative to the metalized source (S) 4 is negative due to the action of the induced reverse electromotive force of the inductive load. At this time, the Schottky diode composed of the metalized source (S) 4, the first-conductivity-type doped silicon carbide drift region 2, the first-conductivity-type heavily doped silicon carbide substrate region 1, and the metalized drain (D) 11 is turned on to form a reverse conduction current. The current flows from the metalized source (S) 4 through the first-conductivity-type doped silicon carbide drift region 2, then through the first-conductivity-type heavily doped silicon carbide substrate region 1 to the metalized drain (D) 11. This current can extract the carriers stored in the first-conductivity-type doped silicon carbide drift region 2, realizing self-reverse conduction of the device and reducing the reverse recovery time and loss.

[0063] It should be further noted that, as can be seen from the above, in the present embodiment, compared with Embodiment 4, the integrated polysilicon / silicon carbide heterojunction, silicon / silicon carbide heterojunction, nickel oxide / silicon carbide heterojunction diode formed by the semiconductor heterojunction region 3 and the first conductive type doped silicon carbide drift region 2 is replaced by the integrated Schottky diode structure by replacing the semiconductor heterojunction region 3 in Embodiment 4 with the source trench filled with the source metal 4, which can also improve the reverse recovery characteristics of the silicon carbide MOSFET, realize self-reversible conduction, and further realize lower reverse recovery loss and higher reverse recovery performance. Similarly, the semiconductor heterojunction region 3 in Embodiment 2, Embodiment 3, Embodiment 5 or Embodiment 6 can also be replaced by the source trench filled with the source metal 4 to achieve the same beneficial effects.

[0064] The above merely illustrates the specific embodiments of the present application, and any feature disclosed in the present specification can be replaced by other equivalent or similar purpose features unless specifically described; all features disclosed or steps in all methods or processes can be combined in any manner except for mutually exclusive features and / or steps.

Claims

1. A low-loss, reversible silicon carbide field-effect power transistor device, comprising: A first conductivity type heavily doped silicon carbide substrate region (1), a metallized drain (11) disposed under the first conductivity type heavily doped silicon carbide substrate region (1), and a first conductivity type doped silicon carbide drift region (2) disposed on the first conductivity type heavily doped silicon carbide substrate region (1); characterized in that, The first conductivity type doped silicon carbide drift region (2) is provided with a second conductivity type doped silicon carbide base region (7), and semiconductor heterogeneous regions (3) and trench gates located on both sides of the second conductivity type doped silicon carbide base region (7). The second conductivity type doped silicon carbide base region (7) is provided with a second conductivity type heavily doped silicon carbide source contact region (5) and a first conductivity type heavily doped silicon carbide source contact region (6). The semiconductor heterogeneous region (3) and the second conductivity type heavily doped silicon carbide source contact region are provided with a second conductivity type doped silicon carbide source contact region (5). (5) The source metal (4) is covered on the contact area (6) of the first conductivity type heavily doped silicon carbide source. The trench gate is composed of an oxide layer (9) located on the trench wall and a polysilicon gate (8) filled in the trench. A second conductivity type heavily doped silicon carbide shielding area (10) is also provided under the trench gate. The semiconductor heterogeneous region (3) is a second conductivity type heavily doped nickel oxide region. The corresponding semiconductor heterogeneous region (3) and the first conductivity type doped silicon carbide drift region (2) form a nickel oxide / silicon carbide heterojunction structure. The silicon carbide field-effect power transistor device also includes a high-performance... k Insulator (12) and second conductivity type doped silicon carbide drift region (14), the high k An insulator and a second conductivity type doped silicon carbide drift region are arranged side-by-side between the semiconductor heterogeneous region (3) and the first conductivity type heavily doped silicon carbide substrate region (1), with the second conductivity type doped silicon carbide drift region located on one side of the first conductivity type doped silicon carbide drift region (2), along the direction from the semiconductor heterogeneous region (3) to the first conductivity type heavily doped silicon carbide substrate region (1). k The insulator and the second conductivity type doped silicon carbide drift region have the same depth.

2. The low-loss reversible silicon carbide field-effect power transistor device according to claim 1, characterized in that, The semiconductor heterogeneous region (3) is replaced by a source trench filled with source metal (4). The source metal, together with the first conductivity type doped silicon carbide drift region (2), the first conductivity type heavily doped silicon carbide substrate region (1), and the metallized drain (11), constitute a Schottky diode structure.

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