Grid stress slow-release structure of split-gate MOSFET and preparation method of grid stress slow-release structure

Abstract

The invention discloses a grid stress slow-release structure of a split-gate MOSFET and a preparation method of the grid stress slow-release structure. The structure comprises a semiconductor epitaxial layer, a groove formed in the semiconductor epitaxial layer, a grid insulating layer arranged in the groove and at least one mounting cavity defined by the grid insulating layer. A gate conducting layer is arranged in each mounting cavity, a buffer dielectric layer is arranged between the outer surface of the gate conducting layer and the inner wall of the corresponding mounting cavity, and the thermal expansion coefficient of the buffer dielectric layer is smaller than that of the gate conducting layer. According to the technical scheme, a stress buffer interface can be formed between the gate conducting layer and the gate insulating layer, so that mechanical stress generated by thermal expansion difference is reduced, and the stability of the gate insulating layer and the reliability of the device are improved.

Description

A gate stress relief structure for a split-gate MOSFET and its fabrication method Technical Field

[0001] This invention relates to the field of semiconductor device structure design and manufacturing technology, and in particular to a gate stress relief structure for a split-gate MOSFET and its preparation method. Background Technology

[0002] Split-gate MOSFETs are a common power semiconductor device structure. They typically involve etching trenches in a semiconductor epitaxial layer and constructing the gate structure within the trenches to control the current path. Compared to conventional trench-gate MOSFETs, split-gate MOSFETs divide the gate structure into upper and lower regions within the trench. By forming multiple mutually insulated gate-related structures within the trench, the electric field distribution inside the trench is optimized, which helps reduce gate-drain capacitance and improve the device's switching performance.

[0003] Currently, the gate structure inside the trench is typically formed by filling it with conductive material and is isolated from the semiconductor region by insulating layers such as oxide layers. During manufacturing, these devices often undergo multiple high-temperature thermal treatment processes, and power devices may also operate in high-temperature environments. During temperature changes, due to differences in the thermal expansion characteristics of the gate material, insulating layer, and semiconductor material, inconsistent expansion or contraction may occur between different materials, resulting in mechanical stress at the interface. When this stress acts near the gate insulating layer for a long period, it may affect the stability of the insulating layer, such as causing performance degradation or interface quality deterioration. Therefore, how to reduce the stress caused by the difference in thermal expansion between the gate structure and the insulating layer inside the trench, thereby improving the stability and reliability of the device, has become a problem that requires further improvement. Summary of the Invention

[0004] This application provides a gate stress relief structure for a split-gate MOSFET, aiming to solve the technical problem that the interface stress generated between the gate conductive layer and the insulating layer due to the difference in the coefficient of thermal expansion in the existing split-gate MOSFET trench gate structure affects the stability of the gate insulating layer and the reliability of the device.

[0005] This invention is implemented as follows: a gate stress relief structure for a split-gate MOSFET includes a semiconductor epitaxial layer, a gate insulating layer, and at least one gate conductive layer; the semiconductor epitaxial layer has a trench; the gate insulating layer is disposed within the trench, and at least one mounting cavity is formed within the gate insulating layer, with different mounting cavities not interconnected; the number of gate conductive layers corresponds one-to-one with the number of mounting cavities, and each gate conductive layer is disposed within a corresponding mounting cavity; wherein, a buffer dielectric layer is provided between the outer surface of each gate conductive layer and the inner wall surface of the corresponding mounting cavity, and the coefficient of thermal expansion of the buffer dielectric layer is less than the coefficient of thermal expansion of the gate conductive layer.

[0006] Optionally, the trench has a depth direction and a width direction perpendicular to the depth direction, wherein each gate conductive layer has two oppositely disposed side surfaces in the width direction; the buffer dielectric layer is disposed between the two side surfaces of the gate conductive layer and the corresponding mounting cavity inner wall, and extends continuously along the side surfaces.

[0007] Optionally, the thickness of the buffer medium layer is 20 Å to 200 Å.

[0008] Optionally, the material of the buffer medium layer is selected from one or more of silicon nitride, silicon oxynitride, silicon oxynitride, or aluminum oxide.

[0009] Optionally, the number of gate conductive layers is two, and the two gate conductive layers are spaced apart in the depth direction of the trench.

[0010] Optionally, the gate conductive layer closer to the bottom of the trench is defined as the bottom gate, and the gate conductive layer farther from the bottom of the trench is defined as the top gate; the trench has a width direction perpendicular to its depth direction; the dimension of the top gate in the width direction is larger than the dimension of the bottom gate in the width direction.

[0011] Optionally, the gate insulating layer between the bottom gate and the trench wall is a field oxide layer, and the gate insulating layer between the top gate and the trench wall is a gate oxide layer.

[0012] Optionally, the gate insulating layer between the field oxide layer and the gate oxide layer is a polysilicon inter-oxide layer.

[0013] Optionally, the thickness of the field oxide layer is 500 Å to 3000 Å.

[0014] Optionally, the thickness of the gate oxide layer is 500 Å to 1200 Å.

[0015] Optionally, the thickness of the intercrystalline silicon oxide layer is 1500 Å to 4000 Å.

[0016] The present invention also provides a method for fabricating a split-gate MOSFET, used to fabricate the gate stress relief structure of the above-mentioned split-gate MOSFET. The method includes: providing a semiconductor epitaxial layer and forming a trench in the semiconductor epitaxial layer; forming a field oxide layer on the trench wall and forming a buffer dielectric layer on the surface of the field oxide layer; filling the trench with a gate conductive material and removing excess gate conductive material outside the trench to form a bottom gate; etching back the structure in the trench to form a space above the bottom gate; filling the trench with an oxide layer and etching back the filled oxide layer to retain a portion of the oxide layer above the bottom gate as a polysilicon inter-oxide layer and forming a space above the polysilicon inter-oxide layer; forming a gate oxide layer on the trench sidewall located above the polysilicon inter-oxide layer and forming a buffer dielectric layer on the surface of the gate oxide layer; filling the upper part of the trench with a gate conductive material and removing excess gate conductive material outside the trench to form a top gate.

[0017] The technical solution provided in this application includes a semiconductor epitaxial layer with trenches, a gate insulating layer disposed within the trenches, at least one mounting cavity formed by the gate insulating layer, and gate conductive layers disposed in each mounting cavity. Unlike a typical structure where only an insulating layer separates the gate conductive layer from the semiconductor region, a buffer dielectric layer is disposed between the outer surface of each gate conductive layer and the inner wall of the corresponding mounting cavity. The thermal expansion coefficient of this buffer dielectric layer is less than that of the gate conductive layer. Thus, the interior of the trench is no longer an interface relationship where the gate conductive layer is directly adjacent to the gate insulating layer, but rather a layered structure where the inner wall of the mounting cavity, the buffer dielectric layer, and the gate conductive layer are sequentially distributed. Since the mounting cavity itself is defined by the gate insulating layer, the buffer dielectric layer is actually arranged on the stress transmission path between the gate conductive layer and the gate insulating layer. Therefore, when the temperature changes, the dimensional changes generated by the gate conductive layer no longer directly affect the gate insulating layer, but are first transferred through the buffer dielectric layer.

[0018] During device manufacturing and operation, the materials within the trench expand or contract with temperature changes, but the magnitude of these changes varies among different materials. The gate conductive layer typically exhibits a more pronounced thermal dimensional change trend. When it is very close to the surrounding insulating structure, or even forms a direct interface, this dimensional change easily translates into compression or tension at the interface, concentrating near the gate insulating layer. The gate insulating layer is relatively thin and located under the combined influence of electric field and structural constraints, making it highly sensitive to interfacial stress. Therefore, its stability is easily affected by prolonged exposure to mechanical forces caused by thermal mismatch. By placing a buffer dielectric layer with a lower coefficient of thermal expansion around the gate conductive layer, the expansion trend of the gate conductive layer during heating is first constrained and dispersed by this buffer dielectric layer, resulting in a smoother deformation transfer at the interface. During cooling, the localized tensile stress that would normally be caused by shrinkage differences is also released due to the presence of the intermediate transition layer. In other words, the significance of this structural change lies not in simply adding a dielectric layer, but in rearranging the stress transmission relationship inside the trench, so that the thermal mismatch effect that was originally concentrated near the gate insulating layer is transferred and mitigated in the transition region where the buffer dielectric layer is located, thereby reducing the mechanical burden on the gate insulating layer.

[0019] Meanwhile, a buffer dielectric layer is disposed between each gate conductive layer and the corresponding mounting cavity inner wall. This means that regardless of whether a single gate conductive layer or multiple separated gate conductive layers are disposed within the trench, each conductive layer has the same stress-relieving interface with the surrounding insulating structure. Therefore, the gate structure at different locations within the trench can achieve a relatively consistent buffering effect under thermal cycling conditions, preventing localized areas from becoming weak points of stress concentration due to overly rigid interface relationships. For trench gate structures, this approach can more effectively maintain the structural integrity and interface stability of the gate insulating layer, thereby contributing to better reliability of the device during long-term use after manufacturing. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0021] Figure 1 is a schematic diagram of the fabrication process of the gate stress relief structure of the split-gate MOSFET of the present invention (I); Figure 2 is a schematic diagram of the fabrication process of the gate stress relief structure of the split-gate MOSFET of the present invention (II); Figure 3 is a schematic diagram of the fabrication process of the gate stress relief structure of the split-gate MOSFET of the present invention (III); Figure 4 is a schematic diagram of the fabrication process of the gate stress relief structure of the split-gate MOSFET of the present invention (IV); Figure 5 is a schematic diagram of the fabrication process of the gate stress relief structure of the split-gate MOSFET of the present invention (V); Figure 6 is a schematic diagram of the fabrication process of the gate stress relief structure of the split-gate MOSFET of the present invention (VI); Figure 7 is a schematic diagram of the fabrication process of the gate stress relief structure of the split-gate MOSFET of the present invention (VII); Figure 8 is a schematic diagram of the fabrication process of the gate stress relief structure of the split-gate MOSFET of the present invention (VIII); Figure 9 is a schematic diagram of the fabrication process of the gate stress relief structure of the split-gate MOSFET of the present invention (IX); Figure 10 is a schematic diagram of the fabrication process of the gate stress relief structure of the split-gate MOSFET of the present invention (X); Figure 11 is a schematic diagram of the fabrication process of the gate stress relief structure of the split-gate MOSFET of the present invention (XI).

[0022] Explanation of reference numerals in the attached figures: 1. Semiconductor epitaxial layer; 11. Trench; 2. Gate insulating layer; 21. Mounting cavity; 22. Field oxide layer; 23. Gate oxide layer; 24. Polysilicon inter-oxide layer; 3. Gate conductive layer; 31. Bottom gate; 32. Top gate; 4. Buffer dielectric layer; 5. Hard mask layer; 6. Photoresist layer.

[0023] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0025] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0026] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the term "and / or" throughout the text includes three solutions; taking A and / or B as an example, it includes technical solution A, technical solution B, and a technical solution that simultaneously satisfies A and B. Furthermore, the technical solutions of various embodiments can be combined with each other, provided that they are feasible for those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0027] In this embodiment of the invention, as shown in FIG11, the gate stress relief structure of the split-gate MOSFET includes a semiconductor epitaxial layer 1, a gate insulating layer 2, and at least one gate conductive layer 3; the semiconductor epitaxial layer 1 is formed with a trench 11; the gate insulating layer 2 is disposed in the trench 11, and at least one mounting cavity 21 is formed in the gate insulating layer 2, and different mounting cavities 21 are not interconnected; the number of gate conductive layers 3 is the same as the number of mounting cavities 21 to correspond one-to-one, and the gate conductive layer 3 is disposed in the corresponding mounting cavity 21; wherein, a buffer dielectric layer 4 is provided between the outer surface of each gate conductive layer 3 and the inner wall surface of the corresponding mounting cavity 21, and the thermal expansion coefficient of the buffer dielectric layer 4 is less than the thermal expansion coefficient of the gate conductive layer 3.

[0028] In this embodiment, the semiconductor epitaxial layer 1 can be understood as the semiconductor layer in the device used to form the active working region. It is both the basis for the formation of the trench 11 structure and an important region for carrying the electric field distribution and current transmission during the device's turn-on and turn-off processes. The semiconductor epitaxial layer 1 can be a silicon epitaxial layer, or it can be formed using semiconductor materials such as silicon carbide, germanium, or silicon-germanium, depending on the device type, voltage rating, or process platform. In power MOSFET applications, the semiconductor epitaxial layer 1 is usually preferably a silicon epitaxial layer because silicon-based processes are mature, device manufacturing costs are low, and it is easy to be compatible with existing trench 11 MOS processes. Of course, any semiconductor material that can form the trench 11 and complete the subsequent gate structure construction can be used as the implementation form of the semiconductor epitaxial layer 1.

[0029] The trench 11 can be understood as a recessed structure extending from the surface of the semiconductor epitaxial layer 1 into its interior, used to accommodate the gate-related structures within the trench 11. The trench 11 not only serves a geometrical containment function, but more importantly, it defines the relative spatial position between the gate structure and the semiconductor region, enabling the gate to effectively control the channel region near the sidewalls of the trench 11. In this embodiment, the trench 11 can be a strip trench 11, an annular trench 11, a mesh trench 11, or other trench 11 forms suitable for the repeated arrangement of power MOSFET cells. The cross-sectional shape of the trench 11 can be approximately rectangular, rounded rectangular, trapezoidal, or other cross-sectional shapes formed by etching processes.

[0030] A gate insulating layer 2 is disposed within the trench 11. The gate insulating layer 2 can be understood as an insulating dielectric structure deposited on the trench wall region of the trench 11, used to electrically isolate the gate conductive layer 3 from the semiconductor epitaxial layer 1. Since the gate and semiconductor body in a MOS device need to maintain an insulating relationship so that channel conduction is controlled by an electric field rather than forming a direct conductive connection, the gate insulating layer 2 is a key component in this type of device. In this solution, the gate insulating layer 2 not only has an insulating function but also further participates in defining the boundary of the mounting cavity 21. The gate conductive layer 3, subsequently disposed within the mounting cavity 21, is at least separated from the semiconductor epitaxial layer 1 by the gate insulating layer 2. The gate insulating layer 2 can be composed of a single insulating dielectric layer or two or more insulating dielectric layers. For example, in a specific implementation, the gate insulating layer 2 may include a silicon oxide layer or a composite insulating system composed of a field oxide layer 22, a gate oxide layer 23, and a polysilicon inter-oxide layer 24. As long as it serves to insulate and define the mounting cavity 21 as a whole, it can be considered as the gate insulating layer 2 described in this solution.

[0031] Different mounting cavities 21 are not interconnected. The mounting cavity 21 described here can be understood as the internal space surrounded or defined by the gate insulating layer 2, used to accommodate the gate conductive layer 3. The general term "mounting cavity 21" is used to accommodate different implementations of a single gate conductive layer 3 or multiple gate conductive layers 3. When only one gate conductive layer 3 is provided inside the trench 11, one mounting cavity 21 can be formed within the gate insulating layer 2; when multiple mutually insulated gate conductive layers 3 are provided along the depth direction inside the trench 11, multiple mutually separated mounting cavities 21 can be formed within the gate insulating layer 2, each mounting cavity 21 accommodating its corresponding gate conductive layer 3. The fact that different mounting cavities 21 are not interconnected means that there is an insulating dielectric space between adjacent mounting cavities 21, thus allowing the gate conductive layers 3 within different mounting cavities 21 to be spatially and electrically separated. For split-gate MOSFETs, this arrangement is beneficial for forming multiple gate-related structures separated vertically within the same trench 11, to meet the construction requirements of split-gate devices.

[0032] The gate conductive layer 3 can be understood as a conductive material layer that forms the gate function. It is used to establish an electric field when an external gate voltage is applied and acts on the channel region in the semiconductor epitaxial layer 1 through the gate insulating layer 2. The material of the gate conductive layer 3 can be polysilicon, or it can be doped polysilicon, metal, metal alloy, metal compound, or other conductive materials suitable for forming the gate. For example, in some embodiments, the gate conductive layer 3 can be formed using doped polysilicon to take into account mature processes and good filling ability; in other embodiments, it can also be formed using metal gate materials to meet different device performance requirements. The number of gate conductive layers 3 is the same as the number of mounting cavities 21 and corresponds one-to-one. This means that an independent gate conductive layer 3 is provided in each mounting cavity 21, thereby enabling the formation of one or more gate structures that are separate from each other.

[0033] The buffer dielectric layer 4 is located between the gate conductive layer 3 and the gate insulating layer 2, situated on the stress transmission path of the gate interface inside the trench 11. The buffer dielectric layer 4 can be a single continuous dielectric layer or composed of multiple dielectric films. As long as it is situated between the gate conductive layer 3 and the inner wall of the mounting cavity 21 and functions as a buffer, it can be considered the buffer dielectric layer 4 in this design. The material of the buffer dielectric layer 4 can be selected from a wide range of options, such as silicon nitride, silicon oxynitride, silicon oxynitride, or aluminum oxide. These materials have low coefficients of thermal expansion and can be formed into thin and uniform dielectric layers using existing thin-film deposition processes. Of course, this design is not limited to the materials listed above. Any material whose coefficient of thermal expansion is lower than that of the gate conductive layer 3 and can remain stable during device fabrication can also be used as the implementation of the buffer dielectric layer 4.

[0034] Split-gate MOSFETs typically undergo high-temperature processes such as oxidation, deposition, and annealing during manufacturing. In actual use, they experience repeated heating and cooling due to conduction losses, switching losses, and changes in ambient temperature. The gate conductive layer 3, gate insulating layer 2, and semiconductor epitaxial layer 1 within the trench 11 all undergo dimensional changes with temperature variations, but the expansion and contraction rates of different materials are not consistent. If the thermal dimensional change of the gate conductive layer 3 is significant, and its outer surface is adjacent to the gate insulating layer 2, the dimensional mismatch caused by temperature changes can easily translate into localized compression or stretching at the interface, acting on the vicinity of the gate insulating layer 2. The gate insulating layer 2 is usually thin and provides the insulation required for gate control; therefore, it is highly sensitive to interface stress. Long-term repeated mechanical action can easily lead to increased interface defects, decreased insulation performance, or reduced reliability.

[0035] After adding a buffer dielectric layer 4 with a lower coefficient of thermal expansion between the gate conductive layer 3 and the inner wall of the mounting cavity 21, the interface relationship inside the trench 11 changes. When the temperature rises, although the gate conductive layer 3 still tends to expand, its outer side is no longer directly adjacent to the gate insulating layer 2, but instead first contacts the buffer dielectric layer 4 with a lower coefficient of thermal expansion. Therefore, the dimensional changes of the gate conductive layer 3 are first transitioned and dispersed within the region where the buffer dielectric layer 4 is located. When the temperature decreases, the contraction tendency of the gate conductive layer 3 is also no longer directly applied to the gate insulating layer 2, but is released through the buffer dielectric layer 4. In this way, the thermal mismatch effect, which was originally easily concentrated near the gate insulating layer 2, is transferred to a specially designed transition layer, thereby reducing the mechanical burden on the gate insulating layer 2. The reason for requiring the coefficient of thermal expansion of the buffer dielectric layer 4 to be lower than that of the gate conductive layer 3 is to ensure that the buffer dielectric layer 4 maintains a smaller dimensional change trend relative to the gate conductive layer 3 during temperature changes, thereby creating a more significant deformation gradient adjustment effect between the two. If the buffer dielectric layer 4 and the gate conductive layer 3 have similar or even larger coefficients of thermal expansion, the intermediate layer will have difficulty effectively constraining the thermal dimensional changes of the gate conductive layer 3, and the buffering effect will be significantly weakened.

[0036] From the perspective of device usage, when the split-gate MOSFET is in the off state, the gate conductive layer 3 remains insulated from the semiconductor epitaxial layer 1, and a corresponding electric field distribution is established inside the device. When a control voltage is applied to the gate to turn the device on, a controlled conductive channel is formed in the semiconductor region near the trench 11, and current flows inside the device. Regardless of whether it is in the on or off state, the device may experience temperature fluctuations due to operating current, switching process, and environmental conditions. Therefore, the materials in the trench 11 do not only have thermal stress problems during the manufacturing stage, but may repeatedly undergo thermal cycling throughout the entire life cycle. Arranging the buffer dielectric layer 4 between each gate conductive layer 3 and the inner wall of the corresponding mounting cavity 21 means that each gate structure has its own stress relief interface. This layout ensures that whether there is one gate conductive layer 3 or multiple gate conductive layers 3 separated from each other inside the trench 11, each conductive layer has a similar buffering relationship with the surrounding insulating structure, thereby reducing the possibility of stress concentration points forming in local areas and helping to maintain the stability of the insulating interface inside the trench 11.

[0037] It should be noted that the specific dimensions, materials, and formation methods of the semiconductor epitaxial layer 1, gate insulating layer 2, mounting cavity 21, gate conductive layer 3, and buffer dielectric layer 4 can be adjusted according to different device voltage ratings, cell densities, and process platforms. For example, the trench depth 11, the number of mounting cavities 21, the material type of the gate conductive layer 3, and the thickness of the buffer dielectric layer 4 can all be determined according to actual design requirements. As long as the overall structure satisfies the following relationship: at least one mounting cavity 21 is formed within the trench 11 by the gate insulating layer 2; a corresponding gate conductive layer 3 is provided within each mounting cavity 21; and a buffer dielectric layer 4 with a lower coefficient of thermal expansion is provided between each gate conductive layer 3 and the inner wall of the corresponding mounting cavity 21, the gate stress relief objective described in this solution can be achieved.

[0038] Optionally, the trench 11 has a depth direction and a width direction perpendicular to the depth direction. In the width direction, each of the gate conductive layers 3 has two oppositely disposed side surfaces. The buffer dielectric layer 4 is disposed between the two side surfaces of the gate conductive layer 3 and the inner wall of the corresponding mounting cavity 21, and extends continuously along the side surfaces.

[0039] Specifically, since the trench 11 typically extends in a strip or near-strip shape, the two side surfaces of the gate conductive layer 3 can be understood as sidewall surfaces extending along the length of the trench 11, which mainly correspond to the sidewall regions of the trench 11.

[0040] In this embodiment, a buffer dielectric layer 4 is disposed between the two side surfaces of the gate conductive layer 3 and the inner wall of the corresponding mounting cavity 21, and extends continuously along the side surfaces. In other words, the buffer dielectric layer 4 is not formed only in a local area, but is formed as a continuous dielectric layer along the side wall interface of the gate conductive layer 3, so that the two sides of the gate conductive layer 3 in the width direction maintain a buffer dielectric layer 4 spacing relationship with the inner wall of the mounting cavity 21. The continuous extension of the buffer dielectric layer 4 along the side surfaces also means that the dielectric layer can form a continuous coverage in the depth direction of the trench 11, so that the gate conductive layer 3 is isolated by the buffer dielectric layer 4 throughout the entire height range of the side wall region of the trench 11.

[0041] The structure of continuously arranged buffer dielectric layers 4 on both side surfaces facilitates the formation of a more uniform stress transition interface within the trench 11. Since the gate conductive layer 3 may expand or contract in the width direction during temperature changes, if the buffer dielectric layer 4 is only placed in localized areas, the stress distribution at different locations may differ, leading to localized stress concentration. However, when the buffer dielectric layer 4 extends continuously along both side surfaces, the dimensional changes in the gate conductive layer 3 in the width direction can be simultaneously transitioned and released through the buffer dielectric layers 4 on both sides, resulting in a more balanced stress distribution at the interface between the gate conductive layer 3 and the inner wall of the mounting cavity 21. Consequently, the mechanical forces generated by the gate structure inside the trench 11 during temperature changes can be dispersed and transmitted at the sidewall interface, reducing the concentrated effect on localized areas of the gate insulating layer 2 and helping to maintain the stability of the insulating interface inside the trench 11.

[0042] Preferably, the thickness of the buffer medium layer 4 is 20 Å to 200 Å.

[0043] In specific implementations, the thickness of the buffer dielectric layer 4 can be 20 Å, 30 Å, 40 Å, 50 Å, 60 Å, 70 Å, 80 Å, 90 Å, 100 Å, 110 Å, 120 Å, 130 Å, 140 Å, 150 Å, 160 Å, 170 Å, 180 Å, 190 Å, or 200 Å, or any appropriate value between these values, such as 45 Å, 65 Å, 85 Å, 95 Å, 105 Å, 125 Å, 145 Å, or 175 Å. By selecting within this thickness range, the buffer dielectric layer 4 can maintain good continuity while occupying a small space in the trench 11. This allows for the formation of a stable buffer interface between the gate conductive layer 3 and the inner wall of the mounting cavity 21 without significantly affecting the overall layout of the gate structure within the trench 11.

[0044] Optionally, there are two gate conductive layers 3, and the two gate conductive layers 3 are spaced apart in the depth direction of the trench 11.

[0045] The depth direction described in this embodiment refers to the direction extending from the opening of the trench 11 toward the interior of the semiconductor epitaxial layer 1, that is, the direction in which the trench 11 extends downward from its surface. When the two gate conductive layers 3 are arranged along this direction, one gate conductive layer 3 is located in the lower region of the trench 11, and the other gate conductive layer 3 is located in the upper region of the trench 11. The two are spatially separated from each other, with a certain gap between them. This gap can be filled with an insulating dielectric structure, thereby making the two gate conductive layers 3 electrically insulated from each other while maintaining a stable layered relationship in structure.

[0046] By setting two gate conductive layers 3 that are separated from each other along the depth direction of the trench 11, a split gate structure can be formed inside the same trench 11. Compared with the trench 11 gate structure with only a single gate conductive layer 3, this dual-gate structure distributed along the depth direction can form different functional regions inside the trench 11. For example, the gate conductive layer 3 located in the upper region of the trench 11 is closer to the opening of the trench 11 and is usually adjacent to the channel formation region, used to control the conduction and turn-off of the channel; while the gate conductive layer 3 located in the lower region of the trench 11 is located deeper in the trench 11, and its spatial relationship with the semiconductor epitaxial layer 1 is different, so it can participate in adjusting the electric field distribution or forming an additional shielding structure inside the trench 11. Through this upper and lower separated gate layout, the electrical characteristics of the device can be more finely adjusted while maintaining the compact structure of the trench 11.

[0047] Optionally, the gate conductive layer 3 closer to the bottom of the trench 11 is defined as the bottom gate 31, and the gate conductive layer 3 farther from the bottom of the trench 11 is defined as the top gate 32; the trench 11 has a width direction perpendicular to its depth direction; the dimension of the top gate 32 in the width direction is larger than the dimension of the bottom gate 31 in the width direction.

[0048] It is understandable that when a device undergoes heat treatment during manufacturing or experiences temperature changes during operation, the gate conductive layer 3 will typically undergo dimensional changes due to thermal expansion. The larger the lateral dimension of the gate conductive layer 3, the greater the overall deformation caused by its thermal expansion. If the upper and lower gate conductive layers 3 inside the trench 11 have the same lateral dimension, their thermal deformation trends during temperature changes will be similar, easily leading to a superposition effect in the middle region of the trench 11, thereby generating relatively concentrated mechanical stress near the adjacent insulating interface.

[0049] Optionally, the gate insulating layer 2 located between the bottom gate 31 and the trench wall 11 is a field oxide layer 22, and the gate insulating layer 2 located between the top gate 32 and the trench wall 11 is a gate oxide layer 23.

[0050] The gate insulating layer 2 between the field oxide layer 22 and the gate oxide layer 23 is a polysilicon inter-oxide layer 24.

[0051] The field oxide layer 22 is located at a deeper position in the trench 11, between the bottom gate 31 and the trench wall of the trench 11. Its main function is to provide insulation and electric field regulation. Since this area does not usually participate directly in channel control, but mainly undertakes structural isolation and electric field distribution regulation, the field oxide layer 22 has a relatively large thickness to enhance insulation capability and improve structural stability.

[0052] The gate oxide layer 23 is located in the upper region of the trench 11, between the top gate 32 and the trench wall 11. This oxide layer directly participates in the gate control function of the MOS structure. When a voltage is applied to the gate, the electric field acts on the channel region in the semiconductor epitaxial layer 1 through the gate oxide layer 23, thereby controlling the on and off states of the device. Therefore, the gate oxide layer 23 needs to have high interface quality and stable electrical characteristics to ensure the gate control performance of the device.

[0053] The polysilicon inter-oxide layer 24 is located between the bottom gate 31 and the top gate 32. Its main function is to electrically insulate the two gate conductive layers 3, so that a split gate structure is formed inside the trench 11. By setting this insulating layer, the bottom gate 31 and the top gate 32 can be electrically kept independent of each other, thereby forming a split gate structure inside the same trench 11.

[0054] Thus, a field oxide layer 22, a polysilicon interphase oxide layer 24, and a gate oxide layer 23 are sequentially formed along the depth direction of the trench 11, creating a clearly partitioned insulating structure within the trench 11. The field oxide layer 22 primarily serves as insulation and electric field modulation, the polysilicon interphase oxide layer 24 provides electrical isolation between the upper and lower gates, and the gate oxide layer 23 forms the gate control interface. This partitioned insulating structure allows for simultaneous gate control, electrical isolation, and structural isolation functions within the trench 11.

[0055] Preferably, the thickness of the field oxide layer 22 is 500 Å to 3000 Å.

[0056] The thickness of the gate oxide layer 23 is 500 Å to 1200 Å.

[0057] The thickness of the polycrystalline silicon inter-oxide layer 24 is 1500 Å to 4000 Å.

[0058] In specific implementations, the thickness of the field oxide layer 22 can be 500 Å, 800 Å, 1000 Å, 1200 Å, 1500 Å, 1800 Å, 2000 Å, 2200 Å, 2500 Å, 2800 Å or 3000 Å, or any appropriate value between the above values ​​can be selected, such as 900 Å, 1300 Å, 1700 Å, 2100 Å or 2600 Å.

[0059] The thickness of the gate oxide layer 23 can be 500 Å, 600 Å, 700 Å, 800 Å, 900 Å, 1000 Å, 1100 Å or 1200 Å, or any appropriate value between the above values, such as 550 Å, 650 Å, 750 Å, 850 Å, 950 Å or 1050 Å.

[0060] The thickness of the polycrystalline silicon inter-oxide layer 24 can be 1500 Å, 1800 Å, 2000 Å, 2200 Å, 2500 Å, 2800 Å, 3000 Å, 3200 Å, 3500 Å, 3800 Å or 4000 Å, or any appropriate value between the above values, such as 1700 Å, 2100 Å, 2400 Å, 2700 Å, 3100 Å or 3600 Å.

[0061] This invention also proposes a method for fabricating a split-gate MOSFET, used to fabricate the gate stress relief structure of the aforementioned split-gate MOSFET. The method includes: providing a semiconductor epitaxial layer 1 and forming a trench 11 in the semiconductor epitaxial layer 1; forming a field oxide layer 22 on the trench wall of the trench 11 and forming a buffer dielectric layer 4 on the surface of the field oxide layer 22; filling the trench 11 with a gate conductive material and removing excess gate conductive material outside the trench 11 to form a bottom gate 31; and etching back the structure within the trench 11 to form the bottom gate 31. A space is formed above the bottom gate 31; an oxide layer is filled in the trench 11, and the filled oxide layer is etched back so that a portion of the oxide layer above the bottom gate 31 is retained as a polysilicon inter-oxide layer 24, and a space is formed above the polysilicon inter-oxide layer 24; a gate oxide layer 23 is formed on the sidewall of the trench 11 located above the polysilicon inter-oxide layer 24, and a buffer dielectric layer 4 is formed on the surface of the gate oxide layer 23; a gate conductive material is filled in the upper part of the trench 11, and excess gate conductive material outside the trench 11 is removed to form the top gate 32.

[0062] Specifically, in some embodiments, the semiconductor epitaxial layer 1 can be formed on a semiconductor substrate, and its material can be a silicon epitaxial layer, or silicon carbide, silicon germanium, or other semiconductor materials suitable for power device manufacturing, depending on the device type. The semiconductor epitaxial layer 1 is formed by an epitaxial growth process, for example, a chemical vapor deposition process can be used to grow an epitaxial layer with a predetermined thickness and doping concentration on the substrate surface.

[0063] After the semiconductor epitaxial layer 1 is formed, a hard mask layer 5 can be deposited on the surface of the semiconductor epitaxial layer 1. The hard mask layer 5 can be formed by chemical vapor deposition, and its material can be silicon oxide, silicon nitride, or other dielectric materials with a high etching selectivity. The thickness can be selected according to the etching depth of the trench 11, for example, it can be 0.2 μm to 2 μm. The hard mask layer 5 is mainly used to provide a stable pattern protection layer during the subsequent etching process of the trench 11, so that the etching process of the trench 11 can maintain good pattern accuracy under high etching depth conditions.

[0064] Referring to Figure 1, a photoresist layer 6 can be formed on the surface of the hard mask layer 5, and the trench 11 pattern can be transferred into the photoresist layer 6 through a photolithography process. Specifically, photoresist can be spin-coated onto the surface of the hard mask layer 5 to form a uniformly covering photoresist film layer on the surface of the hard mask layer 5; then, an exposure process is used to cause the photoresist to undergo chemical changes according to the preset photomask pattern, and a development process is used to remove the unretained photoresist areas, thereby forming patterned openings in the photoresist layer 6 corresponding to the trench 11 structure.

[0065] Referring to Figure 2, after the photoresist pattern is formed, it can be transferred to the hard mask layer 5 using a dry etching process. During the dry etching process, the areas of the hard mask layer 5 not covered by the photoresist are etched away, thereby forming an opening structure in the hard mask layer 5 corresponding to the photoresist pattern. After this step is completed, a pattern structure corresponding to the location of the target trench 11 is formed in the hard mask layer 5, while the photoresist layer 6 remains on the surface of the hard mask layer 5 as a temporary mask layer.

[0066] Referring to Figure 3, the photoresist layer 6 can then be removed, leaving only the hard mask layer 5 with the patterned openings. The semiconductor epitaxial layer 1 is then etched using a dry etching process, further transferring the opening pattern in the hard mask layer 5 into the semiconductor epitaxial layer 1, thereby forming a trench 11 structure in the semiconductor epitaxial layer 1. The etching depth can be controlled according to the device structure design; for example, the trench 11 depth can be 0.9 μm to 5 μm, allowing the trench 11 to extend from the surface of the semiconductor epitaxial layer 1 into its interior.

[0067] Referring to Figure 4, after the trench 11 structure is formed, a field oxide layer 22 can be formed in the trench wall region of the trench 11, and a buffer dielectric layer 4 can be formed on the surface of the field oxide layer 22. In specific implementation, the hard mask layer 5 used for etching the trench 11 in the previous process can be removed first, so that the sidewalls of the trench 11 are fully exposed. The hard mask layer 5 can be removed by wet etching or dry etching. For example, when the hard mask layer 5 is made of silicon oxide or silicon nitride, it can be removed by a corresponding selective etching process, thereby exposing the surface of the semiconductor epitaxial layer 1 in the sidewall region of the trench 11, providing an interface for the subsequent formation of the insulating layer.

[0068] Referring to Figure 4, after the hard mask layer 5 is removed, a field oxide layer 22 can be formed on the surface of the trench wall 11. This field oxide layer 22 can be uniformly deposited on the inner wall of the trench 11 using a chemical vapor deposition (CVD) process, or it can be formed using a thermal oxidation process depending on process requirements. When using CVD, an oxide dielectric layer, such as a silicon oxide layer, can be deposited on the sidewalls and bottom of the trench 11, thereby forming a continuously covering insulating layer structure on the trench wall region. By controlling the deposition time and process parameters, the field oxide layer 22 can be formed to a predetermined thickness; for example, the thickness of the field oxide layer 22 can be controlled within the range of 500 Å to 3000 Å. This field oxide layer 22 is located between the sidewall of the trench 11 and the subsequently formed bottom gate 31. Its main function is to provide a stable insulating environment in the deep region of the trench 11, while also playing a certain role in regulating the electric field distribution inside the trench 11.

[0069] Referring to Figure 5, after the field oxide layer 22 is formed, a buffer dielectric layer 4 can be further formed on the surface of the field oxide layer 22. The buffer dielectric layer 4 can be uniformly deposited on the surface of the field oxide layer 22 by chemical vapor deposition, thereby forming a thin transition dielectric film between the field oxide layer 22 and the subsequently formed gate conductive layer 3. By controlling the deposition process parameters, the thickness of the buffer dielectric layer 4 can be kept within a thin range, for example, it can be controlled within 20 Å to 200 Å. Since the buffer dielectric layer 4 has a low coefficient of thermal expansion, when it is placed between the field oxide layer 22 and the gate conductive layer 3, it can form a transition interface between the two, so that the dimensional changes of the gate conductive layer 3 during temperature changes do not directly affect the field oxide layer 22, thereby forming an interface structure with stress relief effect in the sidewall region of the trench 11. By forming this buffer dielectric layer 4 on the surface of the field oxide layer 22, a stable interface environment can be provided for the subsequent formation of the bottom gate 31 structure.

[0070] Referring to Figure 6, after the field oxide layer 22 and the buffer dielectric layer 4 are formed, gate conductive material can be filled into the trench 11 to form a gate conductive structure located inside the trench 11. Specifically, gate conductive material, such as polysilicon, can be deposited into the trench 11 using a chemical vapor deposition process. Since chemical vapor deposition typically lacks region selectivity, during the deposition process, not only is the inside of the trench 11 filled with gate conductive material, but a continuously deposited conductive material layer is also formed on the surface of the semiconductor epitaxial layer 1. By controlling the deposition time and process parameters, the gate conductive material can be fully filled into the trench 11, thereby avoiding the formation of voids or unfilled areas within the trench 11.

[0071] After trench 11 is filled, excess gate conductive material in the outer region of trench 11 can be removed by chemical mechanical polishing (CMP). During CMP, the gate conductive material deposited on the surface of the epitaxial layer is gradually removed, while the gate conductive material inside trench 11 is retained due to the constraint of the trench 11 structure, thus forming a filled gate conductive layer 3 inside trench 11. After this step, excess conductive material on the outer surface of trench 11 is removed, and the conductive material retained inside trench 11 constitutes the initial gate structure.

[0072] Referring to Figure 7, after forming the aforementioned gate conductive structure, the structure inside the trench 11 can be etched back to create a space above the bottom gate 31. Specifically, a dry etching process can be used to etch the internal structure of the trench 11, removing material to a certain depth in the upper region of the trench 11. During etching, the gate conductive material inside the trench 11 and the insulating structure on its outer side, such as the field oxide layer 22 and the buffer dielectric layer 4, can be etched simultaneously, causing the material in the upper region of the trench 11 to recede downwards as a whole. By controlling the etching time and etching rate, the etching depth can be reached to a predetermined position, thereby forming a cavity region of a certain height above the bottom gate 31.

[0073] Referring to Figure 8, after the bottom gate 31 is formed and a space is created above it using a etch-back process, an insulating layer for separating the upper and lower gate structures can be constructed inside the trench 11. Specifically, an oxide dielectric layer, such as a silicon oxide layer, can first be filled inside the trench 11 using a high-density plasma chemical vapor deposition (PDCVD) process. PDCVD has good trench 11 filling capability, allowing the oxide dielectric to fully fill the cavity region inside the trench 11. Since this deposition process also lacks region selectivity, an additional oxide dielectric layer is formed on the surface of the semiconductor epitaxial layer 1 while the oxide layer is filled inside the trench 11. Subsequently, the excess oxide layer on the epitaxial layer surface can be removed using a chemical mechanical polishing (CMP) process, leaving the filled oxide dielectric inside the trench 11 while restoring the surface of the epitaxial layer to a smooth state.

[0074] Referring to Figure 9, after the trench 11 is filled with an oxide layer, the oxide layer inside the trench 11 can be etched back using a combination of dry etching and photolithography. During the etching process, by controlling the etching depth, a certain thickness of the oxide layer filling the trench 11 is etched away in the upper region. For example, the etching depth can be controlled within the range of approximately 0.5 μm to 1 μm, thereby reforming the cavity structure in the upper part of the trench 11. Simultaneously, a certain thickness of oxide layer is retained in the bottom region inside the trench 11 as the polysilicon inter-oxide layer 24. The polysilicon inter-oxide layer 24 is located above the bottom gate 31, and its thickness can be controlled within the range of 1500 Å to 4000 Å. Through this step, an insulating isolation structure can be established between the bottom gate 31 and the subsequently formed top gate 32, ensuring that the two gate conductive layers 3 remain electrically independent of each other.

[0075] Referring to Figure 10, after forming the polysilicon inter-oxide layer 24 and creating a cavity thereon, a gate oxide layer 23 can be formed on the sidewall of the trench 11 located above the polysilicon inter-oxide layer 24. The gate oxide layer 23 can be grown on the surface of the trench 11 sidewall using a thermal oxidation process, thereby forming the insulating interface required for gate control in the upper region of the trench 11. By controlling the oxidation process conditions, the gate oxide layer 23 can be formed to a predetermined thickness, for example, the thickness of the gate oxide layer 23 can be controlled in the range of 500 Å to 1200 Å. After the gate oxide layer 23 is formed, a buffer dielectric layer 4 can be further deposited on the surface of the gate oxide layer 23 using a chemical vapor deposition process. This buffer dielectric layer 4 can be formed as a relatively thin dielectric film, for example, the thickness can be controlled in the range of 20 Å to 200 Å, thereby forming a stress-relieving interface between the gate conductive material and the gate oxide layer 23.

[0076] Referring to Figure 11, the upper region of trench 11 can then be filled with gate conductive material to form the top gate 32. Specifically, a gate conductive material, such as polysilicon or other conductive material, can be deposited into the trench 11 using a chemical vapor deposition process to fill the cavity region formed in the upper part of trench 11. Since this deposition process also lacks region selectivity, a conductive material layer is deposited on the epitaxial layer surface while the trench 11 is filled with conductive material. Excess conductive material on the epitaxial layer surface can then be removed using a chemical mechanical polishing process, removing the conductive material from the outer region of trench 11 while retaining the filled conductive material inside trench 11, thereby forming the top gate 32 in the upper part of trench 11. Because a polysilicon inter-oxide layer 24 is disposed between the bottom gate 31 and the top gate 32, they are electrically insulated from each other, thus forming a separated gate structure within the same trench 11.

[0077] After the top gate 32 is formed, subsequent processing steps can be carried out according to the conventional process of split-gate MOSFET, such as the formation of the gate lead structure, the formation of the metal interconnect structure on the front side of the device, and the chip back thinning and back metallization, to complete the entire manufacturing process of the split-gate MOSFET device.

[0078] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A gate stress relief structure for a split-gate MOSFET, characterized in that, include: A semiconductor epitaxial layer (1) has trenches (11) formed thereon; A gate insulating layer (2) is disposed in the trench (11), and at least one mounting cavity (21) is formed in the gate insulating layer (2), and different mounting cavities (21) are not interconnected; at least one gate conductive layer (3) is disposed in the corresponding mounting cavity (21), the number of gate conductive layers (3) is the same as the number of mounting cavities (21) to correspond one-to-one, and the gate conductive layer (3) is disposed in the corresponding mounting cavity (21); wherein, a buffer dielectric layer (4) is provided between the outer surface of each gate conductive layer (3) and the inner wall surface of the corresponding mounting cavity (21), and the thermal expansion coefficient of the buffer dielectric layer (4) is less than the thermal expansion coefficient of the gate conductive layer (3).

2. The gate stress relief structure of the split-gate MOSFET according to claim 1, characterized in that, The trench (11) has a depth direction and a width direction perpendicular to the depth direction. In the width direction, each gate conductive layer (3) has two side surfaces disposed opposite to each other. The buffer dielectric layer (4) is disposed between the two side surfaces of the gate conductive layer (3) and the inner wall of the corresponding mounting cavity (21), and extends continuously along the side surfaces.

3. The gate stress relief structure of the split-gate MOSFET according to claim 1, characterized in that, The thickness of the buffer medium layer (4) is 20 Å to 200 Å.

4. The gate stress relief structure of the split-gate MOSFET according to claim 1, characterized in that, The material of the buffer medium layer (4) is selected from one or more of silicon nitride, silicon oxynitride, silicon oxynitride, or aluminum oxide.

5. The gate stress relief structure of the split-gate MOSFET according to any one of claims 1 to 4, characterized in that, The number of gate conductive layers (3) is two, and the two gate conductive layers (3) are spaced apart in the depth direction of the trench (11).

6. The gate stress relief structure of the split-gate MOSFET according to claim 5, characterized in that, The gate conductive layer (3) closer to the bottom of the trench (11) is defined as the bottom gate (31), and the gate conductive layer (3) farther from the bottom of the trench (11) is defined as the top gate (32); the trench (11) has a width direction perpendicular to its depth direction; the top gate (32) has a larger dimension in the width direction than the bottom gate (31) in the width direction.

7. The gate stress relief structure of the split-gate MOSFET according to claim 6, characterized in that, The gate insulating layer (2) located between the bottom gate (31) and the trench (11) wall is a field oxide layer (22), and the gate insulating layer (2) located between the top gate (32) and the trench (11) wall is a gate oxide layer (23).

8. The gate stress relief structure of the split-gate MOSFET according to claim 7, characterized in that, The gate insulating layer (2) between the field oxide layer (22) and the gate oxide layer (23) is a polysilicon inter-oxide layer (24).

9. The gate stress relief structure of the split-gate MOSFET according to claim 8, characterized in that, The thickness of the field oxide layer (22) is 500 Å to 3000 Å; and / or, the thickness of the gate oxide layer (23) is 500 Å to 1200 Å; and / or, the thickness of the polysilicon inter-oxide layer (24) is 1500 Å to 4000 Å.

10. A method for fabricating a split-gate MOSFET, characterized in that, The fabrication method is used to fabricate a gate stress relief structure of a split-gate MOSFET as described in any one of claims 1 to 8. The fabrication method includes: providing a semiconductor epitaxial layer (1) and forming a trench (11) in the semiconductor epitaxial layer (1); forming a field oxide layer (22) on the trench wall of the trench (11) and forming a buffer dielectric layer (4) on the surface of the field oxide layer (22); filling the trench (11) with gate conductive material and removing excess gate conductive material outside the trench (11) to form a bottom gate (31); and etching back the structure in the trench (11) to form the bottom gate (31). 1) A space is formed above; an oxide layer is filled in the trench (11), and the filled oxide layer is etched back so that a portion of the oxide layer above the bottom gate (31) is retained as a polysilicon inter-oxide layer (24), and a space is formed above the polysilicon inter-oxide layer (24); a gate oxide layer (23) is formed on the sidewall of the trench (11) located above the polysilicon inter-oxide layer (24), and a buffer dielectric layer (4) is formed on the surface of the gate oxide layer (23); a gate conductive material is filled in the upper part of the trench (11), and excess gate conductive material outside the trench (11) is removed to form a top gate (32).

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