Memory system and memory access interface device therefor

Abstract

A memory access interface device. A data processing circuit receives a data signal including 2M data from a memory device. A sampling clock pulse generating circuit receives a data strobe signal from the memory device to generate a valid data strobe signal including P valid strobe pulses and to generate a sampling clock pulse signal, where P is greater than M. A sampling circuit samples the data signal according to the sampling clock pulse signal to generate a sampling result. A control circuit sets a valid sampling result according to a time difference between the valid data strobe signal and the data signal, and outputs valid data generated according to the valid sampling result as a read data signal to a memory access controller.

Description

Technical Field

[0001] This invention relates to memory technology, and more particularly to a memory system and its memory interface device. Background Technology

[0002] Double data rate (DDR) memory quickly became the mainstream memory device due to its speed advantage. Current memory technology has evolved to high-speed architectures such as DDR5 and LPDDR5 (Low Power DDR5), which can support speeds of at least DDR-3200 (clock pulse frequency of 1600 MHz) and up to DDR-6400 (clock pulse frequency of 3200 MHz).

[0003] However, existing memory data read / write technologies are unsuitable for such high-speed memory transfers. This is because, with the significant increase in clock pulse frequency, the time skew between the internal data signal and the data strobe signal cannot be reduced, resulting in the data strobe signal lagging too far behind the data signal and failing to sample the data signal correctly. Therefore, a data read / write technology that can meet the read / write requirements of both high-speed and low-speed memories is urgently needed. Summary of the Invention

[0004] In view of the problems in the prior art, one object of the present invention is to provide a memory system and a memory access interface device thereof to improve the prior art.

[0005] One object of the present invention is to provide a memory access interface device, comprising: a data processing circuit, a sampling clock pulse generation circuit, a sampling circuit, and a control circuit. The data processing circuit is configured to receive and process a data signal containing multiple data items from a memory device, wherein the number of data items is 2M, and M is a positive integer. The sampling clock pulse generation circuit is configured to receive a data strobe signal from the memory device and process it to generate a valid data strobe signal containing multiple valid strobe pulses, thereby generating a plurality of sampling clock pulse signals of number 2N, wherein the number of valid strobe pulses is P, P is greater than M, and N and P are positive integers. The sampling circuit is configured to sample the processed data signal according to the sampling clock pulse signals to generate multiple sampling results. The control circuit is configured to: set the first part of the sampling result corresponding to the data signal as a plurality of valid sampling results based on the time difference between the valid data strobe signal and the data signal; and output the plurality of valid data generated based on the valid sampling results as read data signals to the memory access controller.

[0006] Another object of the present invention is to provide a memory system comprising: a memory access controller, a memory device, and a memory access interface device. The memory access interface device comprises: a data processing circuit, a sampling clock pulse generation circuit, a sampling circuit, and a control circuit. The data processing circuit is configured to receive and process a data signal containing multiple data from the memory device, wherein the number of data is 2M, and M is a positive integer. The sampling clock pulse generation circuit is configured to receive a data strobe signal from the memory device, process it to generate a valid data strobe signal containing multiple valid strobe pulses, and thereby generate a plurality of sampling clock pulse signals of number 2N, wherein the number of valid strobe pulses is P, P is greater than M, and N and P are positive integers. The sampling circuit is configured to sample the processed data signal according to the sampling clock pulse signals to generate multiple sampling results. The control circuit is configured to: set a first portion of the sampling result corresponding to the data signal as a plurality of valid sampling results based on the time difference between the valid data strobe signal and the data signal; and output the plurality of valid data generated based on the valid sampling results as read data signals to the memory access controller.

[0007] The features, implementation, and technical effects of the present invention are described in detail below with reference to the accompanying drawings and preferred embodiments. Attached Figure Description

[0008] Figure 1 A block diagram of a memory system according to an embodiment of the present invention is shown;

[0009] Figure 2 An embodiment of the present invention is shown. Figure 1 A more detailed block diagram of the memory access interface device;

[0010] Figure 3 This diagram illustrates a signal timing diagram related to a read operation of a memory access interface device according to an embodiment of the present invention.

[0011] Figure 4 This diagram illustrates a signal timing diagram related to a read operation of a memory access interface device according to another embodiment of the present invention.

[0012] Figure 5 This diagram illustrates a signal timing diagram related to a read operation of a memory access interface device according to another embodiment of the present invention; and

[0013] Figure 6 This diagram illustrates a signal timing diagram related to a read operation of a memory access interface device according to another embodiment of the present invention. Detailed Implementation

[0014] One object of the present invention is to provide a memory system and a memory access interface device thereof, which increases the sampling range by making the number of valid gating pulses of the valid data gating signal greater than the number of data in the data signal, thereby avoiding memory read errors caused by the time difference between the data signal and the data gating signal.

[0015] Please refer to Figure 1 . Figure 1 A block diagram illustrating a memory system 100 according to an embodiment of the present invention is shown. The memory system 100 includes a memory access controller 110, a memory access interface device 120, and a memory device 130.

[0016] The memory system 100 may be electrically coupled to other modules via, for example, but not limited to, a system bus (not shown). For example, the memory system 100 may be electrically coupled to a processor (not shown) via a system bus to enable the processor to access the memory system 100.

[0017] In one embodiment, the memory access interface device 120 may be, for example, but not limited to, physical layer circuitry.

[0018] Preferably, the memory device 130 is a memory that supports double data rate mode, such as DDR4, LPDDR4, DDR5, LPDDR5 and other memory devices.

[0019] External access signals, such as access signals from the processor, can be received by the memory access controller 110 and then transmitted to the memory access interface device 120. Further, the access signal can be transmitted from the memory access interface device 120 to the memory device 130, or the memory access interface device 120 can be used as a reference signal to access the memory device 130.

[0020] For example, the memory access controller 110 may receive and transmit access signals, which may include, for example, but not limited to, access instruction CMD and access address ADD.

[0021] Based on the aforementioned signals, the memory access interface device 120 can transmit access signals to activate the memory device 130, wherein the access signals may include, for example, but not limited to, access instruction CMD and access address ADD. The memory access interface device 120 then receives a data signal DQ and a data strobe signal DQS from the activated memory device 130, samples the data signal DQ according to the data strobe signal DQS to generate a read data signal RDQ, and transmits it to the memory access controller 110.

[0022] Therefore, the internal data stored in the memory device 130 can be accessed according to the correct timing of the above signals.

[0023] The memory access interface device 120 actually includes a receiver RX and a transmitter TX. The following paragraphs will describe the structure and operation of the receiver RX in more detail.

[0024] Please refer to the following at the same time Figure 2 as well as Figure 3 . Figure 2 An embodiment of the present invention is shown. Figure 1 A more detailed block diagram of the memory access interface device 120 is provided. It should be noted that... Figure 2 In this diagram, only the receiver RX of the memory access interface device 120 is shown, while the transmitter TX is not shown. Figure 3 This diagram illustrates a signal timing diagram related to a read operation of a memory access interface device 120 according to an embodiment of the present invention.

[0025] The memory access interface device 120 includes: a data processing circuit 200, a sampling clock pulse generation circuit 210, a sampling circuit 220, and a control circuit 230.

[0026] The data processing circuit 200 is configured to receive and process a data signal DQ containing multiple data from the memory device 120.

[0027] In one embodiment, the data processing circuit 200 is a decision feedback equalizer (DFE) to fine-tune the data signal DQ based on feedback information from the control circuit 230, such as, but not limited to, gain and phase adjustment processing, to reduce signal overshoot and undershoot, and to expand the signal eye diagram.

[0028] The data signal DQ contains 2M data points, where M is a positive integer. For example... Figure 3 As shown, the data signal DQ contains 8 data points D1 to D8. In this case, M is 4.

[0029] The sampling clock pulse generation circuit 210 is configured to receive the data strobe signal DQS from the memory device 130, process it to generate a valid data strobe signal DQSV containing multiple valid strobe pulses, and generate multiple sampling clock pulse signals CLK with a number of 2N, wherein the number of valid strobe pulses is P, P is greater than M, and N and P are positive integers.

[0030] The sampling clock pulse generation circuit 210 will be described in detail in stages below.

[0031] First, the sampling clock pulse generation circuit 210 receives the data strobe signal DQS from the memory device 130.

[0032] In one embodiment, the memory device 130 is an LPDDR4 memory device that supports additional gating functionality. In this case, the data gating signal DQS received by the sampling clock pulse generation circuit 210 has multiple gating pulses, and includes a tri-state preamble and a tri-state postamble before and after each gating pulse. The number of gating pulses is P, and the timing of the gating pulses precedes the data contained in the data signal DQ. P equals M+A, where P is a positive integer and A is a positive integer greater than or equal to 1.

[0033] In existing technologies, the number of gating pulses in the data strobe signal DQS is equal to the number of data pulses in the data signal DQ. However, due to the time difference between the data signal DQ and the data strobe signal DQS caused by the manufacturing process, and because high-speed LPDDR4 memory devices have shorter clock pulse periods (higher frequencies), the timing of the final sampling clock pulse signal is prone to lag behind the data signal DQ by more than 0.5 clock pulse periods, leading to errors in the sampled data.

[0034] Because the LPDDR4 memory device supports additional strobe functions, the memory device 130 can generate an additional number of strobe pulses than the number of data under the drive of, for example, but not limited to, the memory access interface device 120, and the timing of the strobe pulses precedes the data contained in the data signal DQ.

[0035] like Figure 3 As shown, in this embodiment, the data strobe signal DQS includes five strobe pulses SB1 to SB5, and their timing precedes that of the data signal DQ. In this case, P is 5 and A is 1. Furthermore, the data strobe signal DQS has a three-state preamble segment TS1 and a three-state postamble segment TS2 before and after the strobe pulses SB1 to SB5.

[0036] Next, the sampling clock pulse generation circuit 210 processes the data strobe signal DQS to generate a valid data strobe signal DQSV containing multiple valid strobe pulses, wherein the number of valid strobe pulses is P. Since P is M+A and A is a positive integer, P is greater than M.

[0037] More specifically, the sampling clock pulse generation circuit 210 eliminates the three-state preamble segment TS1 and the three-state postamble segment TS2 of the data strobe signal DQS, respectively, into a low-state preamble segment LP1 and a low-state postamble segment LP2, thereby generating a valid data strobe signal DQSV. In one embodiment, the sampling clock pulse generation circuit 210 can perform calculations through internally configured logic circuits to eliminate the three-state state to a low state.

[0038] like Figure 3 As shown, in this embodiment, the valid data strobe signal DQSV includes five valid strobe pulses SV1 to SV5. Each of the valid strobe pulses SV1 to SV5 has edges EG01 to EG10 (including positive and negative edges). The valid data strobe signal DQSV also has a low-state pre-leading segment LP1 and a low-state post-leading segment LP2 before and after the valid strobe pulses SV1 to SV5. However, since the valid data strobe signal DQSV must be processed by the sampling clock pulse generation circuit 210, its timing will lag behind that of the data strobe signal DQS.

[0039] In addition, the sampling clock pulse generation circuit 210 generates multiple sampling clock pulse signals CLK based on the valid data strobe signal DQSV, with a total number of 2N sampling clock pulse signals. N is a positive integer.

[0040] like Figure 3 As shown, in this embodiment, the sampling clock pulse signal CLK actually includes four sampling clock pulse signals CLK1 to CLK4, which are 90 degrees out of phase with each other. In this case, N is 4.

[0041] In one embodiment, the sampling clock pulse generation circuit 210 may also fine-tune the data strobe signal DQS based on feedback information from the control circuit 230 to adjust the timing of the generated sampling clock pulse signal CLK.

[0042] The sampling circuit 220 is configured to sample the processed data signal DQ according to the sampling clock pulse signal CLK to generate multiple sampling results SR. Since it is a double data rate, the sampling circuit 220 samples based on the positive and negative edges of the sampling clock pulse signals CLK1 to CLK4. Therefore, corresponding to the edges EG01 to EG10 of each valid strobe pulse SV1 to SV5, the sampling circuit 220 will generate four sampling results. Two of these sampling results will be used as data, and the other two will be used as edge information.

[0043] The control circuit 230 is configured to set a first portion of the sampling result SR corresponding to the data signal DQ as multiple valid sampling results SRV based on the time difference between the valid data strobe signal DQSV and the data signal DQ, and to set a second portion not corresponding to the data signal DQ as multiple invalid sampling results SRI. In one embodiment, the time difference between the valid data strobe signal DQSV and the data signal DQ can be obtained in advance by measurement, thereby determining the timing relationship between the edges EG01 to EG10 of the valid data strobe signal DQSV and the data signal DQ.

[0044] by Figure 3For example, among the edges EG01 to EG10 of the effective gating pulses SV1 to SV5, edges EG02 to EG09 correspond to the data signal DQ, while edges EG01 and EG10 do not correspond to the data signal DQ. Edges EG01 and EG10 are... Figure 3 The characters are marked with a cross.

[0045] Therefore, the sampling results generated by the edges EG02 to EG09 corresponding to the sampling clock pulse signals CLK1 to CLK4 correspond to the data signal DQ, and are set as valid sampling results SRV by the control circuit 230. The sampling results generated by the edges EG01 and EG10 corresponding to the sampling clock pulse signals CLK1 to CLK4 do not correspond to the data signal DQ, and are set as invalid sampling results SRI by the control circuit 230.

[0046] The control circuit 230 outputs multiple valid data signals, including a read data signal RDQ, generated based on the valid sampling result SRV, to the memory access controller 110, and discards multiple invalid data signals generated based on the invalid sampling result SRI. The control circuit 230 discards 2A of invalid data. Because... Figure 3 In the embodiment, A is 1, so the control circuit 230 discards two invalid data entries.

[0047] Please refer to Figure 4 . Figure 4 This diagram illustrates a signal timing diagram related to a read operation of a memory access interface device 120 according to another embodiment of the present invention. Figure 4 Only the data signal DQ and the valid data strobe signal DQSV are shown in the image.

[0048] and Figure 3 similar, Figure 4 The data signal DQ contains eight data points D1 to D8 (M is 4), and the data strobe signal DQS also contains five strobe pulses SB1 to SB5, with the timing preceding that of the data signal DQ. However, compared to... Figure 3 , Figure 4 The timing of the effective data strobe signal DQSV is further behind the data signal DQ because the timing of the data strobe signal DQS itself is more delayed, or because the processing time of the sampling clock pulse generation circuit 210 is longer.

[0049] Therefore, among the edges EG01 to EG10 of the effective gating pulses SV1 to SV5, edges EG01 to EG08 correspond to the data signal DQ, while edges EG09 and EG10 do not correspond to the data signal DQ. Edges EG09 and EG10 are... Figure 4 The characters are marked with a cross.

[0050] Therefore, the sampling results generated by the edges EG01 to EG08 corresponding to the sampling clock pulse signals CLK1 to CLK4 correspond to the data signal DQ, and are set as valid sampling results SRV by the control circuit 230. The sampling results generated by the edges EG09 and EG10 corresponding to the sampling clock pulse signals CLK1 to CLK4 do not correspond to the data signal DQ, and are set as invalid sampling results SRI by the control circuit 230.

[0051] The control circuit 230 outputs multiple valid data signals, including a read data signal RDQ, generated based on the valid sampling result SRV, to the memory access controller 110, and discards multiple invalid data signals generated based on the invalid sampling result SRI. The control circuit 230 discards 2A of invalid data. Because... Figure 4 In the embodiment, A is also 1, so the invalid data discarded by the control circuit 230 is also two.

[0052] Please refer to Figure 5 . Figure 5 This diagram illustrates a signal timing diagram related to a read operation of a memory access interface device 120, according to yet another embodiment of the present invention. Figure 4 The diagram shows only the data signal DQ, the data strobe signal DQS, and the active data strobe signal DQSV.

[0053] In one embodiment, the memory device 130 is an LPDDR5 memory device or a DDR5 memory device, supporting additional strobing functions. Due to their higher speed, LPDDR5 or DDR5 memory devices have shorter clock pulse periods (higher frequencies), resulting in the final sampled clock pulse signal lagging further behind the data signal DQ in timing.

[0054] Therefore, although with Figure 3 similar, Figure 5 The data signal DQ contains 8 data points D1 to D8 (M is 4), but the data strobe signal DQS contains 6 strobe pulses SB1 to SB6 (P is 6, A is 2), and their timing precedes that of the data signal DQ. The sampling clock pulse generation circuit 210 processes the data strobe signal DQS in the same way, generating a valid data strobe signal DQSV with valid strobe pulses SV1 to SV6, and the valid strobe pulses SV1 to SV6 have edges EG01 to EG12. Edges EG01 to EG08 correspond to the data signal DQ, while edges EG09 to EG12 do not correspond to the data signal DQ. Edges EG09 to EG12 are... Figure 5 The characters are marked with a cross.

[0055] Therefore, the sampling results generated by the edges EG01 to EG08 corresponding to the sampling clock pulse signals CLK1 to CLK4 correspond to the data signal DQ, and are set as valid sampling results SRV by the control circuit 230. The sampling results generated by the edges EG09 to EG12 corresponding to the sampling clock pulse signals CLK1 to CLK4 do not correspond to the data signal DQ, and are set as invalid sampling results SRI by the control circuit 230.

[0056] The control circuit 230 outputs multiple valid data signals, including a read data signal RDQ, generated based on the valid sampling result SRV, to the memory access controller 110, and discards multiple invalid data signals generated based on the invalid sampling result SRI. The control circuit 230 discards 2A of invalid data. Because... Figure 5 In the embodiment, A is 2, so the invalid data discarded by the control circuit 230 is also four.

[0057] Please refer to Figure 6 . Figure 6 This diagram illustrates a signal timing diagram related to a read operation of a memory access interface device 120 according to another embodiment of the present invention.

[0058] In one embodiment, the memory device 130 is a DDR4 memory device and does not support additional strobe functions.

[0059] and Figure 3 similar, Figure 6 The data signal DQ contains 8 data points D1 to D8 (M is 4). At this time, the sampling clock pulse generation circuit 210 receives a data strobe signal DQS containing M strobe pulses. Therefore, Figure 6 The data gating signal DQS has gating pulses SB1 to SB4, and before gating pulses SB1 to SB4, it has a three-state preamble segment TS1, a high-state preamble segment HP, and a first low-state preamble segment LA1 with a half-cycle, and after gating pulses SB1 to SB4, it has a three-state post-lead segment TS2.

[0060] The sampling clock pulse generation circuit 210 eliminates the tri-state preamble segment TS1 to generate the second low-state preamble segment LA2, and eliminates the tri-state postamble segment TS2 to generate the low-state postamble segment LA3, thus becoming... Figure 6 The data strobe signal DQS' is shown. The sampling clock pulse generation circuit 210 then inverts the data strobe signal DQS' to generate a valid data strobe signal DQSV containing multiple valid strobe pulses. At this time, the number of valid strobe pulses is P, and P equals M+0.5.

[0061] like Figure 6As shown, in this embodiment, the effective data gating signal DQSV includes four effective gating pulses SV1 to SV4, and also includes 0.5 gating pulses SV5 (P = 4.5) that are only in a high state. The effective gating pulses SV1 to SV5 have edges EG01 to EG9. Edges EG02 to EG09 correspond to the data signal DQ, while edge EG01 does not correspond to the data signal DQ. Edge EG01... Figure 6 The characters are marked with a cross.

[0062] Therefore, the sampling results generated by the edges EG02 to EG09 corresponding to the sampling clock pulse signals CLK1 to CLK4 correspond to the data signal DQ, and are set as valid sampling results SRV by the control circuit 230. The sampling results generated by the edge EG01 corresponding to the sampling clock pulse signals CLK1 to CLK4 do not correspond to the data signal DQ, and are set as invalid sampling results SRI by the control circuit 230.

[0063] The control circuit 230 outputs multiple valid data generated based on the valid sampling result SRV as a read data signal RDQ to the memory access controller 110, and discards multiple invalid data generated based on the invalid sampling result SRI. Among them, the control circuit 230 discards one invalid data.

[0064] It should be noted that, in Figure 6 In this embodiment, since the valid data strobe signal DQSV is generated by inverting the data strobe signal DQS', during the initial operation phase of the memory access interface device 120, the data strobe signal DQS', which should have remained low, will be inverted to become the high-state valid data strobe signal DQSV. If the sampling circuit 220 of the memory access interface device 120 receives this high state during the initial operation phase, it will incorrectly sample. Therefore, the sampling circuit 220 can be configured to not sample according to the sampling clock pulse signal during the initial operation phase, and to start sampling according to the sampling clock pulse signal after the initial operation phase ends.

[0065] In one embodiment, the sampling clock pulse generation circuit 210 generates 2N sampling clock pulse signals CLK, where N is a positive integer greater than one, so that the sampling result generated by the sampling circuit 220 includes edge information in addition to data. Therefore, based on the valid sampling result SRV and the invalid sampling result SRI, the control circuit 230 generates multiple valid edge information and multiple invalid edge information in addition to valid and invalid data. The control circuit 230 also outputs the valid data and valid edge information to the data processing circuit 200 and the sampling clock pulse generation circuit 210 as the aforementioned feedback information, enabling the data processing circuit 200 and the sampling clock pulse generation circuit to fine-tune the data signal DQ and the sampling clock pulse signal CLK.

[0066] It should be noted that the above-described embodiments are merely examples. In other embodiments, those skilled in the art can make changes without departing from the spirit of the invention.

[0067] In summary, the memory system and its memory access interface device of the present invention increase the sampling range by making the number of valid gating pulses of the valid data gating signal greater than the number of data in the data signal, thereby avoiding memory read errors caused by the time difference between the data signal and the data gating signal.

[0068] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention, and all such changes are within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention should be determined by the scope defined in the claims of this specification.

[0069] Figure Labels

[0070] 100: Memory System

[0071] 110: Memory Access Controller

[0072] 120: Memory access interface device

[0073] 130: Memory device

[0074] 200: Data processing circuit

[0075] 210: Sampling clock pulse generation circuit

[0076] 220: Sampling circuit

[0077] 230: Control Circuit

[0078] ADD: Access address

[0079] CLK, CLK1~CLK4: Sampling clock pulse signals

[0080] CMD: Access Command

[0081] D1~D8: Data

[0082] DQ: Data signal

[0083] DQS, DQS': Data strobe signals

[0084] DQSV: Valid Data Strobe Signal

[0085] EG01~EG12: Edge

[0086] HP: High-state leader segment

[0087] LA1: First low-state leader segment

[0088] LA2: Second low-state leader segment

[0089] LA3: Low-state lead segment

[0090] LP1: Low-state leader segment

[0091] LP2: Low-state lead segment

[0092] RDQ: Read data signal

[0093] RX: Receiver

[0094] SB1~SB6: Gating pulses

[0095] SRI: Invalid sampling result

[0096] SRV: Valid sampling results

[0097] SV1~SV6: Effective gating pulses

[0098] TX: Teleporter

[0099] TS1: Tri-state leading segment

[0100] TS2: Tri-state lead section

Claims

1. A memory access interface device, comprising: A data processing circuit is configured to receive and process a data signal containing multiple data from a memory device, wherein the number of data is 2M, and M is a positive integer. The sampling clock pulse generation circuit is configured to receive a data gating signal from the memory device, process it to generate a valid data gating signal containing multiple valid gating pulses, and generate multiple sampling clock pulse signals of number 2N, wherein the number of valid gating pulses is P, P is greater than M, and N and P are positive integers. The sampling circuit is configured to sample the processed data signal according to the sampling clock pulse signal to generate multiple sampling results; as well as The control circuit is configured as follows: Based on the time difference between the valid data strobe signal and the data signal, the first part of the sampling result corresponding to the data signal is set as multiple valid sampling results; as well as The output consists of multiple valid data generated based on the valid sampling results, which are read data signals sent to the memory access controller.

2. The memory access interface device according to claim 1, wherein when the memory device supports additional gating functions, the data gating signal received by the sampling clock pulse generation circuit has multiple gating pulses, and has a three-state preamble and a three-state postamble before and after the gating pulses; The sampling clock pulse generation circuit eliminates the tri-state preamble and tri-state postamble, respectively, to become the low-state preamble and low-state postamble, thereby generating the effective data strobe signal. The number of gating pulses is P, and the timing of the gating pulses precedes the data. P equals M+A, where A is a positive integer greater than or equal to 1.

3. The memory access interface apparatus of claim 2, wherein the control circuit is further configured to set a second portion that does not correspond to the data signal as a plurality of invalid sampling results, and to discard a plurality of invalid data generated based on the invalid sampling results.

4. The memory access interface device according to claim 3, wherein the invalid data discarded by the control circuit is 2A digits.

5. The memory access interface device according to claim 2, wherein the memory device is an LPDDR4 memory device, an LPDDR5 memory device, or a DDR5 memory device.

6. The memory access interface device according to claim 3, wherein when the memory device does not support the additional gating function, the data gating signal received by the sampling clock pulse generation circuit has multiple gating pulses, and a three-state preamble segment, a high-state preamble segment and a first low-state preamble segment with half a cycle are sequentially provided before the gating pulse, and a three-state post-gating segment is provided after the gating pulse. The sampling clock pulse generation circuit eliminates the tri-state preamble to generate a second low-state preamble, and eliminates the tri-state postamble as a low-state postamble, and then inverts the data strobe signal to generate the effective data strobe signal. The number of gating pulses is M, and P is equal to M+0.

5.

7. The memory access interface device according to claim 6, wherein the sampling circuit does not sample according to the sampling clock pulse signal during the initial operation phase of the memory access interface device, and starts sampling according to the sampling clock pulse signal after the initial operation phase ends.

8. The memory access interface device according to claim 6, wherein the invalid data discarded by the control circuit is one piece.

9. The memory access interface device according to claim 1, wherein N is a positive integer greater than 1, the control circuit further generates a plurality of valid edge information based on the valid sampling result, and outputs the valid sampling result containing the valid data and the valid edge information to the data processing circuit and the sampling clock pulse generation circuit, so that the data processing circuit and the sampling clock pulse generation circuit can fine-tune the data signal and the sampling clock pulse signal accordingly.

10. A memory system comprising: Memory access controller; Memory devices; as well as Memory access interface device, comprising: The clock pulse generation circuit is configured to generate an instruction reference clock pulse signal; A data processing circuit is configured to receive and process a data signal containing multiple data from the memory device, wherein the number of data is 2M, and M is a positive integer. The sampling clock pulse generation circuit is configured to receive a data gating signal from the memory device, process it to generate a valid data gating signal containing multiple valid gating pulses, and generate multiple sampling clock pulse signals of number 2N, wherein the number of valid gating pulses is P, P is greater than M, and N and P are positive integers. The sampling circuit is configured to sample the processed data signal according to the sampling clock pulse signal to generate multiple sampling results; as well as The control circuit is configured as follows: The operating mode is selected based on the time difference between the valid data gating signal and the data signal, so as to set the first part of the sampling result corresponding to the data signal as multiple valid sampling results; as well as The output consists of multiple valid data generated based on the valid sampling results, which are read data signals sent to the memory access controller.

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