Semiconductor memory device

Abstract

According to an embodiment, in a first chip of a semiconductor storage device, a plurality of first conductive layers are layered with first insulating layers interposed. A first semiconductor film extends in a layering direction through the plurality of first conductive layers. In the first chip, a plurality of memory cells are formed at a plurality of intersection positions where the plurality of first conductive layers intersect the first semiconductor film. In a second chip, a plurality of second conductive layers are layered with second insulating layers interposed. A second semiconductor film extends in the layering direction through the plurality of second conductive layers. In the second chip, a plurality of memory cells are formed at a plurality of intersection positions where the plurality of second conductive layers intersect the second semiconductor film. The number of layers of the plurality of first conductive layers and the number of layers of the plurality of second conductive layers are different from each other.

Description

[0001] Citation of relevant applications

[0002] This application asserts priority based on the priority of a prior Japanese patent application No. 2022-89484 filed on June 1, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device with a memory cell array writes data to or reads data from the memory cell array. Specific functions are implemented in the write and / or read processes within the semiconductor memory device. Summary of the Invention

[0005] One embodiment provides a semiconductor memory device that can easily enable multifunctional write processing and / or read processing.

[0006] According to one embodiment, a semiconductor memory device is provided, comprising a first chip, a second chip, and a third chip. The second chip is bonded to the first chip. The third chip is bonded to the second chip on a side opposite to the first chip. The first chip has a plurality of first conductive layers, a first semiconductor film, and a first insulating film. The plurality of first conductive layers are stacked with first insulating layers intersecting each other. The first semiconductor film extends in a stacking direction through the plurality of first conductive layers. The first insulating film is disposed between the plurality of first conductive layers and the semiconductor film. In the first chip, a plurality of memory cells are formed at a plurality of intersection locations where the plurality of first conductive layers and the first semiconductor film intersect. The second chip has a plurality of second conductive layers, a second semiconductor film, and a second insulating film. The plurality of second conductive layers are stacked with second insulating layers intersecting each other. The second semiconductor film extends in a stacking direction through the plurality of second conductive layers. The second insulating film is disposed between the plurality of second conductive layers and the semiconductor film. In the second chip, a plurality of memory cells are formed at a plurality of intersection locations where the plurality of second conductive layers and the second semiconductor film intersect. The number of stacked layers of multiple first conductive layers is different from the number of stacked layers of multiple second conductive layers.

[0007] According to the above configuration, a semiconductor memory device can be provided that can easily enable multifunctional write processing and / or read processing. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating the configuration of the semiconductor memory device according to the first embodiment.

[0009] Figure 2 This is a circuit diagram showing the configuration of the blocks in the first embodiment.

[0010] Figure 3 This is a diagram showing the interconnection configuration between chips in the first embodiment.

[0011] Figure 4 This is a cross-sectional view showing the stacking direction of the semiconductor memory device according to the first embodiment.

[0012] Figure 5 (a) and (b) are cross-sectional views in the stacking direction and top view direction, showing the configuration of the storage cells in the first embodiment.

[0013] Figure 6 This is a top view showing the configuration of the memory cell array in the first embodiment.

[0014] Figure 7 This is a top view showing the configuration of the memory cell array in the first embodiment.

[0015] Figure 8 This is a cross-sectional view showing the lamination direction of the plug connection portion in the first embodiment.

[0016] Figure 9 This is a cross-sectional view showing the stacking direction of the unit portion configuration in the first embodiment.

[0017] Figure 10 This is a circuit diagram showing the configuration of the blocks in the second embodiment.

[0018] Figure 11 This is a cross-sectional view showing the stacking direction of the semiconductor memory device according to the second embodiment.

[0019] Figure 12 (a) and (b) are cross-sectional views showing the stacking direction of the stacking spacing in the second embodiment.

[0020] Figure 13 This is a top view showing the configuration of the semiconductor memory device according to the second embodiment.

[0021] Figure 14 This is a top view showing the configuration of the semiconductor memory device according to the second embodiment.

[0022] Figure 15 This is a cross-sectional view showing the stacking direction of the semiconductor memory device according to the third embodiment.

[0023] Figure 16 (a) and (b) are top-view cross-sectional views showing the configuration of the storage cell in the third embodiment.

[0024] Figure 17 This is a cross-sectional view showing the stacking direction of the semiconductor memory device according to the fourth embodiment.

[0025] Figure 18 (a) and (b) are top-view cross-sectional views showing the configuration of the storage cell in the fourth embodiment. Detailed Implementation

[0026] The semiconductor memory device according to embodiments is described in detail below with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0027] (First Embodiment) The semiconductor memory device of the first embodiment has a memory cell array, and attempts to multi-functionalize the write processing and / or read processing by writing data to or reading data from the memory cell array. For example, the semiconductor memory device 1 can... Figure 1 As shown in the diagram. Figure 1 This is a block diagram showing the configuration of semiconductor memory device 1.

[0028] Semiconductor memory device 1 has multiple chips 10_1, 10_2, and 20. Among the multiple chips 10_1, 10_2, and 20, chips 10_1 and 10_2 each contain memory cell arrays 11_1 and 11_2, and are also referred to as array chips. Chip 20 contains circuitry for controlling the memory cell arrays 11_1 and 11_2, and is also referred to as a circuit chip.

[0029] Furthermore, chips 10_1 and 10_2 are referred to as chip 10 when they are not distinguished from each other. Similarly, memory cell arrays 11_1 and 11_2 are referred to as memory cell array 11 when they are not distinguished from each other. Additionally, Figure 1 The example shows a semiconductor memory device 1 comprising two chips (array chips) 10_1 and 10_2, but the semiconductor memory device 1 may also comprise three or more array chips.

[0030] Chip 10_1 includes a memory cell array 11_1. In memory cell array 11_1, multiple memory cell transistors (hereinafter simply referred to as memory cells) are arranged in three dimensions. Chip 10_2 includes a memory cell array 11_2. In memory cell array 11_2, multiple memory cells are arranged in three dimensions. The memory cell array group 12, including memory cell arrays 11_1 and 11_2, includes multiple blocks BK. A block BK is a collection of multiple memory cells commonly connected by word lines WL. Blocks BK are divided and configured on multiple chips 10_1 and 10_2. The unit that divides the block BK by chip is called a sub-block SBK.

[0031] In the case where the storage cell array group 12 contains multiple blocks BK0 to BK2, the storage cell array 11_1 contains multiple sub-blocks SBK0_1 to SBK2_1, and the storage cell array 11_2 contains multiple sub-blocks SBK0_2 to SBK2_2. The multiple storage cells within the sub-block SBK are associated with rows and columns.

[0032] Each sub-block SBK contains multiple string components SU. A string component SU is a collection of multiple memory strings MS that share a word line WL. Figure 1 The example shows that the subblock SBK consists of four string components SU0 to SU3.

[0033] A string component SU contains multiple memory strings MS. A memory string MS contains a collection of multiple memory cells connected in series.

[0034] in addition, Figure 1 The example shows a semiconductor memory device 1 comprising two chips (array chips) 10_1 and 10_2, but the semiconductor memory device 1 may also comprise three or more array chips. Accordingly, the memory cell array group 12 may comprise three or more memory cell arrays 11. The number of blocks BK within the memory cell array group 12 and the number of sub-blocks SBK within the memory cell array 11 are arbitrary. The number of string components SU within the sub-block SBK is arbitrary.

[0035] Chip 20 includes a sequence generator 21, a voltage generation circuit 22, a row driver 23, a row decoder 24, and a sense amplifier 25, which are used to control the memory cell arrays 11_1 and 11_2.

[0036] The sequence generator 21 provides overall control over all components of the control chip 20. The sequence generator 21 is connected to the voltage generation circuit 22, the row driver 23, the row decoder 24, and the sense amplifier 25. Based on commands and data received from the external controller CTR, the sequence generator 21 controls the operation of the semiconductor memory device 1.

[0037] For example, sequence generator 21 controls write operations based on write commands. During a write operation, sequence generator 21 writes data from a memory cell at a specified address in memory cell array 11 and returns a write completion notification to controller CTR. Sequence generator 21 controls read operations based on read commands. During a read operation, sequence generator 21 reads data from a memory cell at a specified address in memory cell array 11 and returns the read data to controller CTR. Sequence generator 21 controls erase operations based on erase commands. During an erase operation, sequence generator 21 erases data from a specified area in memory cell array 11 and returns an erase completion notification to controller CTR.

[0038] Voltage generation circuit 22 is connected to row driver 23 and sense amplifier 25. Voltage generation circuit 22 generates voltages for write operations, read operations, and erase operations, etc., according to control from sequence generator 21. Voltage generation circuit 22 supplies the generated voltages to row driver 23 and / or sense amplifier 25.

[0039] The line driver 23 is connected to the line decoder 24. The line driver 23 receives the line address (e.g., the page address) from the sequence generator 21. Based on the line address, the line driver 23 transmits the voltage received from the voltage generation circuit 22 to the line decoder 24.

[0040] Row decoder 24 receives row addresses (e.g., block addresses) from sequence generator 21. Row decoder 24 decodes the row addresses. Based on the decoding result, row decoder 24 selects the block BK with the specified address in memory cell array 11.

[0041] The row decoder 24 is connected to the memory cell arrays 11_1 and 11_2 via multiple word lines WL. The word lines WL of memory cell array 11_1 and memory cell array 11_2 are shared by the row decoder 24. Thus, the row decoder 24 can drive the word lines WL of memory cell array 11_1 and memory cell array 11_2 in parallel.

[0042] Row decoder 24 is connected to memory cell arrays 11_1 and 11_2 via multiple select gate lines SGS. The select gate lines SGS of memory cell array 11_1 and memory cell array 11_2 are shared by row decoder 24. Thus, row decoder 24 can drive the select gate lines SGS of memory cell array 11_1 and memory cell array 11_2 in parallel.

[0043] Row decoder 24 is connected to memory cell array 11_1 via multiple select gate lines SGD_1 and to memory cell array 11_2 via multiple select gate lines SGD_2. The select gate lines SGD_1 of memory cell array 11_1 and SGD_2 of memory cell array 11_2 are respectively connected to row decoder 24. Therefore, row decoder 24 can independently drive the select gate lines SGD_1 of memory cell array 11_1 and SGD_2 of memory cell array 11_2.

[0044] The sense amplifier 25 is connected to the memory cell arrays 11_1 and 11_2 via multiple bit lines BL. During a write operation, the sense amplifier 25 supplies a voltage corresponding to the written data to the bit lines BL of the memory cell array 11. During a read operation, the sense amplifier 25 senses the data read from the bit lines BL of the memory cell array 11.

[0045] The bit lines BL of memory cell array 11_1 and BL of memory cell array 11_2 are connected to the sensing amplifier 25. Thus, the sensing amplifier 25 can drive or sense the bit lines BL of memory cell array 11_1 and BL of memory cell array 11_2 in parallel.

[0046] Next, use Figure 2 The circuit configuration of each memory cell array 11_1 and 11_2 is described. Figure 2 This is a circuit diagram showing the configuration of each memory cell array 11_1 and 11_2.

[0047] Each sub-block SBK of each memory cell array 11 has multiple memory strings MS. Each memory string MS has multiple memory cells MC and selection transistors ST1 and ST2. Within each memory string MS, multiple memory cells MC are connected in series between selection transistors ST1 and ST2. The drain of selection transistor ST1 is connected to bit line BL. The source of selection transistor ST2 is connected to source line SL.

[0048] In each string component SU, multiple memory strings MS are commonly connected to select gate lines SGD, SGS, and word lines WL. For example, the select gate line SGD is commonly connected to the gate of the select transistor ST1 of the multiple memory strings MS. The word line WL is commonly connected to the gate of the memory cell MC of the multiple memory strings MS. The select gate line SGS is commonly connected to the gate of the select transistor ST2 of the multiple memory strings MS.

[0049] Within a single string component (SU), a collection of multiple storage units (MCs) connected to a single word line (WL) is called a unit component (CU). For example, if a storage unit (MC) stores p bits of data (p is an integer greater than or equal to 1), the storage capacity of the unit component (CU) is defined as p pages of data.

[0050] The number of word lines WL connecting each memory string MS in memory cell array 11_1 is different from that connecting each memory string MS in memory cell array 11_2. Figure 2 In the example, each memory string MS of memory cell array 11_1 is connected to 6 word lines WL0 to WL5, and each memory string MS of memory cell array 11_2 is connected to 2 word lines WL0 to WL1.

[0051] Each memory string MS in memory cell array 11_1 and each memory string MS in memory cell array 11_2 are configured to drive word lines WL in partial parallel. Two of the six word lines WL0 to WL5, WL0 to WL1, are commonly connected to the gates of the memory cells MC in memory cell array 11_1 and MC in memory cell array 11_2. The remaining four word lines WL2 to WL5 are connected to the gates of the memory cells MC in memory cell array 11_1, but not to the gates of the memory cells MC in memory cell array 11_2.

[0052] Each memory string MS in memory cell array 11_1 and each memory string MS in memory cell array 11_2 are configured to drive the select gate line SGS in parallel. The select gate line SGS is commonly connected to the gate of the select transistor ST2 in memory cell array 11_1 and the gate of the select transistor ST2 in memory cell array 11_2.

[0053] In other words, the row decoder 24 can drive the word line WL in parallel in the memory cell arrays 11_1 and 11_2, and can also drive the select gate line SGS in parallel. As a result, the circuit area of ​​the portion of the row decoder 24 that drives the word line WL and the select gate line SGS can be kept relatively compact.

[0054] The multiple memory strings MS of memory cell array 11_1, the multiple memory strings MS of memory cell array 11_2, and the multiple bit lines BL0 to BLn correspond to each other. Each memory string MS of memory cell array 11_1 shares the memory string MS of memory cell array 11_2 and the corresponding bit line BL.

[0055] In other words, the sensing amplifier 25 can drive the bit line BL in parallel in the memory cell array 11_1 and the memory cell array 11_2, and can sense the potential of the bit line BL in parallel. As a result, the circuit area of ​​the portion of the sensing amplifier 25 that drives the bit line BL and the portion that senses the bit line BL can be kept relatively compact.

[0056] Each memory string MS in memory cell array 11_1 and each memory string MS in memory cell array 11_2 are configured to independently drive the selection transistor ST1. The selection gate line SGD is individually connected between memory cell array 11_1 and memory cell array 11_2. Selection gate lines SGD0_1, SGD1_1, and SGD2_1 are respectively connected to the gates of the selection transistor ST1 in the string components SU0, SU1, and SU2 in memory cell array 11_1. Selection gate lines SGD0_2, SGD1_2, and SGD2_2 are respectively connected to the gates of the selection transistor ST1 in the string components SU0, SU1, and SU2 in memory cell array 11_2.

[0057] In other words, the row decoder 24 can independently drive the selection gate lines SGD_1 and SGD_2 in the memory cell arrays 11_1 and 11_2, and can selectively drive at least one of the memory cell arrays 11_1 and 11_2. Therefore, write and / or read operations can be performed independently in the memory cell arrays 11_1 and 11_2. That is, different functions related to write and / or read operations can be implemented in the memory cell arrays 11_1 and 11_2, and the memory cell arrays 11_1 and 11_2 can be used differently depending on the application.

[0058] For example, the number of memory cells MC in each memory string MS of memory cell array 11_1 is different from that in each memory string MS of memory cell array 11_2. Each memory string MS of memory cell array 11_1 contains 6 memory cells MC0 to MC5, and the wiring load in the memory string MS is relatively large. Each memory string MS of memory cell array 11_2 contains 2 memory cells MC0 to MC1, and the wiring load in the memory string MS is relatively small. Therefore, during the read operation, in memory cell array 11_1, the cell current I of the memory string MS is selected. Cell Relatively small, it can perform low-speed charging and discharging of the bit line BL to achieve a longer operation period tR. In the memory cell array 11_2, the cell current I of the memory string MS is selected. Cell It is relatively large, enabling high-speed charging and discharging of the bit line BL to achieve a short operation period tR. The period tR is the time from receiving the read command from the semiconductor memory device 1 until the read operation is completed, and is mainly the time for sensing the bit line BL using the sensing amplifier 25.

[0059] Next, use Figure 3 The connection structure between chips is explained. Figure 3 This is a diagram showing the connections between chips 20, 10_1, and 10_2.

[0060] A chip (array chip) 10_1 is disposed on top of chip (circuit chip) 20. Chip 10_1 can also be bonded to the upper surface of chip 20. A chip (array chip) 10_2 is disposed on top of chip 10_1. Chip 10_2 can also be bonded to the upper surface of chip 10_1. Chip 10_2 is bonded to chip 10_1 on the opposite side of chip 20. That is, a configuration is formed by sequentially stacking chips 10_1 and 10_2 on chip 20. This configuration is a configuration of stacking multiple memory cell arrays 11_1 and 11_2, also known as a multi-stacked array.

[0061] In each of chips 10_1 and 10_2, the memory cell arrays 11_1 and 11_2 include a cell section and a plug connection section. The cell section is a region in which multiple memory cells MC are arranged. The plug connection section is a region in which select gate line SGS, word line WL, and select gate line SGD are pulled out relative to the cell section in a top-view direction and connected to the contact plug area respectively.

[0062] Select gate line SGD_1 of chip 10_1 and select gate line SGD_2 of chip 10_2 are individually connected to row decoder 24 of chip 20. Select gate line SGD_1 is connected to the plug connection portion of memory cell array 11_1. Select gate line SGD_2 passes through the plug connection portion of memory cell array 11_1 in an insulated state from the plug connection portion and is connected to the plug connection portion of memory cell array 11_2. Select gate line SGD_1 and select gate line SGD_2 are electrically insulated from each other.

[0063] The word line WL of chip 10_1 and the word line WL of chip 10_2 are commonly connected to the row decoder 24 of chip 20. The word line WL is connected to the plug connection part of memory cell array 11_1 and the plug connection part of memory cell array 11_2.

[0064] The select gate line SGS of chip 10_1 and the select gate line SGS of chip 10_2 are commonly connected to the row decoder 24 of chip 20. The select gate line SGS is connected to the plug connection portion of memory cell array 11_1 and the plug connection portion of memory cell array 11_2.

[0065] The bit line BL of chip 10_1 and the bit line BL of chip 10_2 are commonly connected to the sense amplifier 25 of chip 20. The bit line BL is connected to the cell section of memory cell array 11_1 and the cell section of memory cell array 11_2.

[0066] Next, use Figure 4 The general configuration of each chip 20, 10_1, and 10_2 in the semiconductor memory device 1 will be described. Figure 4 This is a cross-sectional view showing the stacking direction of the semiconductor memory device 1.

[0067] In semiconductor memory device 1, multiple chips 20, 10_1, and 10_2 are stacked. Chip 10_1 is arranged on the +Z side of chip 20. Chip 10_2 is arranged on the +Z side of chip 10_1. That is, chips 10_1 and 10_2 are stacked sequentially on the +Z side of chip 20. The construction of sequentially bonding chips 10_1 and 10_2 on the +Z side of chip 20 to form memory cell arrays 11_1 and 11_2 is also called a multi-stacked array.

[0068] In addition, the number of stacked chips (array chips) 10 in the multi-stacked array is not limited to 2, but can be 3 or more.

[0069] Chip 10_1 is bonded to the +Z side of chip 20. Chip 10_1 can also be bonded directly. Chip 20 has an insulating film (e.g., an oxide film) DL1 and an electrode PD1 on the +Z side. Chip 10_1 has an insulating film (e.g., an oxide film) DL2 and an electrode PD2 on the -Z side. In the bonding surface BF1 of chips 20 and 10_1, the insulating film DL1 of chip 20 and the insulating film DL2 of chip 10_1 are bonded, and the electrode PD1 of chip 20 and the electrode PD2 of chip 10_1 are bonded.

[0070] Chip 10_2 is bonded to the +Z side of chip 10_1. Chip 10_2 is bonded to chip 10_1 on the opposite side of chip 20. Chip 10_2 can also be bonded directly. Chip 10_1 has an insulating film (e.g., an oxide film) DL2 and an electrode PD3 on the +Z side. Chip 10_2 has an insulating film (e.g., an oxide film) DL3 and an electrode PD4 on the -Z side. In the bonding surface BF2 of chips 10_1 and 10_2, the insulating film DL2 of chip 10_1 and the insulating film DL3 of chip 10_2 are bonded, and the electrode PD3 of chip 10_1 and the electrode PD4 of chip 10_2 are bonded.

[0071] Chip 20 includes a substrate 4, a transistor Tr, an electrode PD1, wiring structures WS-1 to WS-9, and an insulating film DL1. The substrate 4 is disposed on the -Z side of chip 20 and extends in a plate-like shape in the XY direction. The substrate 4 can be formed from a material primarily composed of semiconductors (e.g., silicon). The substrate 4 has a surface 4a on the +Z side. The transistor Tr functions as a circuit element for controlling the memory cell array 11 (sequence generator 21, voltage generation circuit 22, row driver 23, row decoder 24, sense amplifier 25, etc.). The transistor Tr includes a gate electrode disposed as a conductive film on surface 200a of substrate 200, and a source / drain electrode disposed as a semiconductor region near surface 200a within substrate 200. As described above, electrode PD1 is configured such that its surface is exposed at the bonding surface BF1 of chip 20, 10_1. Each wiring structure WS-1 to WS-9 extends primarily in the Z direction, connecting the gate electrode, source / drain electrode, etc., of transistor Tr to electrode PD1.

[0072] Chip 10_1 has a stacked body SST1, conductive layers 103 and 104, multiple pillars CL1, multiple plugs CP1 and CP2, multiple conductive films BL, electrodes PD2 and PD3, and an insulating film DL2. In the stacked body SST1, multiple conductive layers 102 are stacked in the Z direction, separating insulating layers 101. In the stacked body SST1, conductive layers 102 and insulating layers 101 are stacked alternately multiple times. The Z-direction thickness of conductive layers 102 and insulating layers 101 can be approximately equal. The multiple conductive layers 102, from the -Z side to the +Z side, sequentially function as the select gate line SGD, word line WL5, word line WL4, word line WL3, word line WL2, word line WL1, word line WL0, and select gate line SGS.

[0073] Each conductive layer 102 extends in a plate-like shape in the XY direction. Each columnar body CL1 extends in the Z direction through multiple conductive layers 102. Each columnar body CL1 may also penetrate the stacked body SST1 in the Z direction. Each columnar body CL1 extends in a columnar shape in the Z direction. Each columnar body CL1 contains a semiconductor film CH (reference) that functions as a channel region. Figure 5 The semiconductor film CH extends in a columnar shape (e.g., in a columnar or cylindrical shape) with an axis along the Z direction. At multiple intersections where the multiple conductive layers 102 intersect with the multiple columnar bodies CL1, that is, at multiple intersections where the multiple conductive layers 102 intersect with the multiple semiconductor films CH, multiple memory cells MC are formed.

[0074] like Figure 5 (a) Figure 5 As shown in (b), each columnar body CL1 includes an insulating film CR, a semiconductor film CH, an insulating film TNL, a charge storage film CT, an insulating film BLK1, and an insulating film BLK2. Figure 5 (a) is an XZ sectional view showing the structure of the memory cell MC, and is Figure 4 An enlarged sectional view of part A. Figure 5 (b) is an XY sectional view showing the structure of the memory cell MC, indicating that... Figure 5(a) Cross-section cut along line BB. The insulating film CR extends in the Z direction, forming a cylindrical shape with an axis along the Z direction. The insulating film CR can be formed from an insulating material such as silicon oxide. The semiconductor film CH extends in the Z direction, covering the insulating film CR from the outside in the XY direction, forming a cylindrical shape with an axis along the Z direction. The semiconductor film CH can be formed from a semiconductor such as polycrystalline silicon. The insulating film TNL extends in the Z direction, covering the semiconductor film CH from the outside in the XY direction, forming a cylindrical shape with an axis along the Z direction. The insulating film TNL can be formed from an insulating material such as silicon oxide. The charge storage film CT extends in the Z direction, covering the insulating film TNL from the outside in the XY direction, forming a cylindrical shape with an axis along the Z direction. The charge storage film CT can be formed from an insulating material such as silicon nitride. The insulating film BLK1 extends in the Z direction, covering the charge storage film CT from the outside in the XY direction, forming a cylindrical shape with an axis along the Z direction. The insulating film BLK1 can be formed from an insulating material such as silicon oxide. The insulating film BLK2 extends in the Z direction, covering the insulating film BLK1 from the outside in the XY direction, forming a cylindrical shape with an axis along the Z direction. The insulating film BLK2 can be formed from an insulating material such as aluminum oxide. Figure 5 (a) Figure 5 (b) The portion enclosed by the dashed line functions as the storage unit MC.

[0075] like Figure 4 As shown, the semiconductor film CH in the columnar body CL1 is connected to the conductive layer 103 at the +Z side and to the conductive film BL via a plug at the -Z side. The conductive film BL serves as the bit line BL (reference). Figure 2 The conductive layer 103 is covered by the conductive layer 104 on the +Z side. Conductive layers 103 and 104 serve as the source line SL (reference). Figure 2 ) performs its function. The semiconductor film CH acts as a memory string MS (reference) Figure 2 The channel area in the ) plays a functional role.

[0076] Furthermore, the width of each conductive layer 102 in the Y direction can be equal to that of each other. The width of the multiple conductive layers 102 in the X direction gradually increases from the -Z side to the +Z side. The multiple conductive layers 102 are configured such that the X-direction ends gradually move outward from the -Z side to the +Z side. Thus, in the plug connection portion in the memory cell array 11_1, a stepped structure is formed in which the select gate line SGD, word line WL5, word line WL4, word line WL3, word line WL2, word line WL1, word line WL0, and select gate line SGS are sequentially pulled out in a stepped manner from the -Z side toward the +Z side.

[0077] Multiple plugs CP1 correspond to multiple conductive layers 102. Each plug CP1 is disposed between an electrode PD1 and its corresponding conductive layer 102 in the Z direction, with its -Z side electrically connected to an electrode PD2 and extending along the Z direction, and its +Z side electrically connected to its corresponding conductive layer 102. Thus, the plugs CP1 electrically connect the electrode PD2 and its corresponding conductive layer 102. Each conductive layer 102 can be connected to the transistor Tr of the chip 20 via the plugs CP1, electrode PD2, electrode PD1, and wiring structure WS.

[0078] Multiple plugs CP2 correspond to multiple electrodes PD2 and multiple electrodes PD3. Each plug CP2 is positioned between its corresponding electrode PD2 and corresponding electrode PD3 in the Z direction, with its -Z side electrically connected to electrode PD2 and extending along the Z direction through multiple conductive layers 102, and its +Z side electrically connected to its corresponding electrode PD3. Each plug CP2 penetrates the conductive layers 102 while its outer surface is covered by an insulating film and insulated from the conductive layers 102. Thus, the plugs CP2 electrically connect their corresponding electrodes PD2 and corresponding electrodes PD3.

[0079] Multiple conductive films BL are disposed on the -Z side of the stack SST1. The multiple conductive films BL are arranged relative to each other in the X direction. Each conductive film BL extends in the Y direction. The multiple conductive films BL correspond to multiple pillars CL1. Each conductive film BL is electrically connected to the -Z side end of the corresponding pillar CL1, functioning as a bit line BL. The conductive film BL is electrically connected to electrode PD2. Thus, the bit line BL can be connected to the transistor Tr of chip 10 via electrode PD2, electrode PD1, and wiring structure WS.

[0080] As described above, electrode PD2 is configured such that its surface is exposed at the bonding surface BF1 of chips 20 and 10_1. As described above, electrode PD3 is configured such that its surface is exposed at the bonding surface BF2 of chips 10_1 and 10_2.

[0081] Chip 10_2 has a stacked body SST2, conductive layers 103 and 104, multiple pillars CL2, multiple plugs CP3, multiple conductive films BL, electrodes PD4, and an insulating film DL2. In the stacked body SST2, the multiple conductive layers 102 are stacked in the Z direction, separating the insulating layer 101. In the stacked body SST1, the conductive layers 102 and the insulating layers 101 are stacked alternately multiple times. The Z-direction thickness of the conductive layers 102 and the Z-direction thickness of the insulating layers 101 can be approximately equal to each other. The multiple conductive layers 102, from the -Z side to the +Z side, sequentially function as the select gate line SGD, word line WL1, word line WL0, and select gate line SGS.

[0082] Each conductive layer 102 extends in a plate-like shape in the XY direction. Each columnar body CL2 extends in the Z direction through multiple conductive layers 102. Each columnar body CL2 may also penetrate the stacked body SST2 in the Z direction. Each columnar body CL2 extends in a columnar shape in the Z direction. Each columnar body CL2 contains a semiconductor film CH (reference) that functions as a channel region. Figure 5 The semiconductor film CH extends in a columnar shape (e.g., in a columnar or cylindrical shape) with an axis along the Z direction. At multiple intersections where the multiple conductive layers 102 intersect with the multiple columnar bodies CL2, that is, at multiple intersections where the multiple conductive layers 102 intersect with the multiple semiconductor films CH, multiple memory cells MC are formed.

[0083] like Figure 5 (a) Figure 5 As shown in (b), each columnar body CL2 comprises an insulating film CR, a semiconductor film CH, an insulating film TNL, a charge storage film CT, an insulating film BLK1, and an insulating film BLK2. The insulating film CR extends in the Z direction, forming a columnar shape with an axis along the Z direction. The insulating film CR can be formed from an insulating material such as silicon oxide. The semiconductor film CH extends in the Z direction, covering the insulating film CR from the outside in the XY direction, forming a cylindrical shape with an axis along the Z direction. The semiconductor film CH can be formed from a semiconductor such as polycrystalline silicon. The insulating film TNL extends in the Z direction, covering the semiconductor film CH from the outside in the XY direction, forming a cylindrical shape with an axis along the Z direction. The insulating film TNL can be formed from an insulating material such as silicon oxide. The charge storage film CT extends in the Z direction, covering the insulating film TNL from the outside in the XY direction, forming a cylindrical shape with an axis along the Z direction. The charge storage film CT can be formed from an insulating material such as silicon nitride. The insulating film BLK1 extends in the Z direction, covering the charge storage film CT from the outside in the XY direction, forming a cylindrical shape with an axis along the Z direction. The insulating film BLK1 can be formed from an insulating material such as silicon oxide. The insulating film BLK2 extends in the Z direction, covering the insulating film BLK1 from the outside in the XY direction, forming a cylindrical shape with an axis along the Z direction. The insulating film BLK2 can be formed from an insulating material such as aluminum oxide. Figure 5 (a) Figure 5 (b) The portion enclosed by the dashed line functions as the storage unit MC.

[0084] like Figure 4 As shown, the semiconductor film CH in the columnar body CL2 is connected to the conductive layer 103 at the +Z side and to the conductive film BL via a plug at the -Z side. The conductive film BL serves as the bit line BL (reference). Figure 2 The conductive layer 103 is covered by the conductive layer 104 on the +Z side. Conductive layers 103 and 104 serve as the source line SL (reference). Figure 2 ) performs its function. The semiconductor film CH acts as a memory string MS (reference) Figure 2 The channel area in the ) plays a functional role.

[0085] Furthermore, the width of each conductive layer 102 in the Y direction can be equal to that of each other. The width of the multiple conductive layers 102 in the X direction gradually increases from the -Z side to the +Z side. The multiple conductive layers 102 are configured such that the X-direction ends gradually move outward from the -Z side to the +Z side. Thus, in the plug connection portion in the memory cell array 11_2, a stepped structure is formed in which the select gate line SGD, word line WL5, word line WL4, word line WL3, word line WL2, word line WL1, word line WL0, and select gate line SGS are sequentially pulled out in a stepped manner from the -Z side toward the +Z side.

[0086] Multiple plugs CP3 correspond to multiple conductive layers 102. Each plug CP3 is disposed between an electrode PD4 and its corresponding conductive layer 102 in the Z direction, with its -Z side electrically connected to the electrode PD4 and extending along the Z direction, and its +Z side electrically connected to its corresponding conductive layer 102. Thus, the plugs CP3 electrically connect the electrode PD4 and its corresponding conductive layer 102. Each conductive layer 102 can be connected to the transistor Tr of the chip 20 via plugs CP3, electrodes PD4, PD3, plugs CP2, electrodes PD2, electrodes PD1, and wiring structure WS.

[0087] Multiple conductive films BL are disposed on the -Z side of the stack SST2. The multiple conductive films BL are arranged relative to each other in the X direction. Each conductive film BL extends in the Y direction. The multiple conductive films BL correspond to multiple pillars CL2. Each conductive film BL is electrically connected to the -Z side end of the corresponding pillar CL2, functioning as a bit line BL. The conductive film BL is electrically connected to electrode PD4. Thus, the bit line BL can be connected to the transistor Tr of chip 10 via a plug (not shown), electrode PD4, electrode PD3, plug (not shown), electrode PD2, electrode PD1, and wiring structure WS.

[0088] As described above, electrode PD4 is configured such that its surface is exposed at the bonding surface BF2 of chips 10_1 and 10_2.

[0089] Comparing chips 10_1 and 10_2, the lines extending from the select gate line SGD_1 to chip 20 and from the select gate line SGD_2 to chip 20 are insulated from each other. The connection configuration from the conductive layer 102 on the -Z side of chip 10_1 to the transistor Tr of chip 20 (plug CP1 → electrode PD2 → electrode PD1 → wiring configuration WS-8) is insulated from each other to the connection configuration from the conductive layer 102 on the -Z side of chip 10_2 to the transistor Tr of chip 20 (plug CP3 → electrode PD4 → electrode PD3 → plug CP2 → electrode PD2 → electrode PD1 → wiring configuration WS-9). Therefore, write and / or read operations can be performed independently in memory cell arrays 11_1 and 11_2.

[0090] Furthermore, the number of conductive layers 102 in stacked structure SST1 is different from the number of conductive layers 102 in stacked structure SST2. The interlayer spacing of conductive layers 102 in stacked structure SST1 and the interlayer spacing of conductive layers 102 in stacked structure SST2 can be approximately equal to each other. Here, the interlayer spacing of conductive layers 102 is approximately equal to the sum of the film thickness of conductive layer 102 and the film thickness of insulating layer 101. Accordingly, the Z-direction lengths of the semiconductor film CH of columnar body CL1 penetrating stacked structure SST1 and columnar body CL2 penetrating stacked structure SST2 are different. As a result, the wiring load (=√{(wiring resistance)×(wiring capacitance)}) of each memory string MS in memory cell array 11_1 is different from the wiring load of each memory string MS in memory cell array 11_2, and the period tR during the read operation of memory cell array 11_1 and memory cell array 11_2 is different. In other words, different functions related to read operations can be implemented in storage cell array 11_1 and storage cell array 11_2, and storage cell array 11_1 and storage cell array 11_2 can be used differently according to the purpose.

[0091] For example, the number of conductive layers 102 in stack SST1 is greater than the number of conductive layers 102 in stack SST2. Figure 4In the example, the number of conductive layers 102 in stacked structure SST1 is 8, and the number of conductive layers 102 in stacked structure SST2 is 4, but there is no particular limitation. For example, the number of conductive layers 102 in stacked structure SST2 can be less than 3 / 4 of the number of conductive layers 102 in stacked structure SST1. For example, the number of conductive layers 102 in stacked structure SST2 can be less than 1 / 2 of the number of conductive layers 102 in stacked structure SST1. Accordingly, the Z-direction length of the semiconductor film CH in the columnar body CL1 penetrating stacked structure SST1 is longer than the Z-direction length of the semiconductor film CH in the columnar body CL2 penetrating stacked structure SST2. As a result, the wiring load of each memory string MS in memory cell array 11_1 is greater than the wiring load of each memory string MS in memory cell array 11_2. Therefore, during the read operation, in the memory cell array 11_1, the cell current I of the memory string MS is selected. Cell Relatively small, it can perform low-speed charging and discharging of the bit line BL to achieve a longer operation period tR. In the memory cell array 11_2, the cell current I of the memory string MS is selected. Cell It is relatively large and can perform high-speed charging and discharging of the bit line BL to achieve a short operation period tR.

[0092] Here, the stacked volume SST1 of the memory cell array 11_1 has a larger number of conductive layers 102 and a higher manufacturing cost, while the stacked volume SST2 of the memory cell array 11_2 has a smaller number of conductive layers 102 and a lower manufacturing cost. In other words, the memory cell array 11_1 can be used for high-speed read operations when higher costs are required, while the memory cell array 11_2 can be used for low-speed but low-cost read operations.

[0093] Furthermore, among the multiple wiring structures WS-1 to WS-9, wiring structures WS-1 to WS-4 and WS-8 are electrically connected to the conductive layer 102 of chip 10_1, but not to the conductive layer 102 of chip 10_2. Wiring structures WS-5 to WS-7 are electrically connected to both the conductive layer 102 of chip 10_1 and the conductive layer 102 of chip 10_2. Wiring structure WS-9 is not electrically connected to the conductive layer 102 of chip 10_1, but is electrically connected to the conductive layer 102 of chip 10_2. Therefore, a structure suitable for situations where the number of conductive layers 102 in stacked layer SST1 is greater than the number of conductive layers 102 in stacked layer SST2 can be achieved.

[0094] Alternatively, although not illustrated, the number of conductive layers 102 in stacked structure SST1 may be less than the number of conductive layers 102 in stacked structure SST2. Accordingly, the Z-direction length of the semiconductor film CH in the columnar body CL1 penetrating stacked structure SST1 is shorter than the Z-direction length of the semiconductor film CH in the columnar body CL2 penetrating stacked structure SST2. Therefore, the wiring load of each memory string MS in memory cell array 11_1 is less than the wiring load of each memory string MS in memory cell array 11_2. Therefore, during the read operation, in memory cell array 11_1, the cell current I of the selected memory string MS is... Cell Relatively large, capable of high-speed charging and discharging of bit line BL to achieve short-duration operation, in memory cell array 11_2, the cell current I of memory string MS is selected. Cell It is relatively small and can perform low-speed charging and discharging of the bit line BL to achieve a longer operation during the tR period.

[0095] Next, use Figure 6 The planar configuration of the storage cell array 11_2 is described. Figure 6 This is an XY top view showing the configuration of the storage cell array 11_2.

[0096] In the memory cell array 11_2, blocks BK0, BK1, BK2, and BK3 are arranged sequentially from the +Y side to the -Y side. In each block BK, multiple conductive layers 102 are separated and stacked in the Z direction. For example, in each block BK, four conductive layers 102 function as select gate line SGS, word lines WL0 to WL1, and select gate line SGD. A slit SLT extending in the XZ direction is disposed on the Y-direction side of each block BK. The slit SLT electrically separates the multiple blocks BK.

[0097] Block BK has a unit section and a plug connection section.

[0098] Multiple columnar structures (CLs) are arranged in the unit section. Each columnar structure (CL) extends in the Z direction. The columnar structures (CLs) are connected to the memory string (MS) (reference). Figure 2 Corresponding to this. Multiple columnar bodies CL are arranged in two dimensions along the XY direction. Figure 6 In the example, there are 4 columns facing the X direction. The number of columns CL can be 3 or less, or more than 5. Multiple columns CL can be arranged in an alternating pattern or in a grid pattern.

[0099] On the +Z side of the columnar body CL, multiple position lines BL are arranged in the X direction and each extends along the Y direction. The columnar body CL is connected to any position line BL.

[0100] The plug connectors are located on both sides of the unit in the X direction. The plug connectors include the CP3 region.

[0101] Multiple plugs CP3 are configured in the CP3 region. Each plug CP3 extends in the Z direction. Each plug CP3 is electrically connected to one conductive layer 102 but not to other conductive layers 102. Hereinafter, when referring to plugs CP3 connected to conductive layers 102 that function as word lines WL0 and WL1, they will be described as plugs CP3_w0 and CP3_w1. When referring to plugs CP3 connected to conductive layers 102 that function as select gate lines SGD and SGS, they will be described as plugs CP3_d and CP3_s. Figure 6 In the example, from the X-direction end of the storage cell array 11_2 toward the cell section, plugs CP3_s, CP3_w0, CP3_w1, and CP3_d are arranged sequentially. Plugs CP3 can be configured in one column or in two staggered columns.

[0102] A conductive layer 111 is disposed on the -Z side of plug CP3. The conductive layer 111 is electrically connected to the -Z side of plug CP3 and extends in the +Y or -Y direction from its connection point with plug CP3 to the adjacent block BK. For example, the conductive layer 111 extends in the -Y direction from its connection point with plug CP3 in block BK0 to its connection point with electrode PD4 in block BK1. In the adjacent block BK, on ​​the -Z side of conductive layer 111, electrode PD4 is disposed at a position corresponding to plug CP3, and an insulating layer 112 is disposed at other positions. The -Z side surface of electrode PD4 is exposed to the bonding surface BF2. The -Z side surface of insulating layer 112 is also exposed to the bonding surface BF2.

[0103] Next, use Figure 7 The planar configuration of the storage cell array 11_1 is described. Figure 7 This is an XY top view showing the configuration of the storage cell array 11_1.

[0104] In memory cell array 11_1, each block BK has a cell section and a plug connection section in the same way as memory cell array 11_2. In addition, the structure of the cell section is the same as that of memory cell array 11_2.

[0105] The plug connection portions are located on both sides of the unit portion in the X direction. The plug connection portions include CP1 area and CP2 area.

[0106] Multiple plugs CP1 are configured in the CP1 region. Each plug CP1 extends in the Z direction. Each plug CP1 is electrically connected to one conductive layer 102 but not to other conductive layers 102. Hereinafter, when referring to plugs CP1 connected to conductive layers 102 that function as word lines WL0 to WL5, they will be described as plugs CP1_w0 to CP1_w5. When referring to plugs CP1 connected to conductive layers 102 that function as select gate lines SGD and SGS, they will be described as plugs CP1_d and CP1_s. Figure 7 In the example, from the X-direction end of the storage cell array 11_1 toward the cell section, plugs CP1_s, CP1_w0, CP1_w1, CP1_w2, CP1_w3, CP1_w4, CP1_w5, and plug CP1_d are arranged sequentially. Plug CP1 can be configured in one column or in two staggered columns.

[0107] A conductive layer 111 is disposed on the -Z side of the plug CP1_d. The conductive layer 111 is electrically connected to the -Z side end of the plug CP1 and is connected to the electrode PD2 at the connection position with the plug CP1. The -Z side surface of the electrode PD2 is exposed to the bonding surface BF1. The -Z side surface of the insulating layer 112 is exposed to the bonding surface BF1.

[0108] A conductive layer 111 is disposed on the -Z side of the other plugs CP1_s to CP1_w5. The conductive layer 111 is electrically connected to the -Z side of plug CP1 and extends in the +Y or -Y direction from its connection point with plug CP1 to the adjacent block BK. For example, the conductive layer 111 extends in the -Y direction from its connection point with plug CP1 in block BK0 to its connection point with electrode PD4 in block BK1. In the adjacent block BK, on ​​the -Z side of conductive layer 111, electrode PD2 is disposed at a position corresponding to plug CP2, and an insulating layer 112 is disposed at other positions. The -Z side surface of electrode PD2 is exposed to the bonding surface BF1. The -Z side surface of insulating layer 112 is exposed to the bonding surface BF1.

[0109] Multiple plugs CP2 are configured in the CP2 region. Each plug CP2 extends in the Z direction. Plugs CP2 are not electrically connected to the conductive layer 102 of the memory cell array 11_1. Plugs CP2 are electrically connected to one conductive layer 102 in the memory cell array 11_2, but not to other conductive layers 102. Hereinafter, when referring to plugs CP2 connected to the conductive layer 102 that functions as word lines WL0 and WL1, they will be described as plugs CP2_w0 and CP2_w1. When referring to plugs CP2 connected to the conductive layer 102 that functions as select gate lines SGD and SGS, they will be described as plugs CP2_d and CP2_s. Figure 7In the example, from the X-direction end of the storage cell array 11_1 toward the cell section, plugs CP2_s, CP2_w0, CP2_w1, and CP2_d are arranged sequentially. Plugs CP2 can be configured in one column or in two staggered columns.

[0110] A conductive layer 111 is disposed on the -Z side of plug CP2_d. The conductive layer 111 is electrically connected to the -Z side end of plug CP2 and is connected to electrode PD2 at the connection position with plug CP2. The -Z side surface of electrode PD2 is exposed to the bonding surface BF1. The -Z side surface of insulating layer 112 is exposed to the bonding surface BF1.

[0111] A conductive layer 111 is disposed on the -Z side of plugs CP1_s to CP1_w1, other than plug CP2_d. The conductive layer 111 is electrically connected to the -Z side end of plugs CP2_s to CP2_w1. In the connection position with plugs CP2_s to CP2_w1, the conductive layer 111 is connected to electrode PD2 on the -Z side. The -Z side surface of electrode PD2 is exposed to the bonding surface BF1.

[0112] The conductive layer 111 extends from the connection position of the plugs CP2_s to CP2_w1 in block BK in the +Y or -Y direction to the connection position of the plugs CP2_s to CP2_w1 in the adjacent block BK.

[0113] For example, conductive layer 111 extends in the -Y direction from the connection position in block BK0 with plugs CP1_s to CP1_w1 to the connection position in block BK1 with plugs CP2_s to CP2_w1. Plugs CP1_s to CP1_w1 correspond to plugs CP2_s to CP2_w1. Each plug CP1_s to CP1_w1 is electrically connected to its corresponding plug CP2 via conductive layer 111.

[0114] Compare Figure 7 The planar configuration of the storage cell array 11_1 shown is similar to... Figure 6 The planar configuration of the storage cell array 11_2 shown has the following characteristics: the number of plugs CP1 in region CP1 is greater than the number of plugs CP3 in region CP3. The number of plugs CP2 in region CP2 is equal to the number of plugs CP3 in region CP3.

[0115] Next, use Figure 8 The cross-sectional structure of the plug connection is described. Figure 8 This is a YZ sectional view showing the structure of the plug connection. Figure 8 Cut with CC line respectively Figure 6 and Figure 7 Corresponding to the cross-section at that time.

[0116] In the plug connection section, chips 20, 10_1, and 10_2 are sequentially stacked and bonded. Chip 20 and chip 10_1 are electrically connected to each other via electrodes PD1 and PD2. Chip 10_1 and chip 10_2 are electrically connected to each other via electrodes PD3 and PD4.

[0117] Chip 10_1 includes a memory cell array 11_1 and its wiring. Chip 10_1 has insulating layers 101, 107, 110, 112, 114, a slit SLT, conductive layers 102, 103, 104, 111, and conductors 106, 108, 109.

[0118] In the memory cell array 11_1, insulating layer 101 and conductive layer 102 are stacked alternately multiple times. Multiple conductive layers 102 are arranged from -Z side to +Z side, and sequentially function as select gate line SGD, word line WL5, word line WL4, word line WL3, word line WL2, word line WL1, word line WL0, and select gate line SGS.

[0119] When the conductive layer 102 is defined as functioning as word lines WL5, WL4, WL3, WL2, WL1, and WL0, it is described as conductive layers 102_w5, 102_w4, 102_w3, 102_w2, 102_w1, and 102_w0. When the conductive layer 102 is defined as functioning as select gate lines SGD and SGS, it is described as conductive layers 102_d and 102_s.

[0120] The insulating layer 101 can be formed from an insulating material such as silicon oxide. The conductive layer 102 can be formed from a conductive material such as a material whose main component is metal such as tungsten or a semiconductor that has been given conductivity.

[0121] Multiple conductive layers 102 electrically separate the slits SLT extending in the XZ direction from the conductive layers 102 of other blocks BK. The slits SLT can be formed of an insulating material such as silicon oxide.

[0122] On the +Z side of conductive layer 102_s, a conductive layer 103 is disposed on a dielectric insulating layer 101. A conductive layer 104 is disposed on the +Z side of conductive layer 103. Conductive layer 104 covers the +Z side surface of conductive layer 103. Conductive layers 103 and 104 function as source line SL. The +Z side of conductive layer 104 is covered by insulating layer 114. The surface of insulating layer 114 is exposed at the bonding surface BF2 on the +Z side.

[0123] The conductive layer 103 can be formed from a semiconductor (e.g., polycrystalline silicon) that is imparted with conductivity. The conductive layer 104 can be formed from a material whose main component is a metal such as aluminum.

[0124] A plug CP1 is disposed on the -Z side of the conductive layer 102. The plug CP1 has a cylindrical shape, for example, a cylindrical shape. The plug CP1 includes a conductor 106 and an insulating layer 107. The conductor 106 has a cylindrical shape, for example, a cylindrical shape. The insulating layer 107 covers the side surface of the conductor 106. The insulating layer 107 has a cylindrical shape, for example, a cylindrical shape.

[0125] The +Z side of conductor 106 is connected to a specific conductive layer 102. Conductor 106, with its side insulating layer 107, is electrically insulated from other conductive layers 102, yet it penetrates the other conductive layers 102. The -Z side of conductor 106 is connected to electrode PD2 via conductive layer 111. Thus, conductor 106 electrically connects the specific conductive layer 102 and electrode PD2. Conductor 106 can be formed from a material primarily composed of metals such as copper. Insulating layer 107 can be formed from an insulating material such as silicon oxide.

[0126] exist Figure 8 In the example, plug CP1_w5 is shown. Plug CP1_w5 connects the +Z side of conductor 106 to conductive layer 102_w5. Plug CP1_w5, with its side insulating layer 107, is electrically insulated from other conductive layers 102, and penetrates conductive layer 102_d. The -Z side of plug CP1_w5 is connected to electrode PD2 via conductive layer 111.

[0127] An insulating layer 112 is disposed on the -Z side of the conductive layer 111. The -Z side of the insulating layer 112 is exposed to the bonding surface BF1.

[0128] The plug CP2 extends through multiple conductive layers 102 in the Z direction. The plug CP2 has a cylindrical shape, for example, a cylindrical shape. The plug CP2 includes a conductor 109 and an insulating layer 110. The conductor 109 has a cylindrical shape, for example, a cylindrical shape. The insulating layer 110 covers the sides of the conductor 109. The insulating layer 110 has a cylindrical shape, for example, a cylindrical shape.

[0129] In the CP2 region where plug CP2 is configured, conductive layers 103 and 104 are not configured on the +Z side of plug CP2; instead, a conductor 108 is configured. The +Z side end of conductor 109 is connected to electrode PD3 via conductor 108. Conductor 109 is electrically insulated from multiple conductive layers 102 by its side surface through insulating layer 110, and penetrates multiple conductive layers 102. The -Z side end of conductor 109 is connected to electrode PD2 via conductive layer 111. Thus, conductor 109 electrically connects electrode PD2 and electrode PD3. Conductor 109 can be formed of a material whose main component is metal such as copper. Insulating layer 110 can be formed of an insulating material such as silicon oxide.

[0130] Chip 10_2 includes a memory cell array 11_2 and its wiring. Chip 10_2 has insulating layers 101, 112, 117, a slit SLT, conductive layers 102, 103, 104, 111, and a conductor 116.

[0131] In the memory cell array 11_2, insulating layer 101 and conductive layer 102 are stacked alternately multiple times. Multiple conductive layers 102 are arranged from -Z side to +Z side, and function sequentially as select gate line SGD, word line WL1, word line WL0, and select gate line SGS.

[0132] When the conductive layer 102 is defined as functioning as word lines WL1 and WL0, it is referred to as conductive layers 102_w1 and 102_w0. When the conductive layer 102 is defined as functioning as select gate lines SGD and SGS, it is referred to as conductive layers 102_d and 102_s.

[0133] The insulating layer 101 can be formed from an insulating material such as silicon oxide. The conductive layer 102 can be formed from a conductive material such as a material whose main component is metal such as tungsten or a semiconductor that has been given conductivity.

[0134] Multiple conductive layers 102 electrically separate the slits SLT extending in the XZ direction from the conductive layers 102 of other blocks BK. The slits SLT can be formed of an insulating material such as silicon oxide.

[0135] On the +Z side of conductive layer 102_s, a conductive layer 103 is disposed on a dielectric insulating layer 101. A conductive layer 104 is disposed on the +Z side of conductive layer 103. Conductive layer 104 covers the surface of conductive layer 103 on the +Z side. Conductive layers 103 and 104 function as source line SL.

[0136] The conductive layer 103 can be formed from a semiconductor that is imparted with conductivity. The conductive layer 104 can be formed from a material whose main component is a metal such as aluminum.

[0137] A plug CP3 is disposed on the -Z side of the conductive layer 102. The plug CP3 has a cylindrical shape, for example, a cylindrical shape. The plug CP3 includes a conductor 116 and an insulating layer 117. The conductor 116 has a cylindrical shape, for example, a cylindrical shape. The insulating layer 117 covers the side surface of the conductor 116. The insulating layer 117 has a cylindrical shape, for example, a cylindrical shape.

[0138] The +Z side of conductor 116 is connected to a specific conductive layer 102. Conductor 116, with its side insulating layer 117, is electrically insulated from other conductive layers 102, yet it penetrates other conductive layers 102. The -Z side of conductor 116 is connected to electrode PD4 via conductive layer 111. Thus, conductor 116 is selectively electrically connected to a specific conductive layer 102. Conductor 116 can be formed from a material primarily composed of metals such as copper. Insulating layer 117 can be formed from an insulating material such as silicon oxide.

[0139] exist Figure 8 In the example, plug CP3_w1 is shown. Plug CP3_w1 connects the +Z side of conductor 116 to conductive layer 102_w1. Plug CP3_w1, with its side insulating layer 117, is electrically insulated from other conductive layers 102, and penetrates conductive layer 102_d.

[0140] An insulating layer 112 is disposed on the -Z side of the conductive layer 111. The -Z side of the insulating layer 112 is exposed to the bonding surface BF2.

[0141] Chip 20 has a substrate 200, insulating layers 201, 202, 209, a gate electrode 203, conductors 204, 206, 208, 210, and conductive layers 205, 207.

[0142] A well region and a device separation region are disposed near the surface of the substrate 200. The substrate 200 can be formed of a semiconductor (e.g., silicon). The device separation region electrically isolates the well region from other well regions. An insulating layer 201 is disposed in the device separation region. The insulating layer 201 can be formed of an insulating material such as silicon oxide.

[0143] An insulating layer 202 is disposed on the +Z side of the substrate 200. The insulating layer 202 can be formed of an insulating material such as silicon oxide.

[0144] The transistor Tr includes a gate electrode 203 on the surface 200a of the substrate 200, and a source electrode / drain electrode, etc., are included in the vicinity of the surface 200a within the substrate 200. The gate electrode 203 can be formed from a semiconductor (e.g., polysilicon) that has been imparted with conductivity. The source electrode / drain electrode can be formed as a region in the substrate 200 containing impurities.

[0145] The source electrode and drain electrode are respectively connected to the conductive layer 205 via conductor 204. Conductor 204 extends in the Z direction. The conductive layer 205 is connected to the conductive layer 207 via conductor 206. Conductor 206 extends in the Z direction. The conductive layer 207 is connected to electrode PD1 via conductor 208. Conductor 208 extends in the Z direction. Conductors 204, 206, 208, 208 and conductive layers 205, 207 can be formed of materials with aluminum or copper as the main component.

[0146] On the +Z side of insulating layer 202, electrode PD1 is disposed at a position corresponding to electrode PD2, and insulating layer 209 is disposed at other positions. Electrode PD1 can be formed of a material whose main component is metal such as copper. Insulating layer 209 can be formed of an insulating material such as silicon oxide.

[0147] Comparing the cross-sectional configurations of memory cell array 11_1 and memory cell array 11_2, the number of conductive layers 102 in memory cell array 11_1 is greater than the number of conductive layers 102 in memory cell array 11_2. The spacing between the conductive layers 102 in memory cell array 11_1 and memory cell array 11_2 is the same. The Z-direction height of the stack SST1 in memory cell array 11_1 is greater than the Z-direction height of the stack SST2 in memory cell array 11_2.

[0148] Next, use Figure 9 The cross-sectional structure of the unit section is described. Figure 9 This is a YZ sectional view showing the structure of a unit section. Figure 9 Cut separately with DD line Figure 6 and Figure 7 Corresponding to the cross-section at that time.

[0149] like Figure 9 As shown, columnar body CL1 is configured on chip 10_1, and columnar body CL2 is configured on chip 10_2.

[0150] In chip 10_2, columnar bodies CL2 extend along the Z-direction within the stacked body SST2 and penetrate multiple conductive layers 102. Figure 9 In this example, columnar body CL2 penetrates four conductive layers 102. The +Z side of columnar body CL2 is connected to conductive layer 103, and the -Z side is connected to conductor CP3. The -Z side of conductor CP3 is connected to conductor CP4. Conductor CP4 extends in the Z direction, and its -Z side is connected to conductive film BL.

[0151] The columnar body CL2 is configured with a columnar shape having an axis along the Z direction. Within the columnar body CL2, the insulating film CR, the semiconductor film CH, the insulating film TNL, the charge storage film CT, the insulating film BLK1, and the insulating film BLK2 are arranged sequentially from the axis outwards as described above (see reference). Figure 5 (a) Figure 5(b) The semiconductor film CH covers the +Z side of the insulating film CR and is in contact with the conductive layer 103. The semiconductor film CH is in contact with the semiconductor layer CA on the -Z side. The semiconductor layer CA can be formed of a semiconductor such as polysilicon. The -Z side of the semiconductor layer CA is in contact with the plug CP3. The -Z side of the plug CP3 is in contact with the plug CP4. The -Z side of the plug CP4 is in contact with the conductive film BL. The conductive layer 103 functions as the source line SL, and the conductive film BL functions as the bit line. Thus, the +Z side of the semiconductor film CH is electrically connected to the source line SL, and the -Z side is electrically connected to the bit line BL, functioning as a channel region in the memory string MS.

[0152] In chip 10_2, multiple memory cells MC arranged in the Z-direction are formed at multiple intersection points where multiple conductive layers 102 intersect with pillars CL2. The multiple memory cells MC arranged in the Z-direction are equivalent to the multiple memory cells MC contained in the memory string MS (reference). Figure 2 Multiple memory cells MC are formed at multiple intersection locations where multiple conductive layers 102 intersect with multiple columnar bodies CL2, arranged in the XYZ direction.

[0153] The conductive film BL extends in the Y direction. At the position where the conductive film BL is shifted from the laminate SST1 in the Y direction, the -Z side of the conductive film BL is connected to the electrode PD4 via the plug CP6. The -Z side of the electrode PD4 is exposed at the bonding surface BF2.

[0154] In chip 10_1, a columnar body CL1 extends along the Z-direction within the stacked body SST1 and penetrates multiple conductive layers 102. Figure 9 In this example, columnar body CL2 penetrates eight conductive layers 102. The +Z side of columnar body CL2 is connected to conductive layer 103, and the -Z side is connected to conductor CP3. The -Z side of conductor CP3 is connected to conductor CP4. Conductor CP4 extends in the Z direction, and its -Z side is connected to conductive film BL.

[0155] The columnar body CL1 is configured with a columnar shape having an axis along the Z direction. Within the columnar body CL1, the insulating film CR, the semiconductor film CH, the insulating film TNL, the charge storage film CT, the insulating film BLK1, and the insulating film BLK2 are arranged sequentially from the axis outwards as described above (see reference). Figure 5 (a) Figure 5(b) The semiconductor film CH covers the +Z side of the insulating film CR and is in contact with the conductive layer 103. The semiconductor film CH is in contact with the semiconductor layer CA on the -Z side. The semiconductor layer CA can be formed of a semiconductor such as polysilicon. The -Z side of the semiconductor layer CA is in contact with the plug CP3. The -Z side of the plug CP3 is in contact with the plug CP4. The -Z side of the plug CP4 is in contact with the conductive film BL. The conductive layer 103 functions as the source line SL, and the conductive film BL functions as the bit line. Thus, the +Z side of the semiconductor film CH is electrically connected to the source line SL, and the -Z side is electrically connected to the bit line BL, functioning as a channel region in the memory string MS.

[0156] In chip 10_1, multiple memory cells MC arranged in the Z-direction are formed at multiple intersection points where multiple conductive layers 102 intersect with pillars CL1. The multiple memory cells MC arranged in the Z-direction are equivalent to the multiple memory cells MC contained in the memory string MS (reference). Figure 2 Multiple memory cells MC are formed at multiple intersection locations where multiple conductive layers 102 intersect with multiple columnar bodies CL1, arranged in the XYZ direction.

[0157] The conductive film BL extends in the Y direction. At the position where the conductive film BL is shifted from the laminate SST1 in the Y direction, the -Z side of the conductive film BL is connected to the electrode PD2 via the plug CP6. The -Z side of the electrode PD2 is exposed at the bonding surface BF1.

[0158] Additionally, at the position where the conductive film BL is shifted from the laminate SST1 in the Y direction, its +Z side surface is connected to the electrode PD3 via the plug CP5. The +Z side surface of the electrode PD3 is exposed at the bonding surface BF2 and is in contact with the electrode PD4.

[0159] In other words, the columnar body CL1 of the memory cell array 11_1 and the columnar body CL2 of the memory cell array 11_2 are electrically connected in parallel to the transistor Tr of the chip 10.

[0160] Comparing the cross-sectional configurations of memory cell array 11_1 and memory cell array 11_2, the number of conductive layers 102 in memory cell array 11_1 is greater than that in memory cell array 11_2. The interlayer spacing of the conductive layers 102 in memory cell array 11_1 and memory cell array 11_2 is equal. The Z-direction height of the columnar body CL1 in memory cell array 11_1 is greater than that of the columnar body CL2 in memory cell array 11_2. The Z-direction height of the semiconductor film CH in memory cell array 11_1 is greater than that of the semiconductor film CH in memory cell array 11_2. The number of intersections between the conductive layer 102 and the columnar body CL1 in memory cell array 11_1 is greater than that in memory cell array 11_2. The number of memory cells MC arranged in the Z direction in memory cell array 11_1 is greater than the number of memory cells MC arranged in the Z direction in memory cell array 11_2.

[0161] As described above, in the first embodiment, in the semiconductor memory device 1, the number of conductive layers 102 is set to be different between the stacked layers SST1 and SST2 arranged along the Z direction. Therefore, the Z-direction lengths of the semiconductor film CH penetrating the stacked layer SST1 and the semiconductor film CH penetrating the stacked layer SST2 are different. Consequently, the wiring loads of each memory string MS in the memory cell array 11_1 are different from those of each memory string MS in the memory cell array 11_2, and the periods tR during the readout operations of the memory cell array 11_1 and the memory cell array 11_2 are different. In other words, different functions related to the readout operation can be implemented in the memory cell array 11_1 and the memory cell array 11_2, and the memory cell array 11_1 and the memory cell array 11_2 can be used differently depending on the application. Therefore, the readout processing in the semiconductor memory device 1 can be easily multifunctionalized, and various requests can be handled in parallel.

[0162] Furthermore, the configuration for independently driving the common connection word line WL in memory cell array 11_1 and memory cell array 11_2 is not limited to the common connection bit line BL, but also includes configurations for independently connecting the select gate lines SGD_1 and SGD_2 (see reference). Figure 3 Alternatively, the configuration may consist of independently connected bit lines BL_1 and BL_2, with a common connection to the selected gate line SGD. In this case, bit line BL_1 is connected to a cell portion of memory cell array 11_1, bit line BL_2 is connected to a cell portion of memory cell array 11_2, and bit lines BL_1 and BL_2 are insulated from each other.

[0163] (Second Embodiment) Next, the semiconductor memory device 1i of the second embodiment will be described. Hereinafter, the description will focus on the parts that differ from the first embodiment.

[0164] In the first embodiment, it is exemplified that the number of conductive layers 102 is set to be different between the stacked layers SST1 and SST2, while in the second embodiment, it is exemplified that the stacked spacing of conductive layers 102 is set to be different between the stacked layers SST1 and SST2i.

[0165] In the semiconductor memory device 1i, the number of conductive layers 102, which function as word lines WL, between the stacked layers SST1 and SST2i is equal. Accordingly, as... Figure 10 As shown, the number of word lines WL connecting each memory string MS of the memory cell array 11_1i of chip 10_1i and each memory string MS of the memory cell array 11_2i of chip 10_2i is equal. Figure 10 This is a circuit diagram showing the configuration of block BK in semiconductor memory device 1i. Accordingly, the number of memory cells MC contained in each memory string MS of memory cell array 11_1i and each memory string MS of memory cell array 11_2i is equal.

[0166] exist Figure 10 In the example, each memory string MS of memory cell array 11_1i and each memory string MS of memory cell array 11_2i are connected to 6 word lines WL0 to WL5 respectively. Accordingly, each memory string MS of memory cell array 11_1i and each memory string MS of memory cell array 11_2i each contains 6 memory cells MC0 to MC5.

[0167] In semiconductor memory device 1i, such as Figure 11 and Figure 12 As shown, the stacking spacing P of the conductive layers 102_s to 102_d in the stack SST1 is... 0_1 ~P 6_1 The stacking spacing P between the conductive layers 102_s to 102_d in the stacked volume SST2i 0_2 ~P 6_2 They are not the same. Figure 11 This is an XZ cross-sectional view showing the configuration of semiconductor memory device 1i. Figure 12 This is an XZ sectional view representing the interlayer spacing. Figure 12 (a) is Figure 11 Enlarged sectional view of part E, Figure 12 (b) is Figure 11 An enlarged sectional view of part F.

[0168] According to the interlayer spacing P 0_1 ~P 6_1With the interlayer spacing P 0_2 ~P 6_2 Due to the difference in thickness, the Z-direction film thickness of the conductive layer 102 in stack SST1 is different from that in stack SST2i. Consequently, the wiring load of the word line WL in memory cell array 11_1i is different from that in memory cell array 11_2i, and the write times in the write operations of memory cell array 11_1i and memory cell array 11_2i are different. In other words, different functions related to write operations can be implemented in memory cell array 11_1i and memory cell array 11_2i, and memory cell array 11_1i and memory cell array 11_2i can be used differently depending on the application.

[0169] For example, such as Figure 11 and Figure 12 As shown, the stacking spacing P of the conductive layers 102_s to 102_d in the stack SST1 is... 0_1 ~P 6_1 The stacking spacing P is greater than the 102_s to 102_d conductive layers in the stacked volume SST2i. 0_2 ~P 6_2 If the stacking spacing P of the conductive layers 102_s to 102_d in the stacked volume SST1 is... 0_1 ~P 6_1 The layers are equal to each other, and the interlayer spacing P of the conductive layers 102_s to 102_d in the stacked volume SST2i is equal to each other. 0_2 ~P 6_2 If they are all equal, then the following equation 1 holds true. P 0_1 ≈P 1_1 ≈P 2_1 ≈P 3_1 ≈P 4_1 ≈P 5_1 ≈P 6_1 >P 0_2 ≈P 1_2 ≈P 2_2 ≈P 3_2 ≈P 4_2 ≈P 5_2 ≈P 6_2 ...Equation 1

[0170] According to the relationship shown in Equation 1, the Z-direction film thickness of the conductive layer 102 in stack SST1 is greater than the Z-direction film thickness of the conductive layer 102 in stack SST2i. Therefore, the wiring load of the word line WL in memory cell array 11_1i is less than that in memory cell array 11_2i. Consequently, during the write operation, in memory cell array 11_1i, the charging and discharging of the word line WL can be performed at high speed, resulting in a shorter write time; while in memory cell array 11_2i, the charging and discharging of the word line WL can be performed at low speed, resulting in a longer write time. The write time is the time from when the semiconductor memory device 1i receives the write command until the write completion notification is returned.

[0171] Here, the conductive layer 102 in the stacked body SST1 of the memory cell array 11_1i has a larger stacking spacing and higher manufacturing cost, while the conductive layer 102 in the stacked body SST2i of the memory cell array 11_2i has a smaller stacking spacing and lower manufacturing cost. In other words, the memory cell array 11_1i can be used for write operations when a high-cost but high-speed write operation is required, while the memory cell array 11_2i can be used for write operations when a low-speed but low-cost write operation is required.

[0172] Furthermore, it is desirable that the interlayer spacing P of the conductive layers 102_s to 102_d differs by 5% to 20% between the stacked layers SST1 and SST2i. For example, the interlayer spacing P of the conductive layers 102 in the stacked layer SST1 is... *_1 The stacking spacing P is greater than that of the conductive layer 102 in the stacked body SST2i. *_2 Under the condition that , we expect the following equation 2 to hold: 1.05≤P 0_1 / P 0_2 ≤1.20, 1.05≤P 1_1 / P 1_2 ≤1.20, 1.05≤P 2_1 / P 2_2 ≤1.20, 1.05≤P 3_1 / P 3_2 ≤1.20, 1.05≤P 4_1 / P 4_2 ≤1.20, 1.05≤P 5_1 / P 5_2 ≤1.20, 1.05≤P 6_1 / P 6_2 ≤1.20……Equation 2

[0173] With Equation 2 holding true, a significant performance difference can be found between memory cell arrays 11_1i and 11_2i.

[0174] Furthermore, the stacking spacing P of the conductive layers 102 in stacked layers SST1 and SST2i are different, while the number of conductive layers 102 in stacked layers SST1 and SST2i is the same. Therefore, the Z-direction height of stacked layer SST1 and stacked layer SST2i can be different from each other. Accordingly, the Z-direction height of each columnar column CL1 in memory cell array 11_1i and the Z-direction height of each columnar column CL2 in memory cell array 11_2i can be different from each other.

[0175] exist Figure 11 and Figure 12 In the case where the stacking spacing P of the conductive layers 102 in stack SST1 is greater than the stacking spacing P of the conductive layers 102 in stack SST2i, and the number of conductive layers 102 in stack SST1 and stack SST2i is equal, the Z-direction height of stack SST1 is higher than the Z-direction height of stack SST2i. The Z-direction height of columnar column CL1 in memory cell array 11_1i is higher than the Z-direction height of columnar column CL2 in memory cell array 11_2i.

[0176] Furthermore, the interlayer spacing P is approximately equal to the sum of the thickness of the conductive layer 102 and the thickness of the insulating layer 101. In laminate SST1, the interlayer spacing P can be approximately equal to each other. The proportion of the thickness of the conductive layer 102 to the interlayer spacing P can be approximately equal to each other. The thickness of the conductive layer 102 and the thickness of the insulating layer 101 can be approximately equal to each other. The proportion of the thickness of the conductive layer 102 to the interlayer spacing P can be approximately 50%. Similarly, in laminate SST2, the interlayer spacing P can also be approximately equal to each other. The proportion of the thickness of the conductive layer 102 to the interlayer spacing P can also be approximately equal to each other. The thickness of the conductive layer 102 and the thickness of the insulating layer 101 can also be approximately equal to each other. The proportion of the thickness of the conductive layer 102 to the interlayer spacing P can also be approximately 50%.

[0177] Alternatively, although not illustrated, the interlayer spacing P of the conductive layers 102_s to 102_d in the stacked volume SST1 is... 0_1 ~P 6_1 The interlayer spacing P can also be smaller than the conductive layers 102 s to 102 d in the stacked volume SST2i. 0_2 ~P 6_2Therefore, the Z-direction film thickness of the conductive layer 102 in the stacked layer SST1 can be thinner than the Z-direction film thickness of the conductive layer 102 in the stacked layer SST2i. Consequently, the wiring load of the word line WL in the memory cell array 11_1i is greater than that in the memory cell array 11_2i. Therefore, during the write operation, in the memory cell array 11_1i, the charging and discharging of the word line WL can be performed at a low speed to achieve a longer write time, while in the memory cell array 11_2i, the charging and discharging of the word line WL can be performed at a high speed to achieve a shorter write time.

[0178] In addition, the interlayer spacing P of the conductive layers 102_s to 102_d in the stacked volume SST1 0_1 ~P 6_1 The stacking spacing P between the conductive layers 102_s to 102_d in the stacked volume SST2i 0_2 ~P 6_2 They are different. Therefore, the Z-direction spacing of the memory cells MC in memory cell array 11_1i is different from that in memory cell array 11_2i, and the data retention characteristics of memory cell array 11_1i and memory cell array 11_2i are different. In other words, different functions regarding the reliability of read data can be implemented in memory cell array 11_1i and memory cell array 11_2i, and memory cell array 11_1i and memory cell array 11_2i can be used differently depending on the application.

[0179] For example, such as Figure 11 and Figure 12 As shown, the stacking spacing P of the conductive layers 102_s to 102_d in the stack SST1 is... 0_1 ~P 6_1 The stacking spacing P is greater than the 102_s to 102_d conductive layers in the stacked volume SST2i. 0_2 ~P 6_2 Accordingly, the Z-direction spacing of the memory cells MC in the memory cell array 11_1i (reference) Figure 12 (b) is greater than the Z-direction spacing of the memory cells MC in memory cell array 11_2i (reference). Figure 12 (a)). Therefore, the data retention characteristics of the memory cells MC in memory cell array 11_1i are better than those of the memory cells MC in memory cell array 11_2i. Therefore, during the read operation, data with higher reliability can be read from the memory cells MC in memory cell array 11_1i, and data with lower reliability can be read from the memory cells MC in memory cell array 11_2i.

[0180] Here, the conductive layer 102 in the stacked volume SST1 of the memory cell array 11_1i has a larger stacking spacing and higher manufacturing cost, while the conductive layer 102 in the stacked volume SST2i of the memory cell array 11_2i has a smaller stacking spacing and lower manufacturing cost. In other words, the memory cell array 11_1i can be used for read operations requiring higher cost but higher reliability, while the memory cell array 11_2i can be used for read operations requiring lower reliability but lower cost.

[0181] In addition, the number of memory cells MC in the memory string MS of memory cell array 11_1i can also be equal to the number of memory cells MC in the memory string MS of memory cell array 11_2.

[0182] Alternatively, although not illustrated, the interlayer spacing P of the conductive layers 102_s to 102_d in the stacked volume SST1 is... 0_1 ~P 6_1 The interlayer spacing P can also be smaller than the conductive layers 102 s to 102 d in the stacked volume SST2i. 0_2 ~P 6_2 Therefore, the Z-direction spacing of the memory cells MC in memory cell array 11_1i is smaller than that of the memory cells MC in memory cell array 11_2i. Consequently, the data retention characteristics of the memory cells MC in memory cell array 11_1i are worse than those of the memory cells MC in memory cell array 11_2i. Therefore, during read operations, data with lower reliability can be read from the memory cells MC in memory cell array 11_1i, while data with higher reliability can be read from the memory cells MC in memory cell array 11_2i.

[0183] In addition, such as Figure 13 As shown, the planar configuration of the storage cell array 11_2i differs from that of the first embodiment in the following aspects. Figure 13 This is an XY top view showing the configuration of the storage cell array 11_2i.

[0184] In each block BK of the memory cell array 11_2i, an 8-layer conductive layer 102 is stacked to function as the select gate line SGS, word lines WL0 to WL5, and select gate line SGD.

[0185] Multiple corresponding plugs (CP3) are configured in the CP3 area. Figure 13 In the example, from the X-direction end of the memory cell array 11_2i toward the cell section, plugs CP3_s, CP3_w0, CP3_w1, CP3_w2, CP3_w3, CP3_w4, CP3_w5, and CP3_d are arranged sequentially. Other aspects are the same as... Figure 6The planar structure shown is the same.

[0186] like Figure 14 As shown, the planar configuration of the storage cell array 11_2i differs from that of the first embodiment in the following aspects. Figure 14 This is an XY top view showing the configuration of the storage cell array 11_1i.

[0187] In each block BK of the memory cell array 11_1i, an 8-layer conductive layer 102 is stacked to function as the select gate line SGS, word lines WL0 to WL5, and select gate line SGD.

[0188] Configure multiple corresponding plugs CP3 in the CP2 area. Figure 14 In the example, from the X-direction end of the memory cell array 11_1i toward the cell section, plugs CP3_s, CP3_w0, CP3_w1, CP3_w2, CP3_w3, CP3_w4, CP3_w5, and CP3_d are arranged sequentially. Other aspects are the same as... Figure 7 The planar structure shown is the same.

[0189] Compare Figure 14 The planar configuration of the storage cell array 11_1i shown is similar to... Figure 13 The planar configuration of the storage cell array 11_2i shown has the same number of plugs CP1 in region CP1 as in region CP3, and the same number of plugs CP2 in region CP2 as in region CP3.

[0190] As described above, in the second embodiment, in the semiconductor memory device 1i, the stacking spacing of the conductive layer 102 between the stacked layers SST1 and SST2i arranged along the Z direction is set to be different. Therefore, the Z-direction lengths of the semiconductor film CH of the columnar body CL penetrating the stacked layer SST1 and the columnar body CL penetrating the stacked layer SST2i are different. Consequently, the wiring loads of each memory string MS in the memory cell array 11_1i are different from those of each memory string MS in the memory cell array 11_2i, and the write times in the write operations of the memory cell array 11_1i and the memory cell array 11_2i are different. In other words, different functions related to write operations can be implemented in the memory cell array 11_1i and the memory cell array 11_2i, and the memory cell array 11_1i and the memory cell array 11_2i can be used differently depending on the application. Therefore, the write processing in the semiconductor memory device 1i can be easily multifunctionalized, and various requests can be handled in parallel.

[0191] Furthermore, in the second embodiment, in the semiconductor memory device 1i, the stacking spacing of the conductive layer 102 between the stacked layers SST1 and SST2i arranged along the Z direction is set to be different. Accordingly, the Z-direction spacing of the memory cells MC in the memory cell array 11_1i is different from that in the memory cell array 11_2i, resulting in different data retention characteristics between the memory cell array 11_1i and the memory cell array 11_2i. In other words, different functions regarding the reliability of read data can be implemented in the memory cell array 11_1i and the memory cell array 11_2i, and the memory cell array 11_1i and the memory cell array 11_2i can be used differently depending on the application. Therefore, the read processing in the semiconductor memory device 1i can be easily multifunctionalized, and various requests can be handled in parallel.

[0192] (Third Embodiment) Next, the semiconductor memory device 1j according to the third embodiment will be described. Hereinafter, the description will focus on the parts that differ from the first and second embodiments.

[0193] In the first embodiment, it is exemplified that the number of conductive layers 102 in the stacked body SST is set to different configurations among the memory cell arrays 11, while in the third embodiment, it is exemplified that the thickness of the charge storage film CT is set to different configurations among the memory cell arrays 11.

[0194] In semiconductor memory device 1j, such as Figure 15 and Figure 16 As shown, the thickness D of the charge storage film CT in the storage cell MC_1j of the storage cell array 11_1j is... CT_1j The film thickness D of the charge storage film CT in the storage cell MC_2j of the storage cell array 11_2j. CT_2j They are not the same. Figure 15 This is an XZ cross-sectional view showing the configuration of semiconductor memory device 1j. Figure 16 This is an XY sectional view showing the structure of storage units MC_1j and MC_2j. Figure 16 (a) is the XY cross-sectional view of the storage cell MC_2j, which is equivalent to... Figure 15 XY section view when cut with GG line. Figure 16 (b) is the XY sectional view of the storage cell MC_2j, which is equivalent to... Figure 15 XY sectional view when cut by HH line.

[0195] The film thickness D of the charge storage film CT of storage cells MC_1j and MC_2j at equal stacking positions in stacks SST1 and SST2j. CT_1j D CT_2jThey are all different. The stacking position can be represented by the number of conductive layers 102 counting from the bit line BL side in the stacked volumes SST1 and SST2j. This is based on the film thickness D. CT_1j D CT_2j Due to the difference in thickness, the write speed of memory cell MC_1j is different from that of memory cell MC_2j. Furthermore, based on the film thickness D... CT_1j D CT_2j Due to differences, the data retention characteristics of storage cell MC_1j and storage cell MC_2j are different. In other words, different functions related to the speed of write operations and the reliability of read data can be implemented in storage cell array 11_1 and storage cell array 11_2i, and storage cell array 11_1j and storage cell array 11_2j can be used differently according to the purpose.

[0196] For example, for stacking locations that are equal in stacking volumes SST1 and SST2j, the thickness D of the charge storage film CT of storage cell MC_1j is... CT_1j The thickness D of the charge storage film CT of the memory cell MC_2j is greater than that of the charge storage film CT. CT_2j Thin. As an example, for the stacking position of the second layer from the bit line BL side in stacked layers SST1 and SST2j, memory cells MC_1j and MC_2j are formed at the intersection of conductive layer 102_w5 and columnar structures CL_1j and CL_2j. The diameter D of columnar structures CL_1j and CL_2j is... CL_1j D CL_2j The thickness D of the charge storage film CT of the storage cell MC_1j is equal, but the thickness D of the charge storage film CT is equal. CT_1j The thickness D of the charge storage film CT of the memory cell MC_2j is greater than that of the charge storage film CT. CT_2j Thin. The diameter D of the insulating film CR of the memory cell MC_1j. CR_1j The diameter D of the insulating film CR of the memory cell MC_2j is larger than that of the memory cell MC_2j. CR_2j Regarding the films other than the charge storage film CT and the insulating film CR, the film thickness is equal between storage cells MC_1j and MC_2j. Figure 16 (a) Figure 16 In case (b), the following equations 3 through 9 hold true. D CL_1j ≈D CL_2j ...Number 3D CT_1j <D CT_2j ...Number 4D CR_1j >D CR_2j ...Number 5D CH_1j ≈D CH_2j ...Equation 6D TNL_1j ≈D TNL_2j ...Equation 7D BLK1_1j ≈D BLK1_2j ...Equation 8DBLK2_1j ≈D BLK2_2j ...D of equation 9 and equation 6 CH_1j D CH_2j Let CH represent the thickness of the semiconductor film CH in memory cells MC_1j and MC_2j, respectively. (Equation 7, D) TNL_1j D TNL_2j Let TNL represent the film thickness of the insulating film in memory cells MC_1j and MC_2j, respectively. (Equation 8, D) BLK1_1j D BLK1_2j These represent the film thicknesses of the insulating film BLK1 in memory cells MC_1j and MC_2j, respectively. (D in equation 9) BLK2_1j D BLK2_2j These represent the film thicknesses of the insulating film BLK2 in memory cells MC_1j and MC_2j, respectively.

[0197] Furthermore, the same relationship as equations 3 to 9 also applies to other stacking positions in stacked structures SST1 and SST2j. For example, for the stacking position of the 8th layer from the bit line BL side in stacked structures SST1 and SST2j, the same relationship as equations 3 to 9 also applies between the memory cells MC_1j and MC_2j formed at the intersection of conductive layer 102_w0 and columnar structures CL_1j and CL_2j.

[0198] According to Equation 4, in memory cell MC_1j, the write operation can be accelerated by suppressing the deviation of the threshold voltage during writing, while in memory cell MC_2j, the write operation can be slowed down by increasing the deviation of the threshold voltage during writing. Furthermore, according to Equation 4, in memory cell MC_1j, data retention characteristics can be degraded by shortening the tunneling distance and increasing the electric field, while in memory cell MC_2j, data retention characteristics can be improved by lengthening the tunneling distance and weakening the electric field. The tunneling distance is the distance that the charge travels from the semiconductor film CH through the insulating film TNL to the charge storage film CT during writing. In other words, in the write / read operation, high-speed write operation and low-reliability read operation can be achieved in memory cell array 11_1j, while low-speed write operation and high-reliability read operation can be achieved in memory cell array 11_2j.

[0199] Furthermore, it is expected that the thickness D of the charge storage membrane CT in the storage cells MC_1j and MC_2j corresponding to the same stacking positions in the stacked volumes SST1 and SST2j will be [missing information]. CT_1j D CT_2j The difference is more than 10%. For example, at the same stacking location in stacked volumes SST1 and SST2j, the film thickness D of the charge storage film CT of storage cell MC_1j is different. CT_1j The thickness D of the charge storage film CT of the memory cell MC_2j is greater than that of the charge storage film CT. CT_2jIn the case of a thin layer, we expect the following equation 10 to hold true. D CT_2j / D CT_1j ≥1.1...Equation 10

[0200] By assuming equation 10 holds, a meaningful performance difference can be found between memory cell arrays 11_1j and 11_2j.

[0201] Alternatively, regardless of the stacking positions in stacked volumes SST1 and SST2j, the maximum thickness Max_D of the charge storage membrane CT between storage cell arrays 11_1j and 11_2j is expected to be [value missing]. CT_1j Max_D CT_2j The difference is more than 10%. Maximum film thicknessMax_D CT_1j It is the maximum film thickness among the charge storage film CTs of the multiple storage cells MC_1j contained in the storage cell array 11_1j. Maximum film thickness Max_D CT_2j It is the largest film thickness among the charge storage film CTs of the multiple storage cells MC_1j contained in the storage cell array 11_2j. For example, at the same stacking location in the stacking volumes SST1 and SST2j, the film thickness D of the charge storage film CT of the storage cell MC_1j is... CT_1j The thickness D of the charge storage film CT of the memory cell MC_2j is greater than that of the charge storage film CT. CT_2j In the case of a thin layer, the following equation 11 is expected to hold true. Max_D CT_2j / Max_D CT_1j ≥1.1...Equation 11

[0202] With equation 11 in effect, a meaningful performance difference can be found between memory cell arrays 11_1j and 11_2j.

[0203] Alternatively, although not illustrated, for equal stacking locations in stacks SST1 and SST2j, the thickness D of the charge storage film CT of storage cell MC_1j is... CT_1j The film thickness D of the charge storage film CT of the storage cell MC_2j can also be compared. CT_2jTherefore, in storage cell MC_1j, the write operation can be slowed down by increasing the deviation of the threshold voltage during writing, while in storage cell MC_2j, the write operation can be accelerated by suppressing the deviation of the threshold voltage during writing. Furthermore, in storage cell MC_1j, data retention characteristics can be improved by increasing the tunnel distance and weakening the electric field, while in storage cell MC_2j, data retention characteristics can be degraded by shortening the tunnel distance and strengthening the electric field. In other words, in write / read operations, storage cell array 11_1j can achieve slow write operations and highly reliable read operations, while storage cell array 11_2j can achieve high-speed write operations and less reliable read operations.

[0204] As described above, in the third embodiment, in the semiconductor memory device 1j, the charge storage film CT of the memory cells MC_1j and MC_2j at equal stacking positions in stacked layers SST1 and SST2j has a film thickness D. CT_1j D CT_2j They are all different. Based on the film thickness D... CT_1j D CT_2j Due to the difference in thickness, the write speed of memory cell MC_1j is different from that of memory cell MC_2j. Furthermore, based on the film thickness D... CT_1j D CT_2j Due to differences, the data retention characteristics of storage cell MC_1j and storage cell MC_2j are different. In other words, different functions related to the speed of write operations and the reliability of read data can be implemented in storage cell array 11_1 and storage cell array 11_2i, and storage cell array 11_1j and storage cell array 11_2j can be used differently according to the purpose.

[0205] (Fourth Embodiment) Next, the semiconductor memory device 1k according to the fourth embodiment will be described. Hereinafter, the description will focus on the parts that differ from the first to third embodiments.

[0206] In the third embodiment, the charge storage film CT is configured to have different thicknesses among the storage cell arrays 11. In the fourth embodiment, the insulating film TNL is configured to have different thicknesses among the storage cell arrays 11.

[0207] In semiconductor memory device 1k, such as Figure 17 and Figure 18 As shown, the film thickness D of the insulating film TNL in the memory cell MC_1k of the memory cell array 11_1k is... TNL_1k The film thickness D of the insulating film TNL in the memory cell MC_2k of the memory cell array 11_2k is... TNL_2k They are not the same. Figure 17This is an XZ cross-sectional view showing the configuration of a semiconductor memory device 1k. Figure 18 This is an XY sectional view showing the structure of storage cells MC_1k and MC_2k. Figure 18 (a) is the XY cross-sectional view of the storage cell MC_2k, which is equivalent to... Figure 17 XY sectional view when cut with line II. Figure 18 (b) is the XY cross-sectional view of the storage cell MC_2k, which is equivalent to... Figure 17 XY sectional view when cut by JJ line.

[0208] The film thickness D of the insulating film TNL of the memory cells MC_1k and MC_2k at equal stacking positions in stacks SST1 and SST2k. TNL_1k D TNL_2k They are all different. The stacking position can be represented by the number of conductive layers 102 counting from the bit line BL side in the stacked volumes SST1 and SST2k. This is based on the film thickness D. TNL_1k D TNL_2k Due to the difference in thickness, the write speed of memory cell MC_1k differs from that of memory cell MC_2k. Furthermore, based on the film thickness D... TNL_1k D TNL_2k Due to differences, the data retention characteristics of storage cell MC_1k and storage cell MC_2k are different. In other words, different functions related to the speed of write operations and the reliability of read data can be implemented in storage cell array 11_1 and storage cell array 11_2i, and storage cell array 11_1k and storage cell array 11_2k can be used differently according to the application.

[0209] For example, for equal stacking positions in stacks SST1 and SST2k, the film thickness D of the insulating film TNL of the memory cell MC_1k is... TNL_1k The film thickness D of the insulating film TNL of the memory cell MC_2k is greater than that of the memory cell MC_2k. TNL_2k Thin. As an example, for the stacking position of the second layer from the bit line BL side in the stacked layers SST1 and SST2k, memory cells MC_1k and MC_2k are formed at the intersection of conductive layer 102_w5 and columnar structures CL_1k and CL_2k. The diameter D of columnar structures CL_1k and CL_2k is... CL_1k D CL_2k They are equal, but the film thickness D of the insulating film TNL of the memory cell MC_1k is... TNL_1k The film thickness D of the insulating film TNL of the memory cell MC_2k is greater than that of the memory cell MC_2k. TNL_2k Thin. The diameter D of the insulating film CR of the memory cell MC_1k. CR_1k The diameter D of the insulating film CR larger than that of the memory cell MC_2k CR_2kRegarding the films other than the insulating film TNL and the insulating film CR, the film thickness is equal between memory cells MC_1k and MC_2k. Figure 18 (a) Figure 18 In case (b), the following equations 12 to 18 hold true. D CL_1k ≈D CL_2k ...Equation 12D TNL_1k <D TNL_2k ...Equation 13D CR_1k >D CR_2k ...Equation 14D CH_1k ≈D CH_2k ...Equation 15D CT_1k ≈D CT_2k ...Equation 16D BLK1_1k ≈D BLK1_2k ...Equation 17D BLK2_1k ≈D BLK2_2k ...Equation 18

[0210] D of equation 15 CH_1k D CH_2k Let CH represent the film thicknesses of the semiconductor film CH in memory cells MC_1k and MC_2k, respectively. (Equation 16, D) CT_1k D CT_2k Let represent the film thicknesses of the charge storage film CT in memory cells MC_1k and MC_2k, respectively. (Equation 17, D) BLK1_1k D BLK1_2k These represent the film thicknesses of the insulating film BLK1 in memory cells MC_1k and MC_2k, respectively. (D in equation 18) BLK2_1k D BLK2_2k These represent the film thicknesses of the insulating film BLK2 in memory cells MC_1k and MC_2k, respectively.

[0211] Furthermore, the same relationship applies to other stacking positions in stacked layers SST1 and SST2k as in equations 12 to 18. For example, for the stacking position of the 8th layer from the bit line BL side in stacked layers SST1 and SST2k, the same relationship applies to the memory cells MC_1k and MC_2k formed at the intersection of conductive layer 102_w0 and columnar structures CL_1k and CL_2k.

[0212] According to Equation 13, in memory cell MC_1k, the write operation can be accelerated by suppressing the deviation of the threshold voltage during writing, while in memory cell MC_2k, the write operation can be slowed down by increasing the deviation of the threshold voltage during writing. Furthermore, according to Equation 13, in memory cell MC_1k, data retention characteristics can be degraded by shortening the tunnel distance and increasing the electric field, while in memory cell MC_2k, data retention characteristics can be improved by lengthening the tunnel distance and weakening the electric field. The tunnel distance is the distance that the charge travels from the semiconductor film CH through the insulating film TNL during writing. In other words, in the write / read operation, high-speed write operation and low-reliability read operation can be achieved in memory cell array 11_1k, while low-speed write operation and high-reliability read operation can be achieved in memory cell array 11_2k.

[0213] Furthermore, it is expected that the thickness D of the insulating film TNL in memory cells MC_1k and MC_2k corresponding to the same stacking positions in stacked structures SST1 and SST2k will be [missing information]. TNL_1k D TNL_2k The difference is more than 10%. For example, at the same stacking location in stacked layers SST1 and SST2k, the film thickness D of the insulating film TNL of memory cell MC_1k is different. TNL_1k The film thickness D of the insulating film TNL of the memory cell MC_2k is greater than that of the memory cell MC_2k. TNL_2k In the case of thinness, we expect the following equation 19 to hold true. D TNL_2k / D TNL_1k ≥1.1...Equation 19

[0214] With Equation 19 in effect, a significant performance difference can be found between memory cell arrays 11_1k and 11_2k.

[0215] Alternatively, regardless of the stacking positions in stacked volumes SST1 and SST2k, the maximum film thickness Max_D of the insulating film TNL between memory cell arrays 11_1k and 11_2k is expected to be [value missing]. TNL_1k Max_D TNL_2k The difference is more than 10%. Maximum film thicknessMax_D TNL_1k It is the maximum film thickness among the insulating film thicknesses of the multiple memory cells MC_1k contained in the memory cell array 11_1k, namely Max_D. TNL_2k It is the largest film thickness among the insulating film TNL of the multiple memory cells MC_1k contained in the memory cell array 11_2k. For example, at the same stacking location in stacked volumes SST1 and SST2k, the film thickness D of the insulating film TNL of memory cell MC_1k is... TNL_1k The film thickness D of the insulating film TNL of the memory cell MC_2k is greater than that of the memory cell MC_2k. TNL_2kIn the case of thinness, we expect the following equation 20 to hold true.

[0216] Max_D TNL_2k / Max_D TNL_1k ≥1.1...Equation 20

[0217] With Equation 20 holding true, a meaningful performance difference can be found between memory cell arrays 11_1k and 11_2k.

[0218] Alternatively, although not illustrated, for equal stacking positions in stacks SST1 and SST2k, the film thickness D of the insulating film TNL of the memory cell MC_1k is... TNL_1k It can also be compared to the film thickness D of the insulating film TNL of the memory cell MC_2k. TNL_2k Therefore, in storage cell MC_1k, the write operation can be slowed down by increasing the deviation of the threshold voltage during writing, while in storage cell MC_2k, the write operation can be accelerated by suppressing the deviation of the threshold voltage during writing. Furthermore, in storage cell MC_1k, data retention characteristics can be improved by increasing the tunnel distance and weakening the electric field, while in storage cell MC_2k, data retention characteristics can be degraded by shortening the tunnel distance and strengthening the electric field. In other words, in write / read operations, storage cell array 11_1k can achieve slow write operations and highly reliable read operations, while storage cell array 11_2k can achieve high-speed write operations and less reliable read operations.

[0219] As described above, in the fourth embodiment, in the semiconductor memory device 1k, the film thickness D of the insulating film TNL of the memory cells MC_1k and MC_2k at equal stacking positions in the stacking bodies SST1 and SST2k is... TNL_1k D TNL_2k They are all different. Based on the film thickness D... TNL_1k D TNL_2k Due to the difference in thickness, the write speed of memory cell MC_1k differs from that of memory cell MC_2k. Furthermore, based on the film thickness D... TNL_1k D TNL_2k Due to differences, the data retention characteristics of storage cell MC_1k and storage cell MC_2k are different. In other words, different functions related to the speed of write operations and the reliability of read data can be implemented in storage cell array 11_1 and storage cell array 11_2i, and storage cell array 11_1k and storage cell array 11_2k can be used differently according to the application.

[0220] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. The embodiments and their variations are included within the scope or spirit of the invention, and are also included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: Chip 1; The second chip is bonded to the first chip; and The third chip is bonded to the second chip on the side opposite to the first chip; and The first chip has: Multiple first conductive layers are stacked, separated by first insulating layers; The first semiconductor film extends in the stacking direction through the plurality of first conductive layers; and A first insulating film is disposed between the plurality of first conductive layers and the first semiconductor film; and In the first chip, a plurality of memory cells are formed at a plurality of intersection locations where the plurality of first conductive layers intersect with the first semiconductor film; The second chip has: Multiple second conductive layers are interlayered with a second insulating layer. The second semiconductor film extends in the stacking direction through the plurality of second conductive layers; and A second insulating film is disposed between the plurality of second conductive layers and the second semiconductor film; and In the second chip, a plurality of memory cells are formed at a plurality of intersection locations where the plurality of second conductive layers intersect with the second semiconductor film; The number of stacked layers of the plurality of first conductive layers is different from the number of stacked layers of the plurality of second conductive layers.

2. The semiconductor memory device according to claim 1, wherein the number of stacked layers of the plurality of first conductive layers is greater than the number of stacked layers of the plurality of second conductive layers.

3. The semiconductor memory device according to claim 1, wherein the number of stacked layers of the plurality of first conductive layers is less than the number of stacked layers of the plurality of second conductive layers.

4. A semiconductor memory device comprising: Chip 1; The second chip is bonded to the first chip; and The third chip is bonded to the second chip on the side opposite to the first chip; and The first chip has: Multiple first conductive layers are stacked, separated by first insulating layers; The first semiconductor film extends in the stacking direction through the plurality of first conductive layers; and A first insulating film is disposed between the plurality of first conductive layers and the first semiconductor film; and In the first chip, a plurality of memory cells are formed at a plurality of intersection locations where the plurality of first conductive layers intersect with the first semiconductor film; The second chip has: Multiple second conductive layers are interlayered with a second insulating layer. The second semiconductor film extends in the stacking direction through the plurality of second conductive layers; and A second insulating film is disposed between the plurality of second conductive layers and the second semiconductor film; and In the second chip, a plurality of memory cells are formed at a plurality of intersection locations where the plurality of second conductive layers intersect with the second semiconductor film; The stacking spacing of the plurality of first conductive layers is different from that of the plurality of second conductive layers.

5. The semiconductor memory device according to claim 4, wherein the stacking spacing of the plurality of first conductive layers is larger than the stacking spacing of the plurality of second conductive layers.

6. The semiconductor memory device of claim 4, wherein the stacking spacing of the plurality of first conductive layers is smaller than the stacking spacing of the plurality of second conductive layers.

7. A semiconductor memory device comprising: Chip 1; The second chip is bonded to the first chip; and The third chip is bonded to the second chip on the side opposite to the first chip; and The first chip has: Multiple first conductive layers are stacked, separated by first insulating layers; The first semiconductor film extends in the stacking direction through the plurality of first conductive layers; A first insulating film is disposed between the plurality of first conductive layers and the first semiconductor film; and A first charge storage film is disposed between the first insulating film and the first semiconductor film; and In the first chip, a plurality of memory cells are formed at a plurality of intersection locations where the plurality of first conductive layers intersect with the first semiconductor film; The second chip has: Multiple second conductive layers are interlayered with a second insulating layer. The second semiconductor film extends in the stacking direction through the plurality of second conductive layers; A second insulating film is disposed between the plurality of second conductive layers and the second semiconductor film; and A second charge storage film is disposed between the second insulating film and the second semiconductor film; and In the second chip, a plurality of memory cells are formed at a plurality of intersection locations where the plurality of second conductive layers intersect with the second semiconductor film; In the direction intersecting the stacking direction, the thickness of the first charge storage film and the thickness of the second charge storage film are different from each other.

8. The semiconductor memory device according to claim 7, wherein the thickness of the first charge storage film is thinner than the thickness of the second charge storage film.

9. The semiconductor memory device according to claim 7, wherein the thickness of the first charge storage film is greater than the thickness of the second charge storage film.

10. A semiconductor memory device comprising: Chip 1; The second chip is bonded to the first chip; and The third chip is bonded to the second chip on the side opposite to the first chip; and The first chip has: Multiple first conductive layers are stacked, separated by first insulating layers; The first semiconductor film extends in the stacking direction through the plurality of first conductive layers; A first insulating film is disposed between the plurality of first conductive layers and the first semiconductor film; A first charge storage film is disposed between the first insulating film and the first semiconductor film; and A third insulating film is disposed between the first charge storage film and the first semiconductor film; and In the first chip, a plurality of memory cells are formed at a plurality of intersection locations where the plurality of first conductive layers intersect with the first semiconductor film; The second chip has: Multiple second conductive layers are interlayered with a second insulating layer. The second semiconductor film extends in the stacking direction through the plurality of second conductive layers; A second insulating film is disposed between the plurality of second conductive layers and the second semiconductor film; A second charge storage film is disposed between the second insulating film and the second semiconductor film; and A fourth insulating film is disposed between the second charge storage film and the second semiconductor film; and In the second chip, a plurality of memory cells are formed at a plurality of intersection locations where the plurality of second conductive layers intersect with the second semiconductor film; In the direction intersecting the lamination direction, the thickness of the third insulating film is different from that of the fourth insulating film.

11. The semiconductor memory device of claim 10, wherein the thickness of the third insulating film is thinner than the thickness of the fourth insulating film.

12. The semiconductor memory device of claim 10, wherein the thickness of the third insulating film is greater than the thickness of the fourth insulating film.

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