Semiconductor structure and method of manufacturing the same

Abstract

This application relates to a semiconductor structure and its fabrication method. The semiconductor structure includes a transistor; a first phase-change memory structure, the bottom electrode of which is electrically connected to a first terminal of the source or drain of the transistor; a second phase-change memory structure, the top electrode of which is electrically connected to a first terminal of the transistor and the bottom electrode of the first phase-change memory structure; a first bit line electrically connected to the top electrode of the first phase-change memory structure; and a second bit line electrically connected to the bottom electrode of the second phase-change memory structure. This semiconductor structure forms a complementary structure through the two phase-change memory structures, wherein the first and second phase-change memory structures can always be configured in a complementary state (e.g., the first phase-change memory structure is in a crystalline phase while the second phase-change memory structure is in an amorphous phase, or vice versa), enabling it to function without an external reference signal, with fast read speed, large read margin, and high reliability.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Phase Change Random Access Memory (PCRAM) is an emerging non-volatile storage technology that uses phase change materials as storage media. It achieves data storage by leveraging the different resistivities exhibited by the phase change materials when they rapidly and reversibly switch between crystalline and amorphous phases under the Joule heating effect of electric current.

[0003] The most common internal combination method of PCRAM memory is 1T-1R (one transistor in series with one resistive switching memory) cell, which can realize array configuration, and each cell can be randomly and independently selected.

[0004] However, the 1T-1R also has drawbacks such as the need for a reference signal and a relatively small read margin. Improving the read margin of the PCRAM memory is a problem that urgently needs to be solved. Summary of the Invention

[0005] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problem of small read margin in existing technologies that require a reference signal.

[0006] According to some embodiments, this application provides a semiconductor structure, including:

[0007] transistor;

[0008] A first phase-change memory structure, wherein the bottom electrode of the first phase-change memory structure is electrically connected to the first terminal of the transistor;

[0009] The second phase-change memory structure has its top electrode electrically connected to the first terminal of the transistor.

[0010] The first line is electrically connected to the top electrode of the first phase change memory structure;

[0011] The second bit line is electrically connected to the bottom electrode of the second phase change memory structure.

[0012] In one embodiment, both the first phase change memory structure and the second phase change memory structure include: a bottom electrode, a heating structure, a phase change layer, and a top electrode stacked sequentially from bottom to top.

[0013] In one embodiment, the bottom electrode of the first phase change memory structure and the bottom electrode of the second phase change memory structure are located in the same layer, the heating structure of the first phase change memory structure and the heating structure of the second phase change memory structure are located in the same layer, the phase change layer of the first phase change memory structure and the phase change layer of the second phase change memory structure are located in the same layer, and the top electrode of the first phase change memory structure and the top electrode of the second phase change memory structure are located in the same layer.

[0014] In one embodiment, the width of the heating structure is less than 1 / 5 of the width of the bottom electrode or the top electrode;

[0015] The semiconductor structure also includes:

[0016] The air gap is located between the heating structure of the first phase change memory structure and the heating structure of the second phase change memory structure.

[0017] In one embodiment, the top of the air gap is higher than the lower surface of the top electrode of the first phase change memory structure and the lower surface of the top electrode of the second phase change memory structure.

[0018] In one embodiment, the first phase change memory structure includes a bottom electrode, a heating structure, a phase change layer, and a top electrode stacked sequentially from bottom to top; the second phase change memory structure includes a top electrode, a phase change layer, a heating structure, and a bottom electrode stacked sequentially from bottom to top.

[0019] The bottom electrode of the second phase change memory structure is higher than the top electrode of the first phase change memory structure, or

[0020] The bottom electrode of the second phase change memory structure is flush with the top electrode of the first phase change memory structure.

[0021] In one embodiment, the first bit line and the second bit line are located in the same layer.

[0022] In one embodiment, the top electrode of the second phase change memory structure and the bottom electrode of the first phase change memory structure are both electrically connected to the first end of the transistor via a first interconnect.

[0023] In one embodiment, the first interconnect is connected to a first terminal of the transistor via a first plug;

[0024] The bottom electrode of the first phase-change memory structure is connected to the first interconnect line via a second plug, and the top electrode of the first phase-change memory structure is connected to the first bit line via a third plug;

[0025] The bottom electrode of the second phase change memory structure is connected to the second bit line via a fourth plug, and the top electrode of the second phase change memory structure is electrically connected to the first interconnect line.

[0026] In one embodiment, the semiconductor structure further includes:

[0027] The second interconnect line is located on the first interconnect line, connected to the first interconnect line via the fifth plug, and electrically connected to the top electrode of the second phase change memory structure.

[0028] In one embodiment, the semiconductor structure further includes:

[0029] The third interconnect is located on the second interconnect, connected to the second interconnect via the sixth plug, and connected to the top electrode of the second phase change memory structure via the seventh plug.

[0030] This application also provides a method for fabricating a semiconductor structure, comprising the following steps:

[0031] Forming transistors;

[0032] This forms a first phase-change memory structure, a second phase-change memory structure, a first bit line, and a second bit line; wherein...

[0033] The bottom electrode of the first phase-change memory structure is electrically connected to the first terminal of the transistor;

[0034] The top electrode of the second phase-change memory structure is electrically connected to the first terminal of the transistor;

[0035] The first bit line is electrically connected to the top electrode of the first phase-change memory structure;

[0036] The second bit line is electrically connected to the bottom electrode of the second phase change memory structure.

[0037] In one embodiment, forming the first phase-change memory structure, the second phase-change memory structure, the first bit line, and the second bit line includes the following steps:

[0038] A first dielectric layer is formed, which covers the transistor;

[0039] A first interconnect hole is formed within the first dielectric layer, the first interconnect hole exposing a first end of the transistor;

[0040] A first plug is formed in the first interconnect hole, and a first interconnect line is formed on the upper surface of the first dielectric layer. The first interconnect line is connected to the first end of the transistor via the first plug.

[0041] A second dielectric layer is formed on the first dielectric layer, and a second interconnection hole is formed in the second dielectric layer, the second interconnection hole exposing the first interconnection line;

[0042] A second plug is formed within the second interconnecting hole;

[0043] A third dielectric layer, a fourth dielectric layer, and a fifth dielectric layer are formed sequentially on the second dielectric layer, and a first phase change memory structure and a second phase change memory structure are formed within the third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer; the bottom electrode of the first phase change memory structure is connected to the first interconnect line via the second plug, and the top electrode of the second phase change memory structure is electrically connected to the first interconnect line;

[0044] A sixth dielectric layer is formed on the fifth dielectric layer, and a third interconnection hole is formed in the sixth dielectric layer. A fourth interconnection hole is formed in the sixth dielectric layer, the fifth dielectric layer, and the fourth dielectric layer. The third interconnection hole exposes the top electrode of the first phase change memory structure, and the fourth interconnection hole exposes the bottom electrode of the second phase change memory structure.

[0045] A third plug is formed in the third interconnect hole, and a fourth plug is formed in the fourth interconnect hole. A first bit line and a second bit line are formed on the sixth dielectric layer. The first bit line is electrically connected to the top electrode of the first phase change memory structure via the third plug, and the second bit line is electrically connected to the bottom electrode of the second phase change memory structure via the fourth plug.

[0046] In one embodiment, forming a third dielectric layer, a fourth dielectric layer, and a fifth dielectric layer stacked sequentially on the second dielectric layer, and forming a first phase-change memory structure and a second phase-change memory structure within the third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer, includes the following steps:

[0047] A pair of spaced-apart bottom electrodes are formed on the second dielectric layer, serving as the bottom electrodes of the first phase change memory structure and the second phase change memory structure, respectively.

[0048] A third dielectric layer is formed on the second dielectric layer, and the bottom electrode of the first phase change memory structure and the bottom electrode of the second phase change memory structure are both located in the third dielectric layer.

[0049] A fourth dielectric layer is formed on the third dielectric layer, the fourth dielectric layer covering the bottom electrode; and through holes are formed in the fourth dielectric layer, the through holes being disposed one-to-one with the bottom electrode and exposing the bottom electrode; an air gap is formed in the fourth dielectric layer, the air gap being located between the through holes;

[0050] A heating structure and a phase change layer are formed within the through hole;

[0051] A pair of spaced-apart top electrodes are formed on the fourth dielectric layer, the top electrodes being in contact with the phase change layer; and a fifth dielectric layer is formed on the fourth dielectric layer, the fifth dielectric layer covering the exposed surface of the fourth dielectric layer.

[0052] In one embodiment, forming the heating structure and phase change layer within the through-hole includes the following steps:

[0053] A heating material layer is formed inside the through hole and on the upper surface of the fourth dielectric layer;

[0054] Remove the heating material layer located on the upper surface of the fourth dielectric layer, and etch back the heating material layer located in the through hole to obtain the heating structure whose upper surface is lower than the top of the through hole;

[0055] A phase change material layer is formed inside the through hole and on the upper surface of the fourth dielectric layer;

[0056] The phase change material layer located on the upper surface of the fourth dielectric layer is removed, and the phase change material layer remaining in the through hole is the phase change layer.

[0057] In one embodiment, while forming the second interconnect hole in the second dielectric layer, a fifth interconnect hole is also formed in the second dielectric layer;

[0058] While forming a second plug in the second interconnecting hole, a fifth plug is also formed in the fifth interconnecting hole;

[0059] While forming a pair of spaced-apart bottom electrodes on the second dielectric layer, a second interconnect line is also formed between the bottom electrodes, with a gap between the second interconnect line and the bottom electrodes, and the third dielectric layer fills the gap between the second interconnect line and the bottom electrodes;

[0060] While forming a fourth interconnect hole in the sixth dielectric layer, the fifth dielectric layer and the fourth dielectric layer, a sixth interconnect hole is also formed in the sixth dielectric layer, the fifth dielectric layer and the fourth dielectric layer, and a seventh interconnect hole is formed in the sixth dielectric layer. The sixth interconnect hole exposes the second interconnect line, and the seventh interconnect hole exposes the top electrode of the second phase change memory structure.

[0061] A third plug is formed in the third interconnecting hole, and a fourth plug is formed in the fourth interconnecting hole. At the same time, a sixth plug is formed in the sixth interconnecting hole, and a seventh plug is formed in the seventh interconnecting hole.

[0062] While forming the first bit line and the second bit line on the sixth dielectric layer, a third interconnect line is also formed on the sixth dielectric layer.

[0063] In one embodiment, while forming a first interconnect hole in the first dielectric layer, an eighth interconnect hole is also formed in the first dielectric layer, the eighth interconnect hole exposing the second end of the transistor;

[0064] While forming a first plug in the first interconnecting hole, an eighth plug is also formed in the eighth interconnecting hole;

[0065] While forming a first interconnect line on the upper surface of the first dielectric layer, a control line is also formed on the upper surface of the first dielectric layer, and there is a gap between the control line and the first interconnect line.

[0066] In one embodiment, after forming the first interconnect and the control line, and before forming the second dielectric layer, the following step is further included:

[0067] An etch stop layer is formed on the first interconnect, the control line, and the exposed first dielectric layer.

[0068] In one embodiment, after forming the etch stop layer and before forming the second dielectric layer, the following steps are further included:

[0069] A filling dielectric layer is formed on the upper surface of the etch stop layer between the first interconnect and the control line, the filling dielectric layer filling the gap between the first interconnect and the control line.

[0070] In one embodiment, while forming the first interconnect hole and the eighth interconnect hole in the first dielectric layer, a ninth interconnect hole is also formed in the first dielectric layer, the ninth interconnect hole exposing the control terminal of the transistor;

[0071] While forming a first plug in the first interconnect hole and an eighth plug in the eighth interconnect hole, a ninth lead-out structure is also formed in the ninth interconnect hole.

[0072] The semiconductor structure and its fabrication method provided in this application have the following advantages:

[0073] The semiconductor structure provided in this application forms a complementary structure through two phase change memory structures. The first phase change memory structure and the second phase change memory structure can always be configured to be complementary (for example, the first phase change memory structure is in a crystalline phase state while the second phase change memory structure is in an amorphous phase state, or vice versa), so that it does not require an external reference signal, has a fast read speed, a large read margin, and high reliability.

[0074] The semiconductor structure fabrication method provided in this application forms a complementary structure by creating two phase change memory structures. The first phase change memory structure and the second phase change memory structure can always be configured as complementary (for example, the first phase change memory structure is in a crystalline phase while the second phase change memory structure is in an amorphous phase, or vice versa). This allows the semiconductor structure to be fabricated without an external reference signal, with fast read speed, large read margin, and high reliability. Attached Figure Description

[0075] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0076] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to one embodiment of this application;

[0077] Figure 2 A flowchart of step S102 in the method for fabricating a semiconductor structure provided in one embodiment of this application;

[0078] Figure 3 A cross-sectional schematic diagram of the structure obtained in step S202 in the method for fabricating a semiconductor structure according to one embodiment of this application;

[0079] Figure 4 A schematic cross-sectional view of the structure obtained in step S203 in a method for fabricating a semiconductor structure according to one embodiment of this application;

[0080] Figure 5 A cross-sectional schematic diagram of the semiconductor structure fabrication method provided in one embodiment of this application, after forming the first interconnect and the control line and before forming the second dielectric layer, may further include forming an etch stop layer on the first interconnect, the control line and the exposed first dielectric layer; and forming a filling dielectric layer on the upper surface of the etch stop layer between the first interconnect and the control line.

[0081] Figure 6 A cross-sectional schematic diagram of the structure obtained in step S204 in a method for fabricating a semiconductor structure according to one embodiment of this application;

[0082] Figure 7 A cross-sectional schematic diagram of the structure obtained in step S206 in a method for fabricating a semiconductor structure according to one embodiment of this application;

[0083] Figures 8 to 9 A schematic cross-sectional view of the structure obtained in each step S301 to S303 in the method for preparing a semiconductor structure according to one embodiment of this application;

[0084] Figure 10 A flowchart of step S304 in the method for fabricating a semiconductor structure provided in one embodiment of this application;

[0085] Figures 11 to 14 A schematic cross-sectional view of the structure obtained in each step S401 to S404 in the method for preparing a semiconductor structure according to one embodiment of this application;

[0086] Figure 15 A cross-sectional schematic diagram of the structure obtained in step S305 in a method for fabricating a semiconductor structure according to one embodiment of this application;

[0087] Figure 16 A schematic cross-sectional view of the structure obtained in step S207 in a method for fabricating a semiconductor structure according to one embodiment of this application;

[0088] Figure 17 A schematic cross-sectional view of the structure obtained in step S208 in a method for fabricating a semiconductor structure according to one embodiment of this application; Figure 17 This is also a schematic cross-sectional view of a semiconductor structure provided in one embodiment of this application;

[0089] Figure 18 A flowchart of step S102 in a method for fabricating a semiconductor structure provided in another embodiment of this application;

[0090] Figure 19 A cross-sectional schematic diagram of the structure obtained in step S505 in a method for fabricating a semiconductor structure according to another embodiment of this application;

[0091] Figure 20 A cross-sectional schematic diagram of the structure obtained in step S506 in a method for preparing a semiconductor structure according to another embodiment of this application;

[0092] Figure 21 A cross-sectional schematic diagram of the structure obtained in step S507 in a method for fabricating a semiconductor structure according to another embodiment of this application;

[0093] Figure 22 A cross-sectional schematic diagram of the structure obtained in step S509 in a method for fabricating a semiconductor structure according to another embodiment of this application;

[0094] Figure 23A cross-sectional schematic diagram of the structure obtained in step S510 in a method for preparing a semiconductor structure according to another embodiment of this application;

[0095] Figure 24 A cross-sectional schematic diagram of the structure obtained in step S602 in a method for preparing a semiconductor structure according to another embodiment of this application;

[0096] Figure 25 A flowchart of step S511 in the method for fabricating a semiconductor structure provided in one embodiment of this application;

[0097] Figure 26 A cross-sectional schematic diagram of the structure obtained in step S603 in a method for preparing a semiconductor structure according to another embodiment of this application;

[0098] Figure 27 A flowchart of step S604 in the method for fabricating a semiconductor structure provided in one embodiment of this application;

[0099] Figure 28 A cross-sectional schematic diagram of the structure obtained in step S701 in a method for fabricating a semiconductor structure according to another embodiment of this application;

[0100] Figure 29 A cross-sectional schematic diagram of the structure obtained in step S702 in a method for preparing a semiconductor structure according to another embodiment of this application;

[0101] Figure 30 A cross-sectional schematic diagram of the structure obtained in step S703 in a method for fabricating a semiconductor structure according to another embodiment of this application;

[0102] Figure 31 A cross-sectional schematic diagram of the structure obtained in step S704 in a method for fabricating a semiconductor structure according to another embodiment of this application;

[0103] Figure 32 A cross-sectional schematic diagram of the structure obtained in step S512 in a method for fabricating a semiconductor structure according to another embodiment of this application;

[0104] Figure 33 A cross-sectional schematic diagram of the structure obtained in step S513 in a method for fabricating a semiconductor structure according to another embodiment of this application; Figure 33 This is also a cross-sectional schematic diagram of a semiconductor structure provided in another embodiment of this application;

[0105] Figure 34 A flowchart of step S102 in a method for fabricating a semiconductor structure according to another embodiment of this application;

[0106] Figure 35A flowchart of step S806 in the method for fabricating a semiconductor structure provided in one embodiment of this application;

[0107] Figure 36 A cross-sectional schematic diagram of the structure obtained in step S903 in a method for fabricating a semiconductor structure according to one embodiment of this application;

[0108] Figure 37 A cross-sectional schematic diagram of the structure obtained in step S905 in a method for fabricating a semiconductor structure according to one embodiment of this application;

[0109] Figure 38 A cross-sectional schematic diagram of the structure obtained in step S906 in a method for fabricating a semiconductor structure according to one embodiment of this application;

[0110] Figure 39 A cross-sectional schematic diagram of the structure obtained in step S907 in a method for fabricating a semiconductor structure according to one embodiment of this application;

[0111] Figure 40 A schematic cross-sectional view of the structure obtained in step S908 in a method for fabricating a semiconductor structure according to one embodiment of this application;

[0112] Figure 41 A cross-sectional schematic diagram of the structure obtained in step S909 in the method for preparing a semiconductor structure according to one embodiment of this application;

[0113] Figure 42 A schematic cross-sectional view of the structure obtained in step S807 in a method for fabricating a semiconductor structure according to one embodiment of this application;

[0114] Figure 43 A schematic cross-sectional view of the structure obtained in step S808 in a method for fabricating a semiconductor structure according to one embodiment of this application; Figure 43 This is also a cross-sectional schematic diagram of a semiconductor structure provided in another embodiment of this application.

[0115] Explanation of reference numerals in the attached figures:

[0116] 1. Transistor; 2. First dielectric layer; 201. First interconnect via; 202. First plug; 203. First interconnect line; 204. Eighth interconnect via; 205. Eighth plug; 206. Control line; 207. Etch stop layer; 208. Fill dielectric layer; 3. Second dielectric layer; 301. Second interconnect via; 302. Second plug; 303. Bottom electrode of the first phase change memory structure; 304. Bottom electrode of the second phase change memory structure; 305. Fifth interconnect via; 306. Fifth plug; 307. Second interconnect line; 4. Third dielectric layer; 5. Fourth dielectric layer; 501. Through-hole; 502. Heating material layer; 512. Heating structure; 522. Heating structure; 503. Phase change material layer; 513. 523, Phase Change Layer; 504, Top Electrode of the First Phase Change Memory Structure; 505, Top Electrode of the Second Phase Change Memory Structure; 520, First Phase Change Memory Structure; 521, Second Phase Change Memory Structure; 6, Fifth Dielectric Layer; 7, Sixth Dielectric Layer; 701, Third Interconnect; 702, Fourth Interconnect; 703, Third Plug; 704, Fourth Plug; 705, Sixth Interconnect; 706, Seventh Interconnect; 707, Sixth Plug; 707, Seventh Plug; 8, Seventh Dielectric Layer; 801, First Bit Line; 802, Second Bit Line; 803, Third Interconnect; 9, Eighth Dielectric Layer; 900, Ninth Interconnect; 901, Ninth Plug; 10, Ninth Dielectric Layer; 11, Tenth Dielectric Layer. Detailed Implementation

[0117] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0118] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0119] It should be understood that when an element or layer is referred to as "located above" or "electrically connected to" other elements or layers, it may be directly located above or electrically connected to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first phase change memory structure may be referred to as the second phase change memory structure, and similarly, the second phase change memory structure may be referred to as the first phase change memory structure; the first phase change memory structure and the second phase change memory structure are different phase change memory structures, for example, the first phase change memory structure may be used as a reference cell and the second phase change memory structure may be used as a data cell, or the first phase change memory structure may be used as a data cell and the second phase change memory structure may be used as a reference cell.

[0120] Spatial relation terms such as "above" are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that spatial relation terms include not only the orientation shown in the figure, but also different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as "above" will be oriented "on" other elements or features. Therefore, the exemplary term "above" can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0121] When used herein, the singular forms "a pair" and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the term "comprising" is used in this specification, the presence of the stated feature, integer, step, operation, element, and / or component is confirmed, but the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups is not excluded. Meanwhile, when used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0122] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this application, thus allowing for the anticipation of variations in the shown shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.

[0123] Please see Figure 1 According to some embodiments, this application provides a method for fabricating a semiconductor structure, which may specifically include the following steps:

[0124] S101: Forming a transistor;

[0125] S102: Form the first phase change memory structure, the second phase change memory structure, the first bit line, and the second bit line.

[0126] The transistor has a first terminal and a second terminal, and both the first phase-change memory structure and the second phase-change memory structure have a bottom electrode and a top electrode. Specifically, the bottom electrode of the first phase-change memory structure is electrically connected to the first terminal of the transistor, the top electrode of the second phase-change memory structure is electrically connected to the first terminal of the transistor, the first bit line is electrically connected to the top electrode of the first phase-change memory structure, and the second bit line is electrically connected to the bottom electrode of the second phase-change memory structure.

[0127] The semiconductor structure fabrication method provided in this application forms a complementary structure by creating two phase change memory structures. The first phase change memory structure and the second phase change memory structure can always be configured as complementary (for example, the first phase change memory structure is in a crystalline phase while the second phase change memory structure is in an amorphous phase, or vice versa). This allows the semiconductor structure to be fabricated without an external reference signal, with fast read speed, large read margin, and high reliability.

[0128] It should be noted that this application does not limit the specific type of transistor. The transistor in this application may include, but is not limited to, field-effect transistors or insulated-gate bipolar transistors, etc. The first terminal of the transistor may include the source or the drain. In one embodiment, the first terminal of the transistor may include the drain, and the second terminal of the transistor may include the source.

[0129] The following is combined Figures 2 to 17 The preparation methods of semiconductor structures provided in some embodiments of this application will be described in more detail.

[0130] Please see Figure 2 In one embodiment, step S102 may specifically include the following steps:

[0131] S201: As Figure 3 As shown, a first dielectric layer 2 is formed, and the first dielectric layer 2 covers the transistor 1;

[0132] S202: As Figure 3 As shown, a first interconnect hole 201 is formed in the first dielectric layer 2, and the first interconnect hole 201 exposes the first end of the transistor 1. Figure 3 (First end not shown);

[0133] S203: As Figure 4 As shown, a first plug 202 is formed in the first interconnect hole 201, and a first interconnect line 203 is formed on the upper surface of the first dielectric layer 2. The first interconnect line 203 is connected to the first end of the transistor 1 via the first plug 202.

[0134] S204: As Figure 6 As shown, a second dielectric layer 3 is formed on the first dielectric layer 2, and a second interconnect hole 301 is formed in the second dielectric layer 3, the second interconnect hole 301 exposing the first interconnect line 203;

[0135] S205: As Figure 8 As shown, a second plug 302 is formed within the second interconnection hole 301;

[0136] S206: As Figures 8 to 15 As shown, a third dielectric layer 4, a fourth dielectric layer 5, and a fifth dielectric layer 6 are formed sequentially on the second dielectric layer 3, and a first phase change memory structure 520 and a second phase change memory structure (not shown in the figure) are formed within the third dielectric layer 4, the fourth dielectric layer 5, and the fifth dielectric layer 6; wherein, the bottom electrode 303 of the first phase change memory structure is connected to the first interconnect 203 via the second plug 302, and the top electrode 505 of the second phase change memory structure is electrically connected to the first interconnect 203;

[0137] S207: As Figure 16 As shown, a sixth dielectric layer 7 is formed on the fifth dielectric layer 6, and a third interconnect hole 701 is formed in the sixth dielectric layer 7. A fourth interconnect hole 702 is formed in the sixth dielectric layer 7, the fifth dielectric layer 6 and the fourth dielectric layer 5. The third interconnect hole 701 exposes the top electrode 504 of the first phase change memory structure, and the fourth interconnect hole 702 exposes the bottom electrode 304 of the second phase change memory structure.

[0138] S208: As Figure 17 As shown, in the third interconnect hole 701 ( Figure 17A third plug 703 is formed in the fourth interconnect hole 702, and a fourth plug 704 is formed in the fourth interconnect hole 702. A first bit line 801 and a second bit line 802 are formed on the sixth dielectric layer 7. The first bit line 801 is electrically connected to the top electrode 504 of the first phase change memory structure via the third plug 703, and the second bit line 802 is electrically connected to the bottom electrode 304 of the second phase change memory structure via the fourth plug 704.

[0139] For step S206, please refer to... Figure 7 See Figures 8 to 15 In one embodiment, step S206 may specifically include the following steps:

[0140] S301: As Figure 8 As shown, a pair of bottom electrodes arranged at intervals are formed on the second dielectric layer 3, which serve as the bottom electrode 303 of the first phase change memory structure and the bottom electrode 304 of the second phase change memory structure, respectively.

[0141] S302: As Figure 8 As shown, a third dielectric layer 4 is formed on the second dielectric layer 3, and the bottom electrode 303 of the first phase change memory structure and the bottom electrode 304 of the second phase change memory structure are both located in the third dielectric layer 4.

[0142] In one embodiment, a bottom electrode material layer can be formed on the second dielectric layer, and then the bottom electrode material layer can be patterned to form a third dielectric layer groove and a bottom electrode. The third dielectric layer material layer is filled in the third dielectric layer groove to form a third dielectric layer. Alternatively, a third dielectric layer material layer can be formed on the second dielectric layer first, and then the third dielectric layer material layer can be patterned to form a bottom electrode groove and a third dielectric layer. The bottom electrode material layer is filled in the bottom electrode groove to form a bottom electrode.

[0143] S303: As Figure 9 As shown, a fourth dielectric layer 5 is formed on the third dielectric layer 4, and the fourth dielectric layer 5 covers the bottom electrode; and through holes 501 are formed in the fourth dielectric layer 5, with each through hole 501 corresponding to a bottom electrode and exposing the bottom electrode; an air gap 506 is formed in the fourth dielectric layer 5, and the air gap 506 is located between the through holes 501.

[0144] S304: As Figures 11 to 14 As shown, a heating structure 512 and a phase change layer 513 are formed within the through hole 501;

[0145] S305: As Figure 15 As shown, a pair of spaced-apart top electrodes are formed on the fourth dielectric layer 5, serving as the top electrode 504 of the first phase change memory structure and the top electrode 505 of the second phase change memory structure, respectively; the top electrodes are in contact with the phase change layer 513; and a fifth dielectric layer 6 is formed on the fourth dielectric layer 5, covering the exposed surface of the fourth dielectric layer 5.

[0146] In the semiconductor structure fabrication method provided in the above embodiments, an air gap is formed in the fourth dielectric layer 5. The air gap is located between the vias, which can reduce the parasitic capacitance between the first phase change memory structure and the second phase change memory structure.

[0147] It is understood that in the semiconductor structure fabrication method provided in the above embodiments, the bottom electrode involved in step S303 includes the bottom electrode 303 of the first phase change memory structure and the bottom electrode 304 of the second phase change memory structure.

[0148] This application does not limit the specific method of forming the air gap 506 in the fourth dielectric layer 5; it may be formed by forming an opening in the fourth dielectric layer 5 and depositing a fourth dielectric material layer in the opening, and by controlling the deposition rate of the fourth dielectric material layer to form the air gap 506 in the fourth dielectric layer 5.

[0149] In one embodiment, the width of the via 501 can be 10nm to 20nm, specifically 10nm, 12nm, 15nm, 18nm or 20nm; it should be noted that the above data are only examples, and in actual embodiments, the width of the via 501 is not limited to the above data.

[0150] Based on the above embodiments, the width of the heating structure 512 and the phase change layer 513 can also be 10nm to 20nm, specifically 10nm, 12nm, 15nm, 18nm or 20nm; it should be noted that the above data are only examples, and in actual embodiments, the width of the heating structure 512 and the phase change layer 513 is not limited to the above data.

[0151] It should be noted that this application does not specifically limit the top height of the air gap 506; in another possible embodiment, the top of the air gap 506 may be higher than the lower surface of the top electrode 504 of the first phase change memory structure and the lower surface of the top electrode 505 of the second phase change memory structure; based on the above embodiments, the air gap 506 may be formed in the fourth dielectric layer 5 and the fifth dielectric layer 6.

[0152] For step S304, please refer to... Figure 10 See Figures 11 to 14 In one embodiment, step S304 may specifically include the following steps:

[0153] S401: As Figure 11 As shown, a heating material layer 502 is formed inside the through hole 501 and on the upper surface of the fourth dielectric layer 5;

[0154] S402: As Figure 12As shown, the heating material layer 502 located on the upper surface of the fourth dielectric layer 5 is removed, and the heating material layer 502 located in the through hole 501 is etched back to obtain a heating structure 512 whose upper surface is lower than the top of the through hole 501.

[0155] S403: As Figure 13 As shown, a phase change material layer 503 is formed inside the through hole 501 and on the upper surface of the fourth dielectric layer 5;

[0156] S404: As Figure 14 As shown, the phase change material layer 503 located on the upper surface of the fourth dielectric layer 5 is removed, and the phase change material layer 503 retained in the through hole 501 is the phase change layer 513.

[0157] Please continue reading. Figure 6 In one embodiment, while forming the second interconnect hole 301 in the second dielectric layer 3 in step S204, the step of forming the fifth interconnect hole 305 in the second dielectric layer 3 may also be included.

[0158] Based on the steps above, please continue to refer to... Figure 8 While forming the second plug 302 in the second interconnecting hole 301 in step S205, the step of forming the fifth plug 306 in the fifth interconnecting hole 305 may also be included.

[0159] Based on the steps above, please continue to refer to... Figure 8 In step S206, while forming a pair of spaced-apart bottom electrodes on the second dielectric layer 3, the step of forming a second interconnect 307 between the bottom electrodes may also be included; wherein, there is a gap between the second interconnect 307 and the bottom electrodes, and the third dielectric layer 4 fills the gap between the second interconnect 307 and the bottom electrodes.

[0160] Based on the steps above, please continue to refer to... Figure 16 While forming the fourth interconnect 702 in the sixth dielectric layer 7, the fifth dielectric layer 6 and the fourth dielectric layer 5 in step S207, the method may also include forming the sixth interconnect 705 in the sixth dielectric layer 7, the fifth dielectric layer 6 and the fourth dielectric layer 5, and forming the seventh interconnect 706 in the sixth dielectric layer 7; wherein the sixth interconnect 705 exposes the second interconnect line 307, and the seventh interconnect 706 exposes the top electrode 505 of the second phase change memory structure.

[0161] Based on the steps above, please continue to refer to... Figure 17In step S208, while forming a third plug 703 in the third interconnect hole 701 and a fourth plug 704 in the fourth interconnect hole 702, the step may also include forming a sixth plug 707 in the sixth interconnect hole 705 and a seventh plug 708 in the seventh interconnect hole 706; while forming a first bit line 801 and a second bit line 802 on the sixth dielectric layer 7 in step S208, the step may also include forming a third interconnect line 803 on the sixth dielectric layer 7.

[0162] In one embodiment, such as Figure 3 As shown, while forming the first interconnect hole 201 in the first dielectric layer 2 in step S202, the step of forming an eighth interconnect hole 204 in the first dielectric layer 2 may also be included; specifically, the eighth interconnect hole 204 may expose the second end of the transistor 1. Figure 3 (not shown in the image);

[0163] Based on the above steps, as shown in 4, while forming the first plug 202 in the first interconnect hole 201 in step S203, the step of forming the eighth plug 205 in the eighth interconnect hole 204 may also be included; while forming the first interconnect line 203 on the upper surface of the first dielectric layer 2 in step S202, the step of forming the control line 206 on the upper surface of the first dielectric layer 2 may also be included; specifically, the control line 206 may have a gap with the first interconnect line 203.

[0164] Optionally, in one embodiment, after forming the first interconnect 203 in step S203 and before forming the second dielectric layer 3 in step S204, the step of forming an etch stop layer 207 on the first interconnect 203 and the exposed first dielectric layer 2 may be included. Optionally, in one embodiment, the step of forming a control line 206 on the upper surface of the first dielectric layer 2 is included; based on the above steps, such as Figure 5 As shown, after forming the first interconnect 203 and the control line 206, and before forming the second dielectric layer 3 in step S204, the method may further include forming an etch stop layer 207 on the first interconnect 203, the control line 206, and the exposed first dielectric layer 2.

[0165] It should be noted that this application does not limit the specific material of the etch stop layer 207. The material of the etch stop layer 207 may include, but is not limited to, silicon, silicon carbide, silicon nitride (SiN) or silicon oxynitride (SiON), etc. In one embodiment, the material of the etch stop layer 207 includes silicon nitride.

[0166] Please continue reading. Figure 5 In one embodiment, after forming the etch stop layer 207 and before forming the second dielectric layer 3, the following steps may be included:

[0167] A filling dielectric layer 208 is formed on the upper surface of the etch stop layer 207 between the first interconnect 203 and the control line 206; specifically, the filling dielectric layer 208 fills the gap between the first interconnect 203 and the control line 206.

[0168] It should be noted that this application does not limit the specific methods for forming the first dielectric layer 2, the second dielectric layer 3, the sequentially stacked third dielectric layer 4, fourth dielectric layer 5, and fifth dielectric layer 6, the sixth dielectric layer 7, and the filling dielectric layer 208. The first dielectric layer 2, the second dielectric layer 3, the third dielectric layer 4, the fourth dielectric layer 5, the fifth dielectric layer 6, the sixth dielectric layer 7, and the filling dielectric layer 208 can all be formed using, but are not limited to, Atmospheric Pressure Chemical Vapor Deposition (APCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Plasma-Enhanced Chemical Vapor Deposition (PECVD), High-Density Plasma Chemical Vapor Deposition (HDP-CVD), Radical-Enhanced Chemical Vapor Deposition (RECVD), and Atomic Layer Deposition (ALD). It is formed by deposition using methods such as Layer Deposition (ALD).

[0169] It is understood that this application does not limit the specific materials of the first dielectric layer 2, the second dielectric layer 3, the third dielectric layer 4, the fourth dielectric layer 5, the fifth dielectric layer 6, the sixth dielectric layer 7, and the filling dielectric layer 208. The first dielectric layer 2, the second dielectric layer 3, the third dielectric layer 4, the fourth dielectric layer 5, the fifth dielectric layer 6, the sixth dielectric layer 7, and the filling dielectric layer 208 may be, but are not limited to, silicon, silicon nitride, silicon oxide (SiO2), or silicon nitride (SiN), etc. In one embodiment, the first dielectric layer 2, the second dielectric layer 3, the third dielectric layer 4, the fourth dielectric layer 5, the fifth dielectric layer 6, the sixth dielectric layer 7, and the filling dielectric layer 208 all include silicon nitride.

[0170] In one embodiment, while forming the first interconnect 201 and the eighth interconnect 204 in the first dielectric layer 2, the step of forming a ninth interconnect in the first dielectric layer 2 may also be included; specifically, the ninth interconnect can expose the control terminal of the transistor 1.

[0171] Based on the above steps, while forming the first plug 202 in the first interconnect hole 201 and the eighth plug 205 in the eighth interconnect hole 204, the step of forming the ninth lead-out structure in the ninth interconnect hole may also be included.

[0172] It should be noted that this application does not limit the specific materials of the first plug 202, the second plug 302, the third plug 703, the fourth plug 704, the fifth plug 306, the sixth plug 707, the seventh plug 708, the eighth plug 205, the ninth plug 901, the first interconnect line 203, the second interconnect line 307, and the third interconnect line 803. These plugs and interconnect lines may be made of metal materials such as copper or tungsten, among others. In one embodiment, the first plug 202, the second plug 302, the third plug 703, the fourth plug 704, the fifth plug 306, the sixth plug 707, the seventh plug 708, the eighth plug 205, the ninth plug 901, the first interconnect line 203, the second interconnect line 307, and the third interconnect line 803 all include tungsten. Tungsten can uniformly fill high aspect ratio through holes and has a high melting point, high hardness, excellent corrosion resistance, and good electrical and thermal conductivity.

[0173] This application may also provide a method for fabricating a semiconductor structure according to some optional embodiments; please refer to Figures 3 to 43 The semiconductor structure prepared by the method of preparing the semiconductor structure may include: a transistor 1; a first phase-change memory structure 520, the bottom electrode 303 of the first phase-change memory structure being electrically connected to the first terminal of the transistor 1; a second phase-change memory structure 521, the top electrode 505 of the second phase-change memory structure being electrically connected to the first terminal of the transistor 1; a first bit line 801 being electrically connected to the top electrode 504 of the first phase-change memory structure; and a second bit line 802 being electrically connected to the bottom electrode 304 of the second phase-change memory structure.

[0174] Specifically, the first phase change memory structure 520 may include a bottom electrode 303, a heating structure 512, a phase change layer 513, and a top electrode 504 stacked sequentially from bottom to top; the second phase change memory structure 521 may include a top electrode 505, a phase change layer 513, a heating structure 512, and a bottom electrode 304 stacked sequentially from bottom to top; the bottom electrode 304 of the second phase change memory structure may be higher than the top electrode 504 of the first phase change memory structure.

[0175] More specifically, the top electrode 505 of the second phase change memory structure can be directly connected to the second interconnect 307 via the ninth plug 901. In other words, the top electrode 505 of the second phase change memory structure can be connected to the first interconnect 203 in sequence via the ninth plug 901, the second interconnect 307, and the fifth plug 306.

[0176] In other words, the electrical connection between the top electrode 505 of the second phase-change memory structure and the first interconnect 203 can be achieved in other ways; the following will be combined with Figures 3 to 30 The embodiments for electrically connecting the top electrode 505 of the second phase change memory structure to the first interconnect 203 using other methods are described in detail.

[0177] Please combine Figures 3 to 30 And see Figure 18 In one embodiment, step S102 may specifically include the following steps:

[0178] S501: As Figure 3 As shown, a first dielectric layer 2 is formed, and the first dielectric layer 2 covers the transistor 1;

[0179] S502: As Figure 3 As shown, a first interconnect hole 201 is formed in the first dielectric layer 2, and the first interconnect hole 201 exposes the first terminal of the transistor 1. Figure 3 (First end not shown);

[0180] S503: As Figure 4 As shown, a first plug 202 is formed in the first interconnect hole 201, and a first interconnect line 203 is formed on the upper surface of the first dielectric layer 2. The first interconnect line 203 is connected to the first end of the transistor 1 via the first plug 202.

[0181] S504: As Figure 6 As shown, a second dielectric layer 3 is formed on the first dielectric layer 2, and a second interconnect hole 301 is formed in the second dielectric layer 3, exposing the first interconnect line 203; at the same time, a fifth interconnect hole 305 is also formed in the second dielectric layer 3.

[0182] S505: As Figure 19 As shown, a second plug 302 is formed in the second interconnect hole 301; at the same time, a fifth plug 306 is also formed in the fifth interconnect hole 305;

[0183] S506: As Figure 19 and Figure 20As shown, a third dielectric layer 4, a fourth dielectric layer 5, and a fifth dielectric layer 6 are formed sequentially on the second dielectric layer 3. A first phase change memory structure 520 is formed within the third dielectric layer 4, the fourth dielectric layer 5, and the fifth dielectric layer 6. The bottom electrode 303 of the first phase change memory structure 520 is connected to the first interconnect 203 via a second plug 302. Simultaneously, a second interconnect 307 is formed within the third dielectric layer 4. There is a gap between the second interconnect 307 and the bottom electrode 303 of the first phase change memory structure 520. The third dielectric layer 4 fills the gap between the second interconnect 307 and the bottom electrode 303 of the first phase change memory structure 520.

[0184] S507: As Figure 21 As shown, a sixth dielectric layer 7 is formed on the fifth dielectric layer 6, and a third interconnect hole 701 is formed in the sixth dielectric layer 7. The third interconnect hole 701 exposes the top electrode 504 of the first phase change memory structure 520.

[0185] S508: As Figure 22 As shown, a third plug 703 is formed in the third interconnect hole 701, and a first line 801 is formed on the sixth dielectric layer 7. The first line 801 is electrically connected to the top electrode 504 of the first phase change memory structure 520 via the third plug 703.

[0186] S509: As Figure 22 As shown, a seventh dielectric layer 8 is formed on the sixth dielectric layer 7, and the seventh dielectric layer 8 covers the first line 801;

[0187] S510: As Figure 23 As shown, a ninth interconnect hole 900 is formed in the seventh dielectric layer 8, the sixth dielectric layer 7, the fifth dielectric layer 6 and the fourth dielectric layer 5, and the ninth interconnect hole 900 exposes the second interconnect line 307.

[0188] S511: As Figures 24 to 32 As shown, a ninth plug 901 is formed in the ninth interconnect hole 900, and an eighth dielectric layer 9 and a ninth dielectric layer 10 are formed on the seventh dielectric layer 8 in sequence. A second phase change memory structure 521 is formed in the eighth dielectric layer 9 and the ninth dielectric layer 10. The top electrode 505 of the second phase change memory structure 521 is connected to the second interconnect line 307 via the ninth plug 901.

[0189] S512: As Figure 32 As shown, a tenth dielectric layer 11 is formed on the ninth dielectric layer 10, and a fourth interconnect 702 is formed in the tenth dielectric layer 11, the fourth interconnect 702 exposing the bottom electrode 304 of the second phase change memory structure 521.

[0190] S513: As Figure 33As shown, a fourth plug 704 is formed in the fourth interconnect hole 702, and a second bit line 802 is formed on the tenth dielectric layer 11. The second bit line 802 is electrically connected to the bottom electrode 304 of the second phase change memory structure 521 via the fourth plug 704.

[0191] For step S506, it can be understood that the process of forming a third dielectric layer 4, a fourth dielectric layer 5, and a fifth dielectric layer 6 stacked sequentially on the second dielectric layer 3, and forming a first phase change memory structure 520 within the third dielectric layer 4, the fourth dielectric layer 5, and the fifth dielectric layer 6, can be referred to the detailed description of the process of forming the first phase change memory structure in step S206 above, and will not be elaborated further here.

[0192] For step S511, please refer to... Figures 24 to 32 See Figure 25 In one embodiment, step S511 may specifically include the following steps:

[0193] S601: As Figure 24 As shown, the top electrode 505 of the second phase change memory structure 521 is formed on the seventh dielectric layer 8;

[0194] S602: As Figure 24 As shown, an eighth dielectric layer 9 is formed on the seventh dielectric layer 8, and the top electrode 505 of the second phase change memory structure 521 is located in the eighth dielectric layer 9.

[0195] S603: As Figure 26 As shown, a through hole 501 is formed in the eighth dielectric layer 9. The through hole 501 is correspondingly disposed with the top electrode 505 of the second phase change memory structure 521 and exposes the top electrode 505 of the second phase change memory structure 521.

[0196] S604: As Figures 27 to 31 As shown, a phase change layer 523 and a heating structure 522 are formed in the through hole 501;

[0197] S605: As Figure 32 As shown, a bottom electrode 304 of a second phase change storage structure 521 is formed on the eighth dielectric layer 9, and the bottom electrode 304 of the second phase change storage structure 521 is in contact with the heating structure 522; and a ninth dielectric layer 10 is formed on the eighth dielectric layer 9, and the ninth dielectric layer 10 covers the exposed surface of the eighth dielectric layer 9.

[0198] For step S604, please refer to... Figures 28 to 31 See Figure 27 In one embodiment, step S604 may specifically include the following steps:

[0199] S701: As Figure 28As shown, a phase change material layer 503 is formed inside the through hole 501 and on the upper surface of the eighth dielectric layer 9;

[0200] S702: As Figure 29 As shown, the phase change material layer 503 located on the upper surface of the eighth dielectric layer 9 is removed, and the phase change material layer 503 located in the through hole 501 is etched back to obtain a phase change layer 523 whose upper surface is lower than the top of the through hole 501.

[0201] S703: such as Figure 30 As shown, a heating material layer 502 is formed inside the through hole 501 and on the upper surface of the eighth dielectric layer 9;

[0202] S704: As Figure 31 As shown, the heating material layer 502 located on the upper surface of the eighth dielectric layer 9 is removed, and the heating material layer 502 retained in the through hole 501 is the heating structure 522.

[0203] It is understood that in other alternative embodiments, the bottom electrode 304 of the second phase change memory structure 521 may also be flush with the top electrode 504 of the first phase change memory structure 520. The following is in conjunction with... Figures 3 to 43 The following is a detailed description of an embodiment in which the top electrode 505 of the second phase change memory structure is electrically connected to the first interconnect 203 in another form, and the bottom electrode 304 of the second phase change memory structure 521 is also flush with the top electrode 504 of the first phase change memory structure 520 in the semiconductor structure formed.

[0204] Please see Figure 34 In one embodiment, step S102 may further include the following steps:

[0205] S801: As Figure 3 As shown, a first dielectric layer 2 is formed, and the first dielectric layer 2 covers the transistor 1;

[0206] S802: As Figure 3 As shown, a first interconnect hole 201 is formed in the first dielectric layer 2, and the first interconnect hole 201 exposes the first end of the transistor 1. Figure 3 (First end not shown);

[0207] S803: such as Figure 4 As shown, a first plug 202 is formed in the first interconnect hole 201, and a first interconnect line 203 is formed on the upper surface of the first dielectric layer 2. The first interconnect line 203 is connected to the first end of the transistor 1 via the first plug 202.

[0208] S804: such as Figure 6As shown, a second dielectric layer 3 is formed on the first dielectric layer 2, and a second interconnect hole 301 is formed in the second dielectric layer 3, exposing the first interconnect line 203; at the same time, a fifth interconnect hole 305 is formed in the second dielectric layer 3.

[0209] S805: As Figure 19 As shown, a second plug 302 is formed in the second interconnect hole 301; at the same time, a fifth plug 306 is also formed in the fifth interconnect hole 305;

[0210] S806: As Figure 19 and Figures 36 to 41 As shown, a third dielectric layer 4, a fourth dielectric layer 5, and a fifth dielectric layer 6 are formed sequentially on the second dielectric layer 3. A first phase change memory structure 520 and a second phase change memory structure 521 are formed within the third dielectric layer 4, the fourth dielectric layer 5, and the fifth dielectric layer 6. The bottom electrode 303 of the first phase change memory structure 520 is connected to the first interconnect line 203 via the second plug 302, and the top electrode 505 of the second phase change memory structure 521 is connected to the first interconnect line 203 via the fifth plug 306.

[0211] S807: such as Figure 42 As shown, a sixth dielectric layer 7 is formed on the fifth dielectric layer 6, and a third interconnect hole 701 and a fourth interconnect hole 702 are formed in the sixth dielectric layer 7; the third interconnect hole 701 exposes the top electrode 504 of the first phase change memory structure 520, and the fourth interconnect hole 702 exposes the bottom electrode 304 of the second phase change memory structure 521.

[0212] S808: such as Figure 43 As shown, a third plug 703 is formed in the third interconnect hole 701, and a fourth plug 704 is formed in the fourth interconnect hole 702; a first bit line 801 and a second bit line 802 are formed on the sixth dielectric layer 7; the first bit line 801 is electrically connected to the top electrode 504 of the first phase change memory structure 520 via the third plug 703, and the second bit line 802 is electrically connected to the bottom electrode 304 of the second phase change memory structure 521 via the fourth plug 704.

[0213] For step S806, please refer to Figure 35 and combined Figure 19 and Figures 36 to 41 In one embodiment, step S806 may specifically include the following steps:

[0214] S901: As Figure 19 As shown, the bottom electrode 303 of the first phase change memory structure 520 and the top electrode 505 of the second phase change memory structure 521 are formed on the second dielectric layer 3 at intervals.

[0215] S902: As Figure 19As shown, a third dielectric layer 4 is formed on the second dielectric layer 3, and the bottom electrode 303 of the first phase change memory structure 520 and the top electrode 505 of the second phase change memory structure 521 are both located in the third dielectric layer 4.

[0216] S903: such as Figure 36 As shown, a fourth dielectric layer 5 is formed on the third dielectric layer 4. The fourth dielectric layer 5 covers the bottom electrode 303 of the first phase change memory structure 520 and the top electrode 505 of the second phase change memory structure 521. A first through hole 506 is formed in the fourth dielectric layer 5. The first through hole 506 is correspondingly disposed with the bottom electrode 303 of the first phase change memory structure 520 and exposes the bottom electrode 303 of the first phase change memory structure 520.

[0217] S904: such as Figure 37 As shown, a heating structure 512 of the first phase change storage structure 520 is formed in the first through hole 506;

[0218] S905: As Figure 37 As shown, a second through hole 507 is formed in the fourth dielectric layer 5. The second through hole 507 is correspondingly disposed with the top electrode 505 of the second phase change memory structure 521 and exposes the top electrode 505 of the second phase change memory structure 521.

[0219] S906: such as Figure 38 As shown, a phase change material layer 503 is formed in the first through hole 506 and the second through hole 507;

[0220] S907: such as Figure 39 As shown, the phase change material layer 503 located on the upper surface of the fourth dielectric layer 5 is removed, and the phase change material layer 503 in the second through hole 507 is etched back to obtain the phase change layer 513 of the first phase change memory structure 520 whose upper surface is flush with the fourth dielectric layer 5 and the phase change layer 523 of the second phase change memory structure 521 whose upper surface is lower than the top of the second through hole 507.

[0221] S908: such as Figure 40 As shown, a heating material layer 502 is formed inside the second through hole 507 and on the upper surface of the fourth dielectric layer 5;

[0222] S909: such as Figure 41 As shown, the heating material layer 502 located on the upper surface of the fourth dielectric layer 5 is removed, and the heating material layer 502 retained in the second through hole 507 is the heating structure 522 of the second phase change storage structure 521.

[0223] In one embodiment, step S904 may specifically include the following steps:

[0224] A heating material layer 502 is formed inside the first through hole 506 and on the upper surface of the fourth dielectric layer 5;

[0225] The heating material layer 502 located on the upper surface of the fourth dielectric layer 5 is removed, and the heating material layer 502 located in the first through hole 506 is etched back to obtain a heating structure 512 whose upper surface is lower than the top of the first phase change storage structure 520 of the first through hole 506.

[0226] On the other hand, this application also provides a semiconductor structure according to some embodiments; please continue reading. Figure 17 The semiconductor structure may include transistor 1, a first phase-change memory structure 520, and a second phase-change memory structure ( Figure 17 (Not shown in the text), the first line 801 and the second line 802.

[0227] Specifically, the bottom electrode 303 of the first phase-change memory structure is connected to the first terminal of transistor 1. Figure 17 (Not shown in the diagram) Electrically connected; the top electrode 505 of the second phase change memory structure is electrically connected to the first terminal of transistor 1; the first bit line 801 is electrically connected to the top electrode 504 of the first phase change memory structure; the second bit line 802 is electrically connected to the bottom electrode 304 of the second phase change memory structure.

[0228] The semiconductor structure provided in this application forms a complementary structure through two phase change memory structures. The first phase change memory structure and the second phase change memory structure can always be configured to be complementary (for example, the first phase change memory structure is in a crystalline phase state while the second phase change memory structure is in an amorphous phase state, or vice versa), so that it does not require an external reference signal, has a fast read speed, a large read margin, and high reliability.

[0229] Please continue reading. Figure 17 In one embodiment, the first phase change memory structure 520 and the second phase change memory structure ( Figure 17 (Not shown in the text) can include a bottom electrode, a heating structure 512, a phase change layer 513 and a top electrode stacked from bottom to top.

[0230] Specifically, such as Figure 17 As shown, the first phase change memory structure 520 may include a bottom electrode 303, a heating structure 512, a phase change layer 513, and a top electrode 504 of the first phase change memory structure stacked from bottom to top; the second phase change memory structure may include a bottom electrode 304, a heating structure 512, a phase change layer 513, and a top electrode 505 of the second phase change memory structure stacked from bottom to top.

[0231] In one embodiment, the width of the heating structure 512 and the phase change layer 513 can be 10nm to 20nm, specifically 10nm, 12nm, 15nm, 18nm or 20nm; it should be noted that the above data are only examples, and in actual embodiments, the width of the heating structure 512 and the phase change layer 513 is not limited to the above data.

[0232] It should also be noted that this application does not limit the height relationship between the bottom electrode 304 of the second phase change memory structure and the bottom electrode 303 of the first phase change memory structure; in one embodiment, please refer to [the relevant documentation]. Figure 33 The bottom electrode 304 of the second phase change memory structure can be higher than the top electrode 504 of the first phase change memory structure; in another possible embodiment, please refer to [the relevant documentation]. Figure 43 The bottom electrode 304 of the second phase change memory structure can also be flush with the top electrode 504 of the first phase change memory structure.

[0233] Please continue reading. Figure 17 In one embodiment, the bottom electrode, heating structure 512, phase change layer 513 and top electrode of the first phase change memory structure 520 and the second phase change memory structure can be located in the same layer.

[0234] Specifically, the bottom electrode 303 of the first phase change memory structure and the bottom electrode 304 of the second phase change memory structure can be located in the same layer; the heating structure 512 of the first phase change memory structure 520 and the heating structure 512 of the second phase change memory structure can be located in the same layer; the phase change layer 513 of the first phase change memory structure 520 and the phase change layer 513 of the second phase change memory structure can be located in the same layer; and the top electrode 504 of the first phase change memory structure and the top electrode 505 of the second phase change memory structure can be located in the same layer.

[0235] In the semiconductor structure provided in the above embodiments, the bottom electrode, heating structure 512, phase change layer 513, and top electrode of the first phase change memory structure 520 and the second phase change memory structure are located in the same layer. In this way, during the fabrication of the above semiconductor structure, the bottom electrode 303 of the first phase change memory structure and the bottom electrode 304 of the second phase change memory structure can be formed simultaneously in one process. Alternatively, the heating structure 512 of the first phase change memory structure 520 and the heating structure 512 of the second phase change memory structure can be formed simultaneously in one process. Alternatively, the phase change layer 513 of the first phase change memory structure 520 and the phase change layer 513 of the second phase change memory structure can be formed simultaneously in one process. Alternatively, the top electrode 504 of the first phase change memory structure and the top electrode 505 of the second phase change memory structure can be formed simultaneously in one process, further reducing the number of process steps and lowering the cost.

[0236] In one embodiment, the width of the heating structure 512 is less than 1 / 5 of the width of the bottom electrode or the top electrode. It is understood that this application does not specifically limit the ratio between the width of the heating structure 512 and the width of the bottom electrode or the top electrode. Optionally, the width of the heating structure 512 can be 1 / 10, 1 / 8 or 1 / 6 of the width of the bottom electrode or the top electrode, etc.

[0237] Please continue reading. Figure 17 In one embodiment, the semiconductor structure may further include an air gap 506. This application does not limit the specific location of the air gap 506. In one embodiment, the air gap 506 may be located between the heating structure 512 of the first phase change memory structure 520 and the heating structure 512 of the second phase change memory structure to reduce the parasitic capacitance between the heating structure 512 of the first phase change memory structure 520 and the heating structure 512 of the second phase change memory structure. This application also does not limit the top height of the air gap. In another possible embodiment, the top of the air gap 506 may be higher than the lower surface of the top electrode 504 of the first phase change memory structure and the lower surface of the top electrode 505 of the second phase change memory structure.

[0238] Please continue reading. Figure 17 In one embodiment, the first bit line 801 may be located in the same layer as the second bit line 802.

[0239] In the semiconductor structure provided in the above embodiments, the first bit line and the second bit line are located in the same layer, so that the first bit line and the second bit line can be formed simultaneously in one process during the fabrication of the semiconductor structure, further reducing the number of process steps and lowering the cost.

[0240] Please continue reading. Figure 17 In one embodiment, the top electrode 505 of the second phase change memory structure and the bottom electrode 303 of the first phase change memory structure can both be electrically connected to the first end of the transistor 1 via the first interconnect 203.

[0241] Please continue reading. Figure 17 In one embodiment, the first interconnect 203 can be connected to the first terminal of the transistor 1 via the first plug 202; the bottom electrode 303 of the first phase-change memory structure can be connected to the first interconnect 203 via the second plug 302, and the top electrode 504 of the first phase-change memory structure can be connected to the first bit line 801 via the third plug 703; at this time, the bottom electrode 304 of the second phase-change memory structure can be connected to the second bit line 802 via the fourth plug 704, and the top electrode 505 of the second phase-change memory structure can be electrically connected to the first interconnect 203.

[0242] Please continue reading. Figure 17In one embodiment, the semiconductor structure may further include a second interconnect 307; the second interconnect 307 is located on the first interconnect 203, connected to the first interconnect 203 via a fifth plug 306, and electrically connected to the top electrode 505 of the second phase change memory structure.

[0243] Please continue reading. Figure 17 In one embodiment, the semiconductor structure may further include a third interconnect 803; the third interconnect 803 is located on the second interconnect 307, connected to the second interconnect 307 via a sixth plug 707, and connected to the top electrode 505 of the second phase change memory structure via a seventh plug 708.

[0244] It should be noted that, as Figure 17 As shown, in one embodiment, the semiconductor structure may further include a first dielectric layer 2, a second dielectric layer 3, a third dielectric layer 4, a fourth dielectric layer 5, a fifth dielectric layer 6, and a sixth dielectric layer 7 stacked sequentially from bottom to top; (The following is a description of the semiconductor structure in conjunction with the semiconductor structure.) Figure 17 The first dielectric layer 2, the second dielectric layer 3, the third dielectric layer 4, the fourth dielectric layer 5, the fifth dielectric layer 6, and the sixth dielectric layer 7 will be described in more detail.

[0245] The first dielectric layer 2 covers the transistor 1, the first plug 202 is located inside the first dielectric layer 2, and the first interconnect 203 is located on the first dielectric layer 2; the second dielectric layer 3 is located on the first dielectric layer 2, and the second plug 302 is located inside the second dielectric layer 3; the first phase change memory structure 520 and the second phase change memory structure 521 are located inside the third dielectric layer 4, the fourth dielectric layer 5 and the fifth dielectric layer 6 stacked from bottom to top; the sixth dielectric layer 7 is located on the fifth dielectric layer 6, the third plug 703 is located inside the sixth dielectric layer 7, and the fourth plug 704 is located inside the sixth dielectric layer 7, the fifth dielectric layer 6 and the fourth dielectric layer 5.

[0246] Specifically, the bottom electrode 303 of the first phase change memory structure and the bottom electrode 304 of the second phase change memory structure can both be located within the third dielectric layer 4; the heating structure 512 and the phase change layer 513 can both be located within the fourth dielectric layer 5, and the air gap 506 can also be located within the fourth dielectric layer 5; the top electrode 504 of the first phase change memory structure and the top electrode 505 of the second phase change memory structure can both be located within the fifth dielectric layer 6.

[0247] Specifically, the fifth plug 306 can also be located within the second dielectric layer 3, in which case the second interconnect 307 can be located within the third dielectric layer 4; the sixth plug 707 can be located within the sixth dielectric layer 7, the fifth dielectric layer 6 and the fourth dielectric layer 5, the seventh plug 708 can be located within the sixth dielectric layer 7; and the third interconnect 803 can be located on the sixth dielectric layer 7.

[0248] Specifically, the eighth plug 205 can also be located inside the first dielectric layer 2, in which case the control line 206 can be located on the first dielectric layer 2.

[0249] It is understood that this application does not limit the specific form of the electrical connection between the top electrode 505 of the second phase change memory structure and the first interconnect 203. Figure 17 As shown in some optional embodiments, the top electrode 505 of the second phase change memory structure is connected to the first interconnect 203 in sequence via the seventh plug 708, the third interconnect 803, the sixth plug 707, the second interconnect 307 and the fifth plug 306; in other optional embodiments, the top electrode 505 of the second phase change memory structure may be electrically connected to the first interconnect 203 in other forms.

[0250] Other forms of electrical connection between the top electrode 505 of the second phase change memory structure and the first interconnect 203 are described in detail below.

[0251] Please see Figure 18 In one embodiment, the top electrode 505 of the second phase change memory structure can also be directly connected to the second interconnect 307 via the ninth plug 901. That is, the top electrode 505 of the second phase change memory structure can be connected to the first interconnect 203 in sequence via the ninth plug 901, the second interconnect 307 and the fifth plug 306.

[0252] In the semiconductor structure provided in the above embodiments, the top electrode of the second phase change memory structure is directly connected to the second interconnect line via the ninth plug, which reduces the lateral dimension of the semiconductor structure, thereby increasing heat dissipation and density.

[0253] It should be understood that, although Figure 1 , Figure 2 , Figure 7 , Figure 10 , Figure 18 , Figure 25 , Figure 27 , Figure 34 and Figure 35 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 , Figure 2 , Figure 7 , Figure 10 , Figure 18 , Figure 25 , Figure 27 , Figure 34 and Figure 35At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0254] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0255] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized by, include: transistor; A first phase-change memory structure, wherein the bottom electrode of the first phase-change memory structure is electrically connected to the first terminal of the transistor; The second phase change memory structure has its top electrode electrically connected to the first terminal of the transistor. The first phase change memory structure is in a crystalline phase and the second phase change memory structure is in an amorphous phase, or vice versa. The first line is electrically connected to the top electrode of the first phase change memory structure; The second bit line is electrically connected to the bottom electrode of the second phase change memory structure; Both the first phase change memory structure and the second phase change memory structure include: a bottom electrode, a heating structure, a phase change layer, and a top electrode stacked sequentially from bottom to top; The bottom electrode of the first phase change memory structure and the bottom electrode of the second phase change memory structure are located in the same layer. The heating structure of the first phase change memory structure and the heating structure of the second phase change memory structure are located in the same layer. The phase change layer of the first phase change memory structure and the phase change layer of the second phase change memory structure are located in the same layer. The top electrode of the first phase change memory structure and the top electrode of the second phase change memory structure are located in the same layer.

2. The semiconductor structure of claim 1, wherein, The width of the heating structure is less than 1 / 5 of the width of the bottom electrode or the top electrode; The semiconductor structure also includes: The air gap is located between the heating structure of the first phase change memory structure and the heating structure of the second phase change memory structure.

3. The semiconductor structure of claim 2, wherein, The top of the air gap is higher than the lower surface of the top electrode of the first phase change memory structure and the lower surface of the top electrode of the second phase change memory structure.

4. The semiconductor structure of claim 1, wherein, The first phase change memory structure includes a bottom electrode, a heating structure, a phase change layer, and a top electrode stacked sequentially from bottom to top; the second phase change memory structure includes a top electrode, a phase change layer, a heating structure, and a bottom electrode stacked sequentially from bottom to top. The bottom electrode of the second phase change memory structure is higher than the top electrode of the first phase change memory structure, or The bottom electrode of the second phase change memory structure is flush with the top electrode of the first phase change memory structure.

5. The semiconductor structure of claim 4, wherein, The first bit line and the second bit line are located in the same layer.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that, The top electrode of the second phase-change memory structure and the bottom electrode of the first phase-change memory structure are both electrically connected to the first terminal of the transistor via a first interconnect.

7. The semiconductor structure according to claim 6, characterized in that, The first interconnect is connected to the first terminal of the transistor via a first plug; The bottom electrode of the first phase-change memory structure is connected to the first interconnect line via a second plug, and the top electrode of the first phase-change memory structure is connected to the first bit line via a third plug; The bottom electrode of the second phase change memory structure is connected to the second bit line via a fourth plug, and the top electrode of the second phase change memory structure is electrically connected to the first interconnect line.

8. The semiconductor structure of claim 7, wherein, Also includes: The second interconnect line is located on the first interconnect line, connected to the first interconnect line via the fifth plug, and electrically connected to the top electrode of the second phase change memory structure.

9. The semiconductor structure of claim 8, wherein, Also includes: The third interconnect is located on the second interconnect, connected to the second interconnect via the sixth plug, and connected to the top electrode of the second phase change memory structure via the seventh plug.

10. A method for fabricating a semiconductor structure, characterized in that, include: Forming transistors; Forming a first phase-change memory structure, a second phase-change memory structure, a first bit line, and a second bit line, including: A first dielectric layer is formed, which covers the transistor; A first interconnect hole is formed within the first dielectric layer, the first interconnect hole exposing a first end of the transistor; A first plug is formed in the first interconnect hole, and a first interconnect line is formed on the upper surface of the first dielectric layer. The first interconnect line is connected to the first end of the transistor via the first plug. A second dielectric layer is formed on the first dielectric layer, and a second interconnection hole is formed in the second dielectric layer, the second interconnection hole exposing the first interconnection line; A second plug is formed within the second interconnecting hole; A third dielectric layer, a fourth dielectric layer, and a fifth dielectric layer are formed sequentially on the second dielectric layer, and a first phase change memory structure and a second phase change memory structure are formed within the third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer; the bottom electrode of the first phase change memory structure is connected to the first interconnect line via the second plug, and the top electrode of the second phase change memory structure is electrically connected to the first interconnect line; A sixth dielectric layer is formed on the fifth dielectric layer, and a third interconnection hole is formed in the sixth dielectric layer. A fourth interconnection hole is formed in the sixth dielectric layer, the fifth dielectric layer, and the fourth dielectric layer. The third interconnection hole exposes the top electrode of the first phase change memory structure, and the fourth interconnection hole exposes the bottom electrode of the second phase change memory structure. A third plug is formed within the third interconnect hole, and a fourth plug is formed within the fourth interconnect hole. A first bit line and a second bit line are formed on the sixth dielectric layer. The first bit line is electrically connected to the top electrode of the first phase change memory structure via the third plug, and the second bit line is electrically connected to the bottom electrode of the second phase change memory structure via the fourth plug. The first phase change memory structure is in a crystalline phase and the second phase change memory structure is in an amorphous phase, or vice versa. The bottom electrode of the first phase-change memory structure is electrically connected to the first terminal of the transistor; The top electrode of the second phase-change memory structure is electrically connected to the first terminal of the transistor; The first bit line is electrically connected to the top electrode of the first phase-change memory structure; The second bit line is electrically connected to the bottom electrode of the second phase change memory structure.

11. The method of claim 10, wherein the semiconductor structure is prepared by a method comprising: The method of forming a third, fourth, and fifth dielectric layer stacked sequentially on the second dielectric layer, and forming a first phase-change memory structure and a second phase-change memory structure within the third, fourth, and fifth dielectric layers, includes: A pair of spaced-apart bottom electrodes are formed on the second dielectric layer, serving as the bottom electrodes of the first phase change memory structure and the second phase change memory structure, respectively. A third dielectric layer is formed on the second dielectric layer, and the bottom electrode of the first phase change memory structure and the bottom electrode of the second phase change memory structure are both located in the third dielectric layer. A fourth dielectric layer is formed on the third dielectric layer, the fourth dielectric layer covering the bottom electrode; and through holes are formed in the fourth dielectric layer, the through holes being disposed one-to-one with the bottom electrode and exposing the bottom electrode; an air gap is formed in the fourth dielectric layer, the air gap being located between the through holes; A heating structure and a phase change layer are formed within the through hole; A pair of spaced-apart top electrodes are formed on the fourth dielectric layer, the top electrodes being in contact with the phase change layer; and a fifth dielectric layer is formed on the fourth dielectric layer, the fifth dielectric layer covering the exposed surface of the fourth dielectric layer.

12. The method of claim 11, wherein the semiconductor structure is prepared by a method comprising: The formation of a heating structure and a phase change layer within the through-hole includes: A heating material layer is formed inside the through hole and on the upper surface of the fourth dielectric layer; Remove the heating material layer located on the upper surface of the fourth dielectric layer, and etch back the heating material layer located in the through hole to obtain the heating structure whose upper surface is lower than the top of the through hole; A phase change material layer is formed inside the through hole and on the upper surface of the fourth dielectric layer; The phase change material layer located on the upper surface of the fourth dielectric layer is removed, and the phase change material layer remaining in the through hole is the phase change layer.

13. The method of claim 11, wherein the semiconductor structure is prepared by a method comprising: While forming the second interconnect hole in the second dielectric layer, a fifth interconnect hole is also formed in the second dielectric layer; While forming a second plug in the second interconnecting hole, a fifth plug is also formed in the fifth interconnecting hole; While forming a pair of spaced-apart bottom electrodes on the second dielectric layer, a second interconnect line is also formed between the bottom electrodes, with a gap between the second interconnect line and the bottom electrodes, and the third dielectric layer fills the gap between the second interconnect line and the bottom electrodes; While forming a fourth interconnect hole in the sixth dielectric layer, the fifth dielectric layer and the fourth dielectric layer, a sixth interconnect hole is also formed in the sixth dielectric layer, the fifth dielectric layer and the fourth dielectric layer, and a seventh interconnect hole is formed in the sixth dielectric layer. The sixth interconnect hole exposes the second interconnect line, and the seventh interconnect hole exposes the top electrode of the second phase change memory structure. A third plug is formed in the third interconnecting hole, and a fourth plug is formed in the fourth interconnecting hole. At the same time, a sixth plug is formed in the sixth interconnecting hole, and a seventh plug is formed in the seventh interconnecting hole. While forming the first bit line and the second bit line on the sixth dielectric layer, a third interconnect line is also formed on the sixth dielectric layer.

14. The method of claim 10, wherein the semiconductor structure is prepared by a method comprising: The formation of the first phase change memory structure, the second phase change memory structure, the first bit line, and the second bit line includes: A first dielectric layer is formed, which covers the transistor; A first interconnect hole is formed within the first dielectric layer, the first interconnect hole exposing a first end of the transistor; A first plug is formed in the first interconnect hole, and a first interconnect line is formed on the upper surface of the first dielectric layer. The first interconnect line is connected to the first end of the transistor via the first plug. A second dielectric layer is formed on the first dielectric layer, and a second interconnect is formed within the second dielectric layer, the second interconnect exposing the first interconnect; simultaneously, a fifth interconnect is formed within the second dielectric layer. A second plug is formed in the second interconnecting hole; simultaneously, a fifth plug is also formed in the fifth interconnecting hole; A third, fourth, and fifth dielectric layer are formed sequentially on the second dielectric layer, and a first phase-change memory structure is formed within the third, fourth, and fifth dielectric layers. The bottom electrode of the first phase-change memory structure is connected to the first interconnect line via the second plug. Simultaneously, a second interconnect line is formed within the third dielectric layer, and a gap exists between the second interconnect line and the bottom electrode of the first phase-change memory structure. The third dielectric layer fills the gap between the second interconnect line and the bottom electrode. A sixth dielectric layer is formed on the fifth dielectric layer, and a third interconnection hole is formed in the sixth dielectric layer, the third interconnection hole exposing the top electrode of the first phase change memory structure; A third plug is formed in the third interconnect hole, and a first bit line is formed on the sixth dielectric layer. The first bit line is electrically connected to the top electrode of the first phase change memory structure via the third plug. A seventh dielectric layer is formed on the sixth dielectric layer, and the seventh dielectric layer covers the first bit line; A ninth interconnect is formed within the seventh, sixth, fifth, and fourth dielectric layers, and the ninth interconnect exposes the second interconnect. A ninth plug is formed in the ninth interconnect hole, and an eighth and ninth dielectric layers are formed sequentially on the seventh dielectric layer, and a second phase change memory structure is formed in the eighth and ninth dielectric layers; the top electrode of the second phase change memory structure is connected to the second interconnect line via the ninth plug; A tenth dielectric layer is formed on the ninth dielectric layer, and a fourth interconnection hole is formed in the tenth dielectric layer, the fourth interconnection hole exposing the bottom electrode of the second phase change memory structure; A fourth plug is formed in the fourth interconnect hole, and a second bit line is formed on the tenth dielectric layer. The second bit line is electrically connected to the bottom electrode of the second phase change memory structure via the fourth plug.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, The method of forming an eighth dielectric layer and a ninth dielectric layer stacked sequentially on the seventh dielectric layer, and forming a second phase-change memory structure within the eighth dielectric layer and the ninth dielectric layer, includes: The top electrode of the second phase change memory structure is formed on the seventh dielectric layer; An eighth dielectric layer is formed on the seventh dielectric layer, and the top electrode of the second phase change memory structure is located within the eighth dielectric layer; A via is formed in the eighth dielectric layer, the via being disposed corresponding to the top electrode of the second phase change memory structure and exposing the top electrode of the second phase change memory structure; A phase change layer and a heating structure are formed within the through hole; A bottom electrode of a second phase change memory structure is formed on the eighth dielectric layer, and the bottom electrode of the second phase change memory structure is in contact with the heating structure; and a ninth dielectric layer is formed on the eighth dielectric layer, and the ninth dielectric layer covers the exposed surface of the eighth dielectric layer.

16. The method of claim 15, wherein the semiconductor structure is prepared by a method comprising: The formation of a phase change layer and heating structure within the through-hole includes: A phase change material layer is formed inside the through hole and on the upper surface of the eighth dielectric layer; Remove the phase change material layer located on the upper surface of the eighth dielectric layer, and etch back the phase change material layer located in the via to obtain the phase change layer with its upper surface lower than the top of the via; A heating material layer is formed inside the through hole and on the upper surface of the eighth dielectric layer; The heating material layer located on the upper surface of the eighth dielectric layer is removed, and the heating material layer remaining in the through hole constitutes the heating structure.

17. The method of claim 10, wherein: The formation of the first phase change memory structure, the second phase change memory structure, the first bit line, and the second bit line includes: A first dielectric layer is formed, which covers the transistor; A first interconnect hole is formed within the first dielectric layer, the first interconnect hole exposing a first end of the transistor; A first plug is formed in the first interconnect hole, and a first interconnect line is formed on the upper surface of the first dielectric layer. The first interconnect line is connected to the first end of the transistor via the first plug. A second dielectric layer is formed on the first dielectric layer, and a second interconnect is formed within the second dielectric layer, the second interconnect exposing the first interconnect; simultaneously, a fifth interconnect is formed within the second dielectric layer. A second plug is formed in the second interconnecting hole; simultaneously, a fifth plug is also formed in the fifth interconnecting hole; A third, fourth, and fifth dielectric layer are formed sequentially on the second dielectric layer, and a first phase change memory structure and a second phase change memory structure are formed within the third, fourth, and fifth dielectric layers; the bottom electrode of the first phase change memory structure is connected to the first interconnect line via the second plug, and the top electrode of the second phase change memory structure is connected to the first interconnect line via the fifth plug. A sixth dielectric layer is formed on the fifth dielectric layer, and a third interconnect and a fourth interconnect are formed in the sixth dielectric layer; the third interconnect exposes the top electrode of the first phase change memory structure, and the fourth interconnect exposes the bottom electrode of the second phase change memory structure. A third plug is formed in the third interconnect hole, and a fourth plug is formed in the fourth interconnect hole; and a first bit line and a second bit line are formed on the sixth dielectric layer; the first bit line is electrically connected to the top electrode of the first phase change memory structure via the third plug, and the second bit line is electrically connected to the bottom electrode of the second phase change memory structure via the fourth plug.

18. The method of claim 17, wherein the semiconductor structure is prepared by a method comprising: The method of forming a third, fourth, and fifth dielectric layer stacked sequentially on the second dielectric layer, and forming a first phase-change memory structure and a second phase-change memory structure within the third, fourth, and fifth dielectric layers, includes: The bottom electrode of the first phase change memory structure and the top electrode of the second phase change memory structure are formed on the second dielectric layer at intervals; A third dielectric layer is formed on the second dielectric layer, and the bottom electrode of the first phase change memory structure and the top electrode of the second phase change memory structure are both located in the third dielectric layer. A fourth dielectric layer is formed on the third dielectric layer, the fourth dielectric layer covering the bottom electrode of the first phase change memory structure and the top electrode of the second phase change memory structure; and a first through hole is formed in the fourth dielectric layer, the first through hole being correspondingly disposed to the bottom electrode of the first phase change memory structure and exposing the bottom electrode of the first phase change memory structure. A heating structure for the first phase change storage structure is formed within the first through hole; A second through-hole is formed in the fourth dielectric layer, the second through-hole being disposed corresponding to the top electrode of the second phase change memory structure, and exposing the top electrode of the second phase change memory structure; A phase change material layer is formed in the first through hole and the second through hole; Remove the phase change material layer located on the upper surface of the fourth dielectric layer, and etch back the phase change material layer in the second via to obtain the phase change layer of the first phase change memory structure whose upper surface is flush with the fourth dielectric layer and the phase change layer of the second phase change memory structure whose upper surface is lower than the top of the second via. A heating material layer is formed inside the second through hole and on the upper surface of the fourth dielectric layer; The heating material layer located on the upper surface of the fourth dielectric layer is removed, and the heating material layer remaining in the second through hole is the heating structure of the second phase change storage structure.

19. The method of claim 18, wherein the semiconductor structure is prepared by a method comprising: The heating structure that forms the first phase change storage structure within the first through hole includes: A heating material layer is formed inside the first through hole and on the upper surface of the fourth dielectric layer; The heating material layer located on the upper surface of the fourth dielectric layer is removed, and the heating material layer located in the first through hole is etched back to obtain a heating structure whose upper surface is lower than the top of the first phase change memory structure.

20. The method for preparing a semiconductor structure according to any one of claims 10 to 19, characterized in that, While forming a first interconnect hole in the first dielectric layer, an eighth interconnect hole is also formed in the first dielectric layer, and the eighth interconnect hole exposes the second end of the transistor; While forming a first plug in the first interconnecting hole, an eighth plug is also formed in the eighth interconnecting hole; While forming a first interconnect line on the upper surface of the first dielectric layer, a control line is also formed on the upper surface of the first dielectric layer, and there is a gap between the control line and the first interconnect line.

21. The method of claim 20, wherein the semiconductor structure is prepared by a method comprising: After forming the first interconnect and the control line, and before forming the second dielectric layer, the method further includes: An etch stop layer is formed on the first interconnect, the control line, and the exposed first dielectric layer.

22. The method of claim 21, wherein the semiconductor structure is prepared by a method comprising: After forming the etching stop layer and before forming the second dielectric layer, the method further includes: A filling dielectric layer is formed on the upper surface of the etch stop layer between the first interconnect and the control line, the filling dielectric layer filling the gap between the first interconnect and the control line.

23. The method of claim 20, wherein the semiconductor structure is prepared by a method comprising: While forming the first interconnect hole and the eighth interconnect hole in the first dielectric layer, a ninth interconnect hole is also formed in the first dielectric layer, and the ninth interconnect hole exposes the control terminal of the transistor; While forming a first plug in the first interconnect hole and an eighth plug in the eighth interconnect hole, a ninth lead-out structure is also formed in the ninth interconnect hole.

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