Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof, which comprises a substrate, a transistor comprising a control end, a first end and a second end, the first end and the second end being located in the substrate, and the control end being located between the first end and the second end; a first magnetic storage structure, a bottom electrode of which is electrically connected with the first end of the transistor; a second magnetic storage structure, a top electrode of which is electrically connected with the first end of the transistor, and the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure being located in the same layer; a first bit line, which is electrically connected with the top electrode of the first magnetic storage structure; a second bit line, which is electrically connected with the bottom electrode of the second magnetic storage structure; and a selection line, which is electrically connected with the second end of the transistor. The semiconductor structure does not need an external reference signal, has high reading speed, large reading margin and high reliability, and the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure can be formed simultaneously in one process in the preparation process, so that the process steps are reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] MRAM (Magnetoresistive Random Access Memory) is a non-volatile magnetic random access memory. MRAM memory consists of multiple storage elements that exhibit magnetoresistive effects, such as giant magnetoresistance (GMR) or tunneling magnetoresistance (TMR), allowing data to be written and read.

[0003] Currently, the most common internal combination of MRAM memory is the 1T-1MTJ (1transistor-1magnetic tunnel junction) unit. 1T-1MTJ has the advantages of small area, low manufacturing cost and good integration with CMOS process.

[0004] However, 1T-1MTJ also has the disadvantages of requiring a reference signal and having a small read margin. Improving the read margin of MRAM memory is an urgent problem that needs to be solved. Summary of the Invention

[0005] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the problem that a reference signal needs to be provided and a small reading margin is required in the prior art.

[0006] According to some embodiments, the present application provides a semiconductor structure, including:

[0007] substrate;

[0008] a transistor comprising a control terminal, a first terminal, and a second terminal; the first terminal and the second terminal are located in the substrate, and the control terminal is located between the first terminal and the second terminal;

[0009] a first magnetic storage structure, wherein a bottom electrode of the first magnetic storage structure is electrically connected to the first terminal of the transistor;

[0010] a second magnetic storage structure, wherein a top electrode of the second magnetic storage structure is electrically connected to the first end of the transistor, and a bottom electrode of the first magnetic storage structure and a bottom electrode of the second magnetic storage structure are located in the same layer;

[0011] a first bit line electrically connected to a top electrode of the first magnetic storage structure;

[0012] a second bit line electrically connected to the bottom electrode of the second magnetic storage structure;

[0013] The selection line is electrically connected to the second terminal of the transistor.

[0014] In one embodiment, the control terminal is located in the substrate between the first terminal and the second terminal, and the selection line is located in the second terminal.

[0015] In one embodiment, the bottom of the selection line is flush with the bottom of the control terminal.

[0016] In one embodiment, the height of the selection line is the same as the height of the control terminal.

[0017] In one embodiment, the control end is located above the substrate between the first end and the second end;

[0018] The selection line is located above the second end, and a height of the selection line is flush with a height of the control end.

[0019] In one embodiment, the semiconductor structure further comprises:

[0020] a first conductive layer, located on the substrate and connected to the first terminal of the transistor via a first interconnect structure; a bottom electrode of the first magnetic storage structure is connected to the first conductive layer via a second interconnect structure, and a top electrode of the first magnetic storage structure is connected to the first bit line via a third interconnect structure; and the second bit line is connected to the bottom electrode of the second magnetic storage structure via a fourth interconnect structure;

[0021] a second conductive line layer, located on the first conductive line layer and connected to the first conductive line layer via a fifth interconnect structure;

[0022] The third conductive line layer is located on the second conductive line layer, is connected to the second conductive line layer via a sixth interconnect structure, and is connected to the top electrode of the second magnetic storage structure via a seventh interconnect structure.

[0023] In one embodiment, the second conductive line layer and the bottom electrode of the first magnetic storage structure are located in the same layer; the third conductive line layer and the first bit line and the second bit line are located in the same layer.

[0024] In one embodiment, the control terminal of the transistor is a gate, the first terminal of the transistor is a drain, the second terminal of the transistor is a source, and the selection line is a source line;

[0025] The source line is located in the same layer as the first conductive line layer, and there is a gap between the source line and the first conductive line layer; the source line is electrically connected to the second end of the transistor via an eighth interconnect structure.

[0026] In one embodiment, the first magnetic storage structure and the second magnetic storage structure each include: the bottom electrode, the magnetic tunnel junction structure, and the top electrode stacked sequentially from bottom to top;

[0027] The magnetic tunnel junction structure includes: a fixed layer, a magnetic tunnel junction layer and a free layer stacked sequentially from bottom to top, and the fixed layer, magnetic tunnel junction layer and free layer of the first magnetic storage structure and the second magnetic storage structure are respectively located in the same layer.

[0028] On the other hand, the present application also provides a method for preparing a semiconductor structure, comprising the following steps:

[0029] providing a substrate;

[0030] forming a transistor, the transistor comprising a first terminal and a second terminal located in the substrate, and a control terminal located between the first terminal and the second terminal;

[0031] forming a first magnetic storage structure, a second magnetic storage structure, a first bit line, and a second bit line; wherein the bottom electrode of the first magnetic storage structure is electrically connected to the first terminal of the transistor, the top electrode of the second magnetic storage structure is electrically connected to the first terminal of the transistor, the first bit line is electrically connected to the top electrode of the first magnetic storage structure, the second bit line is electrically connected to the bottom electrode of the second magnetic storage structure, and the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure are located on the same layer;

[0032] A selection line is formed that is electrically connected to the second terminal of the transistor.

[0033] In one embodiment, forming the transistor includes:

[0034] forming a first trench in the substrate;

[0035] forming the control terminal in the first trench;

[0036] forming the first end and the second end in the substrate;

[0037] The forming of a selection line electrically connected to the second terminal of the transistor comprises:

[0038] forming a second groove in the second end;

[0039] The selection line is formed in the second trench.

[0040] In one embodiment, the forming of the first magnetic storage structure, the second magnetic storage structure, the first bit line, and the second bit line comprises the following steps:

[0041] forming a first dielectric layer, wherein the first dielectric layer covers the transistor;

[0042] forming a first interconnection hole in the first dielectric layer, wherein the first interconnection hole exposes the first end of the transistor;

[0043] forming a first interconnect structure in the first interconnect hole, and forming a first conductive line layer on the upper surface of the first dielectric layer, wherein the first conductive line layer is electrically connected to the first terminal of the transistor via the first interconnect structure;

[0044] forming a second dielectric layer on the first dielectric layer, and forming a second interconnection hole in the second dielectric layer, wherein the second interconnection hole exposes the first conductive line layer;

[0045] forming a second interconnection structure in the second interconnection hole;

[0046] forming a third dielectric layer, a first magnetic storage structure, a second magnetic storage structure, and a fourth dielectric layer on the second dielectric layer; wherein the bottom electrode of the first magnetic storage structure is connected to the first conductive line layer via a second interconnect structure;

[0047] forming a fifth dielectric layer on the fourth dielectric layer, forming a third interconnection hole in the fifth dielectric layer, and forming a fourth interconnection hole in the fifth dielectric layer and the fourth dielectric layer, wherein the third interconnection hole exposes the top electrode of the first magnetic storage structure, and the fourth interconnection hole exposes the bottom electrode of the second magnetic storage structure;

[0048] A third interconnect structure is formed in the third interconnect hole, a fourth interconnect structure is formed in the fourth interconnect hole, and the first bit line and the second bit line are formed on the fifth dielectric layer, the first bit line is electrically connected to the top electrode of the first magnetic storage structure via the third interconnect structure, and the second bit line is electrically connected to the bottom electrode of the second magnetic storage structure via the fourth interconnect structure.

[0049] In one embodiment, forming the third dielectric layer, the first magnetic storage structure, the second magnetic storage structure, and the fourth dielectric layer on the second dielectric layer includes the following steps:

[0050] forming a pair of bottom electrodes spaced apart from each other on the second dielectric layer, serving as the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure respectively;

[0051] forming a third dielectric layer on the second dielectric layer, wherein the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure are both located in the third dielectric layer;

[0052] forming a magnetic tunnel junction structure and a top electrode on the bottom electrode;

[0053] forming a fourth dielectric layer on the third dielectric layer, wherein the fourth dielectric layer covers the bottom electrode;

[0054] In one embodiment, the magnetic tunnel junction structure includes: a fixed layer, a magnetic tunnel junction layer, and a free layer stacked sequentially from bottom to top;

[0055] The step of forming a magnetic tunnel junction structure and a top electrode on the bottom electrode comprises the following steps:

[0056] forming a fixed material layer, a magnetic tunnel junction material layer, a free material layer and a top electrode material layer stacked sequentially from bottom to top on the upper surface of the bottom electrode;

[0057] The fixed material layer, magnetic tunnel junction material layer, free material layer and top electrode material layer stacked sequentially from bottom to top are patterned to obtain the fixed layer, magnetic tunnel junction layer, free layer and top electrode stacked sequentially from bottom to top.

[0058] In one embodiment, while forming the second interconnection hole in the second dielectric layer, a fifth interconnection hole is also formed in the second dielectric layer; while forming the second interconnection structure in the second interconnection hole, a fifth interconnection structure is also formed in the fifth interconnection hole;

[0059] A pair of spaced-apart bottom electrodes are formed on the second dielectric layer, and a second conductive layer is formed between the bottom electrodes. The second conductive layer is connected to the first conductive layer via the fifth interconnect structure, and a gap is formed between the second conductive layer and the bottom electrodes. The third dielectric layer fills the gap between the second conductive layer and the bottom electrodes.

[0060] Simultaneously with forming a fourth interconnect hole in the fifth dielectric layer and the fourth dielectric layer, a sixth interconnect hole is also formed in the fifth dielectric layer and the fourth dielectric layer, and a seventh interconnect hole is also formed in the fifth dielectric layer, the sixth interconnect hole exposing the second metal line layer, and the seventh interconnect hole exposing the top electrode of the second magnetic storage structure; simultaneously with forming a third interconnect structure in the third interconnect hole and a fourth interconnect structure in the fourth interconnect hole, a sixth interconnect structure is also formed in the sixth interconnect hole, and a seventh interconnect structure is also formed in the seventh interconnect hole; simultaneously with forming the first bit line and the second bit line on the fifth dielectric layer, a third conductive layer is also formed on the fifth dielectric layer, the third conductive layer being connected to the second conductive layer via the sixth interconnect structure, and being connected to the top electrode of the second magnetic storage structure via the seventh interconnect structure.

[0061] In one embodiment, the control terminal of the transistor is a gate, the first terminal of the transistor is a drain, the second terminal of the transistor is a source, and the selection line is a source line;

[0062] while forming the first interconnection hole in the first dielectric layer, also forming an eighth interconnection hole in the first dielectric layer, wherein the eighth interconnection hole exposes the second end of the transistor;

[0063] forming an eighth interconnection structure in the eighth interconnection hole while forming a first interconnection structure in the first interconnection hole;

[0064] While forming a first conductive line layer on the upper surface of the first dielectric layer, a source line is also formed on the upper surface of the first dielectric layer. The source line is electrically connected to the second end of the transistor via the eighth interconnect structure, and a gap is formed between the source line and the first conductive line layer.

[0065] In one embodiment, after forming the source line and the first conductive line layer and before forming the second dielectric layer, the following steps are further included:

[0066] An etch stop layer is formed on the source line, the first conductive line layer and the exposed first dielectric layer.

[0067] In one embodiment, after forming the etch stop layer and before forming the second dielectric layer, the following steps are further included:

[0068] A filling dielectric layer is formed on the upper surface of the etch stop layer between the source line and the first conductive line layer, and the filling dielectric layer fills the gap between the source line and the first conductive line layer.

[0069] In one embodiment, while forming the first interconnection hole and the eighth interconnection hole in the first dielectric layer, a ninth lead hole is also formed in the first dielectric layer, wherein the ninth lead hole exposes the control terminal of the transistor;

[0070] forming a first interconnection structure in the first interconnection hole, forming an eighth interconnection structure in the eighth interconnection hole, and forming a ninth interconnection structure in the ninth interconnection hole;

[0071] A first conductive line layer and the source line are formed on the upper surface of the first dielectric layer, and a word line is also formed on the upper surface of the first dielectric layer to connect to the control terminal of the transistor.

[0072] The semiconductor structure and preparation method provided by this application may have the following advantages:

[0073] The semiconductor structure provided by the present application forms a complementary structure by two magnetic storage structures, wherein the first magnetic storage structure and the second magnetic storage structure can always be configured in a complementary state (for example, the first magnetic storage structure is in a parallel state R P , while the second magnetic storage structure is in the antiparallel state R AP , or vice versa), so that it does not require an external reference signal, has a fast reading speed, a large reading margin, and high reliability, and can reduce the influence of the tailing bit effect on the reading margin; at the same time, since the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure are located in the same layer, the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure can be formed simultaneously in one step during the preparation of the semiconductor structure, thereby reducing the process steps and reducing the cost.

[0074] The method for preparing a semiconductor structure provided by the present application forms a complementary structure by forming two magnetic storage structures, wherein the first magnetic storage structure and the second magnetic storage structure can always be configured in a complementary state (for example, the first magnetic storage structure is in a parallel state R P , while the second magnetic storage structure is in the antiparallel state R AP , or vice versa), so that the semiconductor structure prepared thereby does not require an external reference signal, has a fast reading speed, a large reading margin, and high reliability, and can reduce the influence of the tailing bit effect on the reading margin; at the same time, since the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure are located in the same layer, the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure can be formed simultaneously in one step during the preparation process, thereby reducing the process steps and lowering the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0076] Figure 1 A flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present application;

[0077] Figure 2 A flowchart of step S3 in the method for preparing a semiconductor structure provided in one embodiment of the present application;

[0078] Figure 3 A schematic cross-sectional view of the structure obtained in step S32 in the method for preparing a semiconductor structure provided in one embodiment of the present application;

[0079] Figure 4 A schematic cross-sectional view of the structure obtained in step S33 in the method for preparing a semiconductor structure provided in one embodiment of the present application;

[0080] Figure 5 A schematic cross-sectional view of a structure obtained by forming an etch stop layer on a source line, a first conductive line layer, and an exposed first dielectric layer in a method for fabricating a semiconductor structure provided in one embodiment of the present application;

[0081] Figure 6 A schematic cross-sectional view of the structure obtained in step S34 in the method for preparing a semiconductor structure provided in one embodiment of the present application;

[0082] Figure 7 A schematic cross-sectional view of the structure obtained from step S361 to step S362 in the method for preparing a semiconductor structure provided in one embodiment of the present application;

[0083] Figure 8 A flowchart of step S36 in the method for preparing a semiconductor structure provided in one embodiment of the present application;

[0084] Figure 9 A schematic cross-sectional view of a structure obtained by forming a fixed material layer, a magnetic tunnel junction material layer, and a free material layer stacked sequentially from bottom to top on an upper surface of a bottom electrode in a method for fabricating a semiconductor structure provided in one embodiment of the present application;

[0085] Figure 10 A schematic cross-sectional view of the structure obtained in step S36 in the method for preparing a semiconductor structure provided in one embodiment of the present application;

[0086] Figures 11 to 12 A schematic cross-sectional view of the structure obtained from step S37 to step S38 in the method for preparing a semiconductor structure provided in one embodiment of the present application; Figure 12 It is also a schematic cross-sectional view of a semiconductor structure provided in one embodiment of the present application;

[0087] Figure 13 This is a schematic cross-sectional view of a semiconductor structure provided in another embodiment of the present application.

[0088] Description of reference numerals:

[0089] 1. Substrate; 2. Transistor; 201. Control terminal; 301. First dielectric layer; 302. First interconnection hole; 303. First interconnection structure; 304. First conductor layer; 305. Second dielectric layer; 306. Second interconnection hole; 307. Second interconnection structure; 308. Third dielectric layer; 309. Fourth dielectric layer; 310. First magnetic storage structure; 3101. Bottom electrode of first magnetic storage structure; 3102. Top electrode of first magnetic storage structure; 311. Second magnetic storage structure; 3111. Bottom electrode of second magnetic storage structure; 3112. Top electrode of second magnetic storage structure; 312. Fifth dielectric layer; 313. Third interconnection hole; 314. Fourth interconnection hole; 315. Third interconnection structure; 316. Fourth interconnect structure; 317, first bit line; 318, second bit line; 319, eighth interconnect hole; 320, eighth interconnect structure; 321, selection line; 322, etch stop layer; 323, filling dielectric layer; 324, fifth interconnect hole; 325, fifth interconnect structure; 326, insulating cover layer; 327, magnetic tunnel junction structure; 3271, fixed material layer; 3272, magnetic tunnel junction material layer; 3273, free material layer; 3274, fixed layer; 3275, magnetic tunnel junction layer; 3276, free layer; 3277, top electrode material layer; 328, second wire layer; 329, sixth interconnect hole; 330, seventh interconnect hole; 331, sixth interconnect structure; 332, seventh interconnect structure; 333, third wire layer. DETAILED DESCRIPTION

[0090] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0091] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0092] It should be understood that when an element or layer is referred to as being "over" or "electrically connected to" another element or layer, it can be directly over or directly electrically connected to the other element or layer, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first magnetic storage structure may be referred to as the second magnetic storage structure, and similarly, the second magnetic storage structure may be referred to as the first magnetic storage structure; the first magnetic storage structure and the second magnetic storage structure are different magnetic storage structures, for example, the first magnetic storage structure may serve as a reference unit and the second magnetic storage structure may serve as a data unit, or the first magnetic storage structure may serve as a data unit and the second magnetic storage structure may serve as a reference unit.

[0093] Spatially relative terms such as "located above..." may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "located above..." will be oriented as being "on" the other elements or features. Therefore, the exemplary term "located above..." may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0094] As used herein, the singular forms "a pair of" and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the term "including" is used in this specification, it can specify the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0095] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. As such, variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes as a result, for example, of manufacturing techniques. The regions shown in the figures are schematic in nature and their shapes are not intended to represent the actual shapes of regions of a device and are not intended to limit the scope of the present invention.

[0096] See also Figure 1 The present application provides a method for preparing a semiconductor structure, which may specifically include the following steps:

[0097] S1: providing a substrate;

[0098] S2: forming a transistor; specifically, the transistor may include a first terminal and a second terminal located in the substrate, and a control terminal located between the first terminal and the second terminal;

[0099] S3: forming a first magnetic storage structure, a second magnetic storage structure, a first bit line, and a second bit line; specifically, the bottom electrode of the first magnetic storage structure is electrically connected to the first end of the transistor, the top electrode of the second magnetic storage structure is electrically connected to the first end of the transistor, the first bit line is electrically connected to the top electrode of the first magnetic storage structure, and the second bit line is electrically connected to the bottom electrode of the second magnetic storage structure, and the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure are located in the same layer;

[0100] S4: forming a selection line electrically connected to the second terminal of the transistor.

[0101] The method for preparing a semiconductor structure provided by the present application forms a complementary structure by forming two magnetic storage structures, wherein the first magnetic storage structure and the second magnetic storage structure can always be configured in a complementary state (for example, the first magnetic storage structure is in a parallel state R P , while the second magnetic storage structure is in the antiparallel state R AP , or vice versa), so that the semiconductor structure prepared thereby does not require an external reference signal, has a fast reading speed, a large reading margin, and high reliability; at the same time, since the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure are located in the same layer, the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure can be formed simultaneously in one step during the preparation process, thereby reducing the number of process steps and lowering the cost.

[0102] For example, when the first magnetic storage structure serves as a reference unit and the second magnetic storage structure serves as a data unit, the data unit, that is, the inverse state of the second magnetic storage structure, can be written to the reference unit, that is, the first magnetic storage structure, and the data bit can be read by comparison with the paired reference unit; in this way, the influence of the tailing bit effect on the read margin can be reduced.

[0103] The following combination Figures 2 to 12 The preparation methods of the semiconductor structures provided in some embodiments of the present application are described in more detail.

[0104] Regarding step S1, the present application does not limit the material of the substrate provided in step S1. For example, the material of the substrate may include but is not limited to sapphire, silicon carbide (SiC), silicon (Si), or gallium nitride (GaN).

[0105] For step S2, the first end and the second end involved in the preparation method of the semiconductor structure provided in the present application may include a drain doping region and a source doping region; at the same time, the conductivity type of the above-mentioned drain doping region and the conductivity type of the source doping region may be the same or different, and the present application does not limit this.

[0106] It can be understood that the transistors involved in this application may include but are not limited to field effect transistors or insulated gate bipolar transistors, etc., and this application does not limit the specific type of transistors.

[0107] For steps S3 and S4, see Figures 2 to 12 In one embodiment, step S3 may specifically include the following steps:

[0108] S31: forming a first dielectric layer 301, wherein the first dielectric layer 301 covers the transistor 2;

[0109] S32: Figure 3 As shown, a first interconnection hole 302 is formed in the first dielectric layer 301; wherein the first interconnection hole 302 exposes the first end of the transistor 2 ( Figure 3 not indicated);

[0110] S33: If Figure 4 As shown, a first interconnect structure 303 is formed in the first interconnect hole 302, and a first wire layer 304 is formed on the upper surface of the first dielectric layer 301. The first wire layer 304 is electrically connected to the first terminal of the transistor 2 via the first interconnect structure 303;

[0111] S34: Figure 6 As shown, a second dielectric layer 305 is formed on the first dielectric layer 301 , and a second interconnection hole 306 is formed in the second dielectric layer 305 , wherein the second interconnection hole 306 exposes the first wire layer 304 ;

[0112] S35: Figure 7 As shown, a second interconnection structure 307 is formed in the second interconnection hole 306;

[0113] S36: Figures 7 to 10 As shown, a third dielectric layer 308, a first magnetic storage structure 310, a second magnetic storage structure 311 and a fourth dielectric layer 309 are formed on the second dielectric layer 305; wherein the bottom electrode 3101 of the first magnetic storage structure 310 is connected to the first wire layer 304 via the second interconnect structure 307;

[0114] S37: Figure 11 As shown, a fifth dielectric layer 312 is formed on the fourth dielectric layer 309, and a third interconnection hole 313 is formed in the fifth dielectric layer 312, and a fourth interconnection hole 314 is formed in the fifth dielectric layer 312 and the fourth dielectric layer 309; wherein the third interconnection hole 313 exposes the top electrode 3102 of the first magnetic storage structure 310, and the fourth interconnection hole 314 exposes the bottom electrode 3111 of the second magnetic storage structure 311;

[0115] S38: Figure 12 As shown, a third interconnect structure 315 is formed in the third interconnect hole 313, a fourth interconnect structure 316 is formed in the fourth interconnect hole 314, and a first bit line 317 and a second bit line 318 are formed on the fifth dielectric layer 312; wherein the first bit line 317 is electrically connected to the top electrode 3102 of the first magnetic storage structure 310 via the third interconnect structure 315, and the second bit line 318 is electrically connected to the bottom electrode 3111 of the second magnetic storage structure 311 via the fourth interconnect structure 316.

[0116] In step S32 and step S33, in one embodiment, the control terminal of transistor 2 is the gate, the first terminal of transistor 2 is the drain, the second terminal of transistor 2 is the source, the selection line 321 is the source line, and the first conductive line layer 304 is the drain line; based on the above embodiment, Figure 3 As shown, in step S32, while forming the first interconnection hole 302 in the first dielectric layer 301, an eighth interconnection hole 319 is also formed in the first dielectric layer 301. The eighth interconnection hole 319 exposes the second terminal ( Figure 3 Based on the above steps, if Figure 4As shown, in step S33, while the first interconnect structure 303 is formed in the first interconnect hole 302, the eighth interconnect structure 320 is also formed in the eighth interconnect hole 319; while the first wire layer 304 is formed on the upper surface of the first dielectric layer 301, a source line is also formed on the upper surface of the first dielectric layer 301. The source line is electrically connected to the second end of the transistor 2 via the eighth interconnect structure 320, and a gap is formed between the source line and the first wire layer 304.

[0117] The method for preparing the semiconductor structure provided in the above embodiment forms the eighth interconnect hole while forming the first interconnect hole, and forms the eighth interconnect structure while forming the first interconnect structure. The eighth interconnect structure can serve as a source contact structure to electrically connect the source line to the second end of the transistor. In this way, during the preparation process, the first interconnect hole and the eighth interconnect hole can be formed simultaneously in one process, and the first interconnect structure and the eighth interconnect structure can also be formed simultaneously in one process, further reducing the number of process steps and lowering costs.

[0118] In one embodiment, see Figure 5 After the step of forming the first conductive line layer 304 and the source line, and before forming the second dielectric layer 305 in step S34, a step of forming an etch stop layer 322 may be further included; specifically, after the step of forming the first conductive line layer 304 and the source line, and before forming the second dielectric layer 305 in step S34, an etch stop layer 322 may be further formed on the source line, the first conductive line layer 304, and the exposed first dielectric layer 301.

[0119] The present application does not limit the specific material of the etch stop layer 322. The material of the etch stop layer 322 may include but is not limited to silicon, silicon carbide, silicon nitride (SiN) or silicon oxynitride (SiON), etc. In one embodiment, the material of the etch stop layer 322 includes silicon nitride.

[0120] More specifically, in one embodiment, please refer to Figure 5 After the step of forming the etch stop layer 322 and before forming the second dielectric layer 305 in step S34, a filling dielectric layer 323 can be formed on the upper surface of the etch stop layer 322 between the source line and the first conductive layer 304. The filling dielectric layer 323 fills the gap between the source line and the first conductive layer 304.

[0121] The present application does not limit the specific methods for forming the first dielectric layer 301, forming the second dielectric layer 305, forming the third dielectric layer 308 and the fourth dielectric layer 309 stacked in sequence, forming the fifth dielectric layer 312 and forming the filling dielectric layer 323. The first dielectric layer 301, the second dielectric layer 305, the third dielectric layer, the fourth dielectric layer 309, the fifth dielectric layer 312 and the filling dielectric layer 323 can all be formed by, but not limited to, chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), radical-enhanced chemical vapor deposition (RECVD), atomic layer deposition (ALD), and the like. Deposition, ALD) and other deposition methods are used to form it.

[0122] The present application does not limit the specific materials of the first dielectric layer 301, the second dielectric layer 305, the third dielectric layer, the fourth dielectric layer 309, the fifth dielectric layer 312, and the filling dielectric layer 323. The first dielectric layer 301, the second dielectric layer 305, the third dielectric layer, the fourth dielectric layer 309, the fifth dielectric layer 312, and the filling dielectric layer 323 may include, but are not limited to, silicon, silicon nitride, silicon oxide (SiO2), or silicon nitride (SiN), etc. In one embodiment, the first dielectric layer 301, the second dielectric layer 305, the third dielectric layer, the fourth dielectric layer 309, the fifth dielectric layer 312, and the filling dielectric layer 323 all include silicon nitride.

[0123] For steps S34 and S35, please refer to Figures 6 and 7 In one embodiment, as Figure 6 As shown, in step S34, while forming the second interconnection hole 306 in the second dielectric layer 305, a fifth interconnection hole 324 is also formed in the second dielectric layer 305; based on the above steps, as shown in FIG. Figure 7 As shown, in step S35 , while the second interconnection structure 307 is formed in the second interconnection hole 306 , the fifth interconnection structure 325 is also formed in the fifth interconnection hole 324 .

[0124] The method for preparing the semiconductor structure provided in the above embodiment forms the fifth interconnect hole while forming the second interconnect hole, and forms the fifth interconnect structure while forming the second interconnect structure. In this way, during the preparation process, the second interconnect hole and the fifth interconnect hole can be formed simultaneously in one step, and the second interconnect structure and the fifth interconnect structure can be formed simultaneously in one step, further reducing the process steps and lowering the cost.

[0125] For step S36, please combine Figure 8 See Figures 7 to 10 In one embodiment, step S36 may specifically include the following steps:

[0126] S361: If Figure 7 As shown, a pair of bottom electrodes arranged at intervals are formed on the second dielectric layer 305 , serving as the bottom electrode 3101 of the first magnetic storage structure 310 and the bottom electrode 3111 of the second magnetic storage structure 311 respectively;

[0127] S362: If Figure 7 As shown, a third dielectric layer 308 is formed on the second dielectric layer 305 , and the bottom electrode 3101 of the first magnetic storage structure 310 and the bottom electrode 3111 of the second magnetic storage structure 311 are both located in the third dielectric layer 308 ;

[0128] S363: If Figure 9 and Figure 10 As shown, a magnetic tunnel junction structure 327 and a top electrode are formed on the bottom electrode;

[0129] S364: If Figure 10 As shown, a fourth dielectric layer 309 is formed on the third dielectric layer 308 , and the fourth dielectric layer 309 covers the bottom electrode.

[0130] It should be noted that step S363 may specifically include: forming a magnetic tunnel junction structure 327 in the first magnetic storage structure and a top electrode 3102 of the first magnetic storage structure 310 on the bottom electrode 3101 of the first magnetic storage structure 310, and forming a magnetic tunnel junction structure 327 in the second magnetic storage structure and a top electrode 3112 of the second magnetic storage structure 311 on the bottom electrode 3111 of the second magnetic storage structure 311.

[0131] Please continue reading Figure 7Based on the fifth interconnect structure 325 formed in the fifth interconnect hole 324, in one embodiment, in step S361, while forming a pair of spaced-apart bottom electrodes on the second dielectric layer 305, a second conductive layer 328 is also formed between the bottom electrodes. The second conductive layer 328 is connected to the first conductive layer 304 via the fifth interconnect structure 325, with a gap between the second conductive layer 328 and the bottom electrodes. The third dielectric layer 308 fills the gap between the second conductive layer 328 and the bottom electrodes.

[0132] The second conductive layer formed by the method for preparing the semiconductor structure provided in the above embodiment is located on the same layer as the bottom electrode of the first magnetic storage structure, so that during the process of preparing the above semiconductor structure, the second conductive layer and the bottom electrode of the first magnetic storage structure can be formed simultaneously in one step, further reducing the process steps and lowering the cost.

[0133] See also Figures 9 and 10 In one embodiment, the magnetic tunnel junction structure 327 may include but is not limited to a fixed layer 3271 , a magnetic tunnel junction layer 3272 and a free layer 3273 stacked sequentially from bottom to top.

[0134] Based on the above embodiment, step S364 may specifically include the following steps:

[0135] like Figure 9 As shown, a fixed material layer 3271, a magnetic tunnel junction material layer 3272, a free material layer 3273 and a top electrode material layer 3277 are formed on the upper surface of the bottom electrode in sequence from bottom to top;

[0136] like Figure 10 As shown, the fixed material layer 3271, the magnetic tunnel junction material layer 3272, the free material layer 3273 and the top electrode material layer 3277 stacked sequentially from bottom to top are patterned to obtain the fixed layer 3274, the magnetic tunnel junction layer 3275, the free layer 3276 and the top electrode stacked sequentially from bottom to top.

[0137] The present application does not limit the specific materials of the fixed material layer 3271 and the fixed layer 3274. The fixed material layer 3271 and the fixed layer 3274 may include but are not limited to a cobalt iron boron (CoFeB) layer, a tantalum (Ta) layer, a cobalt / platinum stacked layer structure ([Co(x) / Pt(y)] n), any one or any combination of the above-mentioned layers, such as a ruthenium (Ru) layer or an iridium (Ir) layer, etc.; the present application does not limit the specific materials of the magnetic tunnel junction material layer 3272 and the magnetic tunnel junction layer 3275. In one embodiment, the magnetic tunnel junction material layer 3272 and the magnetic tunnel junction layer 3275 both include a cobalt iron boron layer; the present application does not limit the specific materials of the free material layer 3273 and the free layer 3276. In one embodiment, the free material layer 3273 and the free layer 3276 both include magnesium oxide (MgO).

[0138] In one embodiment, Figure 10 As shown, after the step S363 of forming the magnetic tunnel junction structure 327 and the top electrode on the bottom electrode, and before the step S364 of forming the fourth dielectric layer 309 on the third dielectric layer 308 and the fourth dielectric layer 309 covering the bottom electrode, the step of forming an insulating covering layer 326 on the magnetic tunnel junction structure 327 and the top electrode may also be included.

[0139] For steps S37 and S38, see Figures 11 to 12 In one embodiment, as Figure 11 As shown, in step S37, while forming the fourth interconnection hole 314 in the fifth dielectric layer 312 and the fourth dielectric layer 309, a sixth interconnection hole 329 is also formed in the fifth dielectric layer 312 and the fourth dielectric layer 309, and a seventh interconnection hole 330 is formed in the fifth dielectric layer 312; wherein the sixth interconnection hole 329 exposes the second metal line layer, and the seventh interconnection hole 330 exposes the top electrode 3112 of the second magnetic storage structure 311; based on the above steps, as Figure 12 As shown, in step S38, while forming the third interconnect structure 315 in the third interconnect hole 313 and the fourth interconnect structure 316 in the fourth interconnect hole 314, a sixth interconnect structure 331 is also formed in the sixth interconnect hole 329, and a seventh interconnect structure 332 is also formed in the seventh interconnect hole 330. While forming the first bit line 317 and the second bit line 318 on the fifth dielectric layer 312, a third conductive layer 333 is also formed on the fifth dielectric layer 312. The third conductive layer 333 is connected to the second conductive layer 328 via the sixth interconnect structure 331, and is connected to the top electrode 3112 of the second magnetic storage structure 311 via the seventh interconnect structure 332.

[0140] The method for preparing the semiconductor structure provided in the above embodiment forms the sixth interconnect hole and the seventh interconnect hole at the same time as the fourth interconnect hole is formed, and forms the sixth interconnect structure and the seventh interconnect structure at the same time as the fourth interconnect structure is formed. In this way, during the preparation process, the fourth interconnect hole, the sixth interconnect hole and the seventh interconnect hole can be formed simultaneously in one step, and the fourth interconnect structure, the sixth interconnect structure and the seventh interconnect structure can be formed simultaneously in one step, further reducing the process steps and lowering the cost.

[0141] At the same time, the third wire layer formed by the preparation method of the semiconductor structure provided in the above embodiment is located in the same layer as the first bit line and the second bit line, so that in the process of preparing the above semiconductor structure, the third wire layer, the first bit line and the second bit line can be formed simultaneously in one step, further reducing the process steps and reducing costs.

[0142] In one embodiment, while forming the first interconnect hole 302 and the eighth interconnect hole 319 in the first dielectric layer 301, a ninth lead hole is also formed in the first dielectric layer 301, exposing the control terminal of the transistor 2. Based on the above steps, while forming the first interconnect structure 303 in the first interconnect hole 302 and the eighth interconnect structure 320 in the eighth interconnect hole 319, a ninth interconnect structure is also formed in the ninth interconnect hole. Based on the above steps, while forming the first conductive line layer 304 and the source line on the upper surface of the first dielectric layer 301, a word line is also formed on the upper surface of the first dielectric layer 301 to connect to the control terminal of the transistor 2.

[0143] The present application does not limit the specific method of forming the first interconnection hole 302, the second interconnection hole 306, the third interconnection hole 313, the fourth interconnection hole 314, the fifth interconnection hole 324, the sixth interconnection hole 329, the seventh interconnection hole 330, the eighth interconnection hole 319 and the ninth interconnection hole. The first interconnection hole 302, the second interconnection hole 306, the third interconnection hole 313, the fourth interconnection hole 314, the fifth interconnection hole 324, the sixth interconnection hole 329, the seventh interconnection hole 330, the eighth interconnection hole 319 and the ninth interconnection hole can be formed by, but not limited to, the following methods:

[0144] A photoresist is coated on the surface of the obtained structure, and the photoresist is exposed and developed to remove excess portions of the photoresist to form an interconnection hole pattern. According to the interconnection hole pattern, the obtained structure is etched using, but not limited to, a dry etching method to form a first interconnection hole 302, a second interconnection hole 306, a third interconnection hole 313, a fourth interconnection hole 314, a fifth interconnection hole 324, a sixth interconnection hole 329, a seventh interconnection hole 330, an eighth interconnection hole 319, and a ninth interconnection hole.

[0145] The present application does not limit the specific materials of the first interconnect structure 303, the second interconnect structure 307, the third interconnect structure 315, the fourth interconnect structure 316, the fifth interconnect structure 325, the sixth interconnect structure 331, the seventh interconnect structure 332, the eighth interconnect structure 320, the ninth interconnect structure, and the first conductive layer 304, the second conductive layer 328, and the third conductive layer 333. These interconnect structures and conductive layers may include, but are not limited to, metal materials such as copper or tungsten. In one embodiment, the first interconnect structure 303, the second interconnect structure 307, the third interconnect structure 315, the fourth interconnect structure 316, the fifth interconnect structure 325, the sixth interconnect structure 331, the seventh interconnect structure 332, the eighth interconnect structure 320, the ninth interconnect structure, and the first conductive layer 304, the second conductive layer 328, and the third conductive layer 333 all include tungsten. Tungsten can uniformly fill high aspect ratio through-holes and has a high melting point, high hardness, excellent corrosion resistance, and good electrical and thermal conductivity.

[0146] It should be noted that the method for preparing the semiconductor structure provided in this application does not limit the form of the control terminal 201 of the transistor 2 and the selection line 321 electrically connected to the second terminal of the transistor 2. In some possible embodiments, for example Figure 13 As shown, the control terminal 201 of the transistor 2 can be buried in the substrate 1. The steps of forming the transistor 2 with the control terminal 201 buried in the substrate 1 are described in more detail below.

[0147] In the process of forming the transistor 2 in step S2 of one embodiment, the transistor 2 may include a first end and a second end located in the substrate 1, and a control end 201 located between the first end and the second end; based on the above embodiment, the following method can be adopted but is not limited to, and the formation of the transistor 2 may include: forming a first trench (not shown) in the substrate 1; forming the control end 201 in the first trench; and forming the first end and the second end in the substrate 1.

[0148] Furthermore, based on the above steps, the selection line 321 electrically connected to the second terminal of the transistor 2 may be formed in the following manner, but not limited to:

[0149] A second trench (not shown) is formed in the second end of the transistor 2 ; a selection line 321 is formed in the second trench.

[0150] It can be understood that the selection line 321 involved in the above embodiment may include a source line.

[0151] It can be understood that the transistor involved in the present application is located at the first end and the second end of the substrate, and may include a drain doping region and a source doping region located in the substrate.

[0152] It should be understood that although Figure 1、 Figure 2 and Figure 8 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 、 Figure 2 and Figure 8 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0153] Please continue reading Figure 12 According to some embodiments, the present application also provides a semiconductor structure, which may include a substrate ( Figure 12 ), transistor 2, a first magnetic storage structure 310, a second magnetic storage structure 311, a first bit line 317, a second bit line 318 and a selection line 321.

[0154] Specifically, transistor 2 includes a control end, a first end and a second end; wherein the first end and the second end are located in the substrate, and the control end is located between the first end and the second end; the bottom electrode 3101 of the first magnetic storage structure 310 is electrically connected to the first end of transistor 2; the top electrode 3112 of the second magnetic storage structure 311 is electrically connected to the first end of transistor 2, and the bottom electrode 3101 of the first magnetic storage structure 310 and the bottom electrode 3112 of the second magnetic storage structure 311 are located in the same layer; the first bit line 317 is electrically connected to the top electrode 3101 of the first magnetic storage structure 310; the second bit line 318 is electrically connected to the bottom electrode 3111 of the second magnetic storage structure 311; and the selection line 321 is electrically connected to the second end of transistor 2.

[0155] The semiconductor structure provided by the present application forms a complementary structure by two magnetic storage structures, wherein the first magnetic storage structure and the second magnetic storage structure can always be configured in a complementary state (for example, the first magnetic storage structure is in a parallel state R P , while the second magnetic storage structure is in the antiparallel state R AP , or vice versa), so that it does not require an external reference signal, has a fast reading speed, a large reading margin, and high reliability; at the same time, since the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure are located in the same layer, the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure can be formed simultaneously in one step during the preparation of the semiconductor structure, thereby reducing the number of process steps and lowering costs.

[0156] For example, when the first magnetic storage structure serves as a reference unit and the second magnetic storage structure serves as a data unit, the data unit, that is, the inverse state of the second magnetic storage structure, can be written to the reference unit, that is, the first magnetic storage structure, and the data bit can be read by comparison with the paired reference unit; in this way, the influence of the tailing bit effect on the read margin can be reduced.

[0157] In one embodiment, the control terminal is located above the substrate between the first terminal and the second terminal; based on the above embodiment, Figure 12 As shown, the selection line 321 may be located above the second end; further, based on the above embodiment, the height of the selection line 321 may be flush with the height of the control end.

[0158] Please continue reading Figure 12 In one embodiment, the semiconductor structure may further include a first conductive line layer 304 , a second conductive line layer 328 , and a third conductive line layer 333 .

[0159] Specifically, the first wire layer 304 is located on the substrate and is connected to the first end of the transistor 2 via the first interconnect structure 303; the bottom electrode 3101 of the first magnetic storage structure 310 is connected to the first wire layer 304 via the second interconnect structure 307, and the top electrode 3102 of the first magnetic storage structure 310 is connected to the first bit line 317 via the third interconnect structure 315; the second bit line 318 is connected to the bottom electrode 3111 of the second magnetic storage structure 311 via the fourth interconnect structure 316; the second wire layer 328 is located on the first wire layer 304 and is connected to the first wire layer 304 via the fifth interconnect structure 325; the third wire layer 333 is located on the second wire layer 328, is connected to the second wire layer 328 via the sixth interconnect structure 331, and is connected to the top electrode 3112 of the second magnetic storage structure 311 via the seventh interconnect structure 332.

[0160] Please continue reading Figure 12 In one embodiment, the second conductive layer 328 and the bottom electrode 3101 of the first magnetic storage structure 310 are located in the same layer; the third conductive layer 333 and the first bit line 317 and the second bit line 318 are all located in the same layer.

[0161] In the semiconductor structure provided in the above embodiment, the second conductive layer and the bottom electrode of the first magnetic storage structure 310 are located on the same layer, and the third conductive layer and the first bit line and the second bit line are all located on the same layer. Therefore, during the preparation of the above semiconductor structure, the second conductive layer and the bottom electrode of the first magnetic storage structure 310 can be formed simultaneously in one step, and the third conductive layer, the first bit line and the second bit line can also be formed simultaneously in one step, thereby further reducing the number of process steps and lowering costs.

[0162] Please continue reading Figure 12 In one embodiment, the control terminal of transistor 2 is a gate, the first terminal of transistor 2 is a drain, the second terminal of transistor 2 is a source, the selection line 321 is a source line, and the first conductive line layer 304 is a drain line; based on the above embodiment, the source line and the first conductive line layer 304 are located in the same layer, and there is a gap between the source line and the first conductive line layer 304; the source line is electrically connected to the second terminal of transistor 2 via the eighth interconnect structure 320.

[0163] In the semiconductor structure provided in the above embodiment, the source line and the first conductive line layer are located in the same layer, so that the source line and the first conductive line layer can be formed simultaneously in one step during the preparation of the semiconductor structure, further reducing the number of process steps and lowering costs.

[0164] Please continue reading Figure 12 In one embodiment, the first magnetic storage structure 310 and the second magnetic storage structure 311 each include a bottom electrode, a magnetic tunnel junction structure 327 and a top electrode stacked sequentially from bottom to top.

[0165] Specifically, the magnetic tunnel junction structure 327 may include a fixed layer 3274, a magnetic tunnel junction layer 3275 and a free layer 3276 stacked in sequence from bottom to top, and the fixed layer 3274, the magnetic tunnel junction layer 3275 and the free layer 3276 of the first magnetic storage structure 310 and the second magnetic storage structure 311 are respectively located on the same layer.

[0166] It can be understood that the bottom electrode involved in the present application may include the bottom electrode 3101 of the first magnetic storage structure 310 and the bottom electrode 3111 of the second magnetic storage structure 311; the top electrode involved in the present application may include the top electrode 3102 of the first magnetic storage structure 310 and the top electrode 3112 of the second magnetic storage structure 311.

[0167] It should be noted that the semiconductor structure provided in this application does not limit the form of the control terminal of the transistor 2 and the selection line 321 electrically connected to the second terminal of the transistor 2. In some possible embodiments, such as Figure 13 As shown, the control terminal 201 of the transistor 2 may be buried in the substrate 1 . The structure of the transistor 2 with the control terminal 201 buried in the substrate 1 will be described in more detail below.

[0168] See also Figure 13 In one embodiment, the control terminal 201 is located in the substrate 1 between the first terminal and the second terminal; based on the above embodiment, the selection line 321 is located in the second terminal.

[0169] It should be noted that the present application does not limit the positional relationship between the bottom of the selection line 321 and the bottom of the control terminal 201; in one embodiment, the bottom of the selection line 321 can be flush with the bottom of the control terminal 201; in another possible embodiment, the bottom of the selection line 321 can also be higher than the bottom of the control terminal 201.

[0170] In one embodiment, the height of the selection line 321 is the same as the height of the control terminal 201 .

[0171] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0172] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a transistor comprising a control terminal, a first terminal, and a second terminal; the first terminal and the second terminal are located in the substrate, and the control terminal is located between the first terminal and the second terminal; a first magnetic storage structure, wherein a bottom electrode of the first magnetic storage structure is electrically connected to the first terminal of the transistor; a second magnetic storage structure, wherein a top electrode of the second magnetic storage structure is electrically connected to the first end of the transistor, and a bottom electrode of the first magnetic storage structure and a bottom electrode of the second magnetic storage structure are located in the same layer; a first bit line electrically connected to a top electrode of the first magnetic storage structure; a second bit line electrically connected to the bottom electrode of the second magnetic storage structure; The selection line is electrically connected to the second terminal of the transistor.

2. The semiconductor structure according to claim 1, wherein: The control terminal is located in the substrate between the first terminal and the second terminal, and the selection line is located in the second terminal.

3. The semiconductor structure according to claim 2, wherein: The bottom of the selection line is flush with the bottom of the control terminal.

4. The semiconductor structure according to claim 3, wherein: The height of the selection line is the same as that of the control terminal.

5. The semiconductor structure according to claim 1, wherein: The control end is located above the substrate between the first end and the second end; The selection line is located above the second end, and a height of the selection line is flush with a height of the control end. The semiconductor structure according to claim 1 , wherein: Also includes: a first conductive line layer, located on the substrate and connected to the first terminal of the transistor via a first interconnect structure; The bottom electrode of the first magnetic storage structure is connected to the first conductive line layer via a second interconnect structure, and the top electrode of the first magnetic storage structure is connected to the first bit line via a third interconnect structure; The second bit line is connected to the bottom electrode of the second magnetic storage structure via a fourth interconnect structure; a second conductive line layer, located on the first conductive line layer and connected to the first conductive line layer via a fifth interconnect structure; The third conductive line layer is located on the second conductive line layer, is connected to the second conductive line layer via a sixth interconnect structure, and is connected to the top electrode of the second magnetic storage structure via a seventh interconnect structure.

7. The semiconductor structure according to claim 6, wherein: The second conductive line layer and the bottom electrode of the first magnetic storage structure are located in the same layer; the third conductive line layer and the first bit line and the second bit line are located in the same layer.

8. The semiconductor structure according to claim 6, wherein: The control terminal of the transistor is a gate, the first terminal of the transistor is a drain, the second terminal of the transistor is a source, and the selection line is a source line; The source line is located in the same layer as the first conductive line layer, and there is a gap between the source line and the first conductive line layer; the source line is electrically connected to the second end of the transistor via an eighth interconnect structure.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that The first magnetic storage structure and the second magnetic storage structure each include: the bottom electrode, the magnetic tunnel junction structure and the top electrode stacked sequentially from bottom to top; wherein The magnetic tunnel junction structure includes: a fixed layer, a magnetic tunnel junction layer and a free layer stacked sequentially from bottom to top, and the fixed layer, magnetic tunnel junction layer and free layer of the first magnetic storage structure and the second magnetic storage structure are respectively located in the same layer.

10. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a transistor, the transistor comprising a first terminal and a second terminal located in the substrate, and a control terminal located between the first terminal and the second terminal; forming a first magnetic storage structure, a second magnetic storage structure, a first bit line, and a second bit line; wherein the bottom electrode of the first magnetic storage structure is electrically connected to the first terminal of the transistor, the top electrode of the second magnetic storage structure is electrically connected to the first terminal of the transistor, the first bit line is electrically connected to the top electrode of the first magnetic storage structure, the second bit line is electrically connected to the bottom electrode of the second magnetic storage structure, and the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure are located on the same layer; A selection line is formed that is electrically connected to the second terminal of the transistor.

11. The method for preparing a semiconductor structure according to claim 10, wherein: The forming of the transistor comprises: forming a first trench in the substrate; forming the control terminal in the first trench; forming the first end and the second end in the substrate; The forming of a selection line electrically connected to the second terminal of the transistor comprises: forming a second groove in the second end; The selection line is formed in the second trench.

12. The method for preparing a semiconductor structure according to claim 10, wherein: The forming of the first magnetic storage structure, the second magnetic storage structure, the first bit line and the second bit line includes: forming a first dielectric layer, wherein the first dielectric layer covers the transistor; forming a first interconnection hole in the first dielectric layer, wherein the first interconnection hole exposes the first end of the transistor; forming a first interconnect structure in the first interconnect hole, and forming a first conductive line layer on the upper surface of the first dielectric layer, wherein the first conductive line layer is electrically connected to the first terminal of the transistor via the first interconnect structure; forming a second dielectric layer on the first dielectric layer, and forming a second interconnection hole in the second dielectric layer, wherein the second interconnection hole exposes the first conductive line layer; forming a second interconnection structure in the second interconnection hole; forming a third dielectric layer, a first magnetic storage structure, a second magnetic storage structure, and a fourth dielectric layer on the second dielectric layer; wherein the bottom electrode of the first magnetic storage structure is connected to the first conductive line layer via a second interconnect structure; forming a fifth dielectric layer on the fourth dielectric layer, forming a third interconnection hole in the fifth dielectric layer, and forming a fourth interconnection hole in the fifth dielectric layer and the fourth dielectric layer, wherein the third interconnection hole exposes the top electrode of the first magnetic storage structure, and the fourth interconnection hole exposes the bottom electrode of the second magnetic storage structure; A third interconnect structure is formed in the third interconnect hole, a fourth interconnect structure is formed in the fourth interconnect hole, and the first bit line and the second bit line are formed on the fifth dielectric layer, the first bit line is electrically connected to the top electrode of the first magnetic storage structure via the third interconnect structure, and the second bit line is electrically connected to the bottom electrode of the second magnetic storage structure via the fourth interconnect structure.

13. The method for preparing a semiconductor structure according to claim 12, wherein: The method of forming a third dielectric layer, a first magnetic storage structure, a second magnetic storage structure, and a fourth dielectric layer on the second dielectric layer includes: forming a pair of bottom electrodes spaced apart from each other on the second dielectric layer, serving as the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure respectively; forming a third dielectric layer on the second dielectric layer, wherein the bottom electrode of the first magnetic storage structure and the bottom electrode of the second magnetic storage structure are both located in the third dielectric layer; forming a magnetic tunnel junction structure and a top electrode on the bottom electrode; A fourth dielectric layer is formed on the third dielectric layer, wherein the fourth dielectric layer covers the bottom electrode.

14. The method for preparing a semiconductor structure according to claim 13, wherein: The magnetic tunnel junction structure comprises: a fixed layer, a magnetic tunnel junction layer and a free layer stacked sequentially from bottom to top; The forming of a magnetic tunnel junction structure and a top electrode on the bottom electrode comprises: forming a fixed material layer, a magnetic tunnel junction material layer, a free material layer and a top electrode material layer stacked sequentially from bottom to top on the upper surface of the bottom electrode; The fixed material layer, magnetic tunnel junction material layer, free material layer and top electrode material layer stacked sequentially from bottom to top are patterned to obtain the fixed layer, magnetic tunnel junction layer, free layer and top electrode stacked sequentially from bottom to top.

15. The method for preparing a semiconductor structure according to claim 13, wherein: while forming the second interconnection hole in the second dielectric layer, also forming a fifth interconnection hole in the second dielectric layer; while forming the second interconnection structure in the second interconnection hole, also forming a fifth interconnection structure in the fifth interconnection hole; A pair of spaced-apart bottom electrodes are formed on the second dielectric layer, and a second conductive layer is formed between the bottom electrodes. The second conductive layer is connected to the first conductive layer via the fifth interconnect structure, and a gap is formed between the second conductive layer and the bottom electrodes. The third dielectric layer fills the gap between the second conductive layer and the bottom electrodes. While forming a fourth interconnect hole in the fifth dielectric layer and the fourth dielectric layer, a sixth interconnect hole is also formed in the fifth dielectric layer and the fourth dielectric layer, and a seventh interconnect hole is also formed in the fifth dielectric layer. The sixth interconnect hole exposes the second conductive layer, and the seventh interconnect hole exposes the top electrode of the second magnetic storage structure. While forming a third interconnect structure in the third interconnect hole and a fourth interconnect structure in the fourth interconnect hole, a sixth interconnect structure is also formed in the sixth interconnect hole, and a seventh interconnect structure is also formed in the seventh interconnect hole. While forming the first bit line and the second bit line on the fifth dielectric layer, a third conductive layer is also formed on the fifth dielectric layer. The third conductive layer is connected to the second conductive layer via the sixth interconnect structure, and is connected to the top electrode of the second magnetic storage structure via the seventh interconnect structure.

16. The method for preparing a semiconductor structure according to claim 15, wherein: The control terminal of the transistor is a gate, the first terminal of the transistor is a drain, the second terminal of the transistor is a source, and the selection line is a source line; while forming the first interconnection hole in the first dielectric layer, also forming an eighth interconnection hole in the first dielectric layer, wherein the eighth interconnection hole exposes the second end of the transistor; forming an eighth interconnection structure in the eighth interconnection hole while forming a first interconnection structure in the first interconnection hole; While forming a first conductive line layer on the upper surface of the first dielectric layer, a source line is also formed on the upper surface of the first dielectric layer. The source line is electrically connected to the second end of the transistor via the eighth interconnect structure, and a gap is formed between the source line and the first conductive line layer.

17. The method for preparing a semiconductor structure according to claim 16, wherein: After forming the source line and the first conductive line layer and before forming the second dielectric layer, the method further includes: An etch stop layer is formed on the source line, the first conductive line layer and the exposed first dielectric layer.

18. The method for preparing a semiconductor structure according to claim 17, wherein: After forming the etch stop layer and before forming the second dielectric layer, the method further includes: A filling dielectric layer is formed on the upper surface of the etch stop layer between the source line and the first conductive line layer, and the filling dielectric layer fills the gap between the source line and the first conductive line layer.

19. The method for preparing a semiconductor structure according to claim 17, wherein: While forming the first interconnection hole and the eighth interconnection hole in the first dielectric layer, a ninth interconnection hole is also formed in the first dielectric layer, wherein the ninth interconnection hole exposes the control terminal of the transistor; forming a first interconnection structure in the first interconnection hole, forming an eighth interconnection structure in the eighth interconnection hole, and forming a ninth interconnection structure in the ninth interconnection hole; A first conductive line layer and the source line are formed on the upper surface of the first dielectric layer, and a word line is also formed on the upper surface of the first dielectric layer to connect to the control terminal of the transistor.

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