A temperature-approximation-independent current reference circuit

Abstract

The application belongs to the technical field of integrated circuits, and discloses a temperature-approximate-independent current reference circuit, which comprises a starting module, a reference current generating module and an output current generating module. The input end of the reference current generating module is connected with the starting module, and a feedback signal is applied to the starting circuit module. The input end of the output current generating module is connected with the output end of the reference current generating module. On the basis of the reference current output, the reference current can be amplified or reduced by one or several groups of current mirrors, so as to obtain one or several groups of temperature-approximate-independent output currents. The application can work in a wide voltage range and output a temperature-approximate-independent current.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and in particular relates to a current reference circuit that is approximately independent of temperature. Background Technology

[0002] The reference source is the core module of the analog system. It is widely used as the reference source for ADCs (analog-to-digital converters) or LDOs (low dropout linear regulators). Its temperature coefficient, power consumption, operating voltage range and other parameters are critical to its design and play an important role in the entire chip system.

[0003] Ideally, the reference current or voltage should not change with temperature, voltage, or process variations. However, the bandgap reference voltage is obtained by adding a voltage with a positive temperature coefficient and a voltage with a negative temperature coefficient. The positive temperature coefficient voltage is linear, while the negative temperature coefficient voltage has higher-order temperature coefficients. Therefore, a typical reference voltage is parabolic in form.

[0004] Therefore, how to address the impact of high-order temperature coefficients on reference voltage and current is a major technical problem that urgently needs to be solved in this field. If a resistor with a temperature coefficient similar to that of voltage is selected, a reference current that is approximately independent of temperature can be generated. Summary of the Invention

[0005] To address the problems existing in the prior art, the present invention provides a current reference circuit that is approximately independent of temperature.

[0006] The present invention is implemented as follows: a current reference circuit that is approximately independent of temperature, the circuit including a startup circuit module, a reference current generation module, and an output current generation module.

[0007] The startup circuit module is used to power on the circuit, enabling the current reference circuit to enter normal working state.

[0008] The reference current generating module is connected to the startup circuit module and is used to generate a reference current that is approximately independent of temperature.

[0009] The output current generating module is connected to the reference current generating module to generate one or more sets of required output currents.

[0010] Furthermore, the startup circuit module includes:

[0011] The first PMOS transistor has its gate connected to the gate of the first NMOS transistor and one end of the first resistor, its source connected to the power supply, and its drain connected to the drain of the first NMOS transistor, the gate of the second NMOS transistor, the gate of the second PMOS transistor, the gate of the tenth PMOS transistor, and the gate of the eleventh PMOS transistor.

[0012] The first NMOS transistor has its source connected to ground.

[0013] The source of the second PMOS transistor is connected to the power supply, and its drain is connected to the drain of the second NMOS transistor and the gate of the third PMOS transistor.

[0014] The source of the second NMOS transistor is connected to ground.

[0015] The source of the third PMOS transistor is connected to the power supply, and its drain is connected to the source of the fourth PMOS transistor.

[0016] The fourth PMOS transistor has its gate and drain connected to the source of the fifth PMOS transistor.

[0017] The fifth PMOS transistor has its gate and drain connected to the drain of the third NMOS transistor, the drain of the fourth NMOS transistor, the gate of the fifth NMOS transistor, and the gate of the sixth NMOS transistor.

[0018] The third NMOS transistor has its source connected to ground, and its gate connected to the gate of the third PMOS transistor, the drain of the second NMOS transistor, the drain of the second PMOS transistor, the gate of the tenth NMOS transistor, the gate of the eleventh NMOS transistor, the gate of the sixteenth NMOS transistor, and the gate of the nineteenth NMOS transistor.

[0019] The fourth NMOS transistor has its source connected to ground, and its gate connected to the drain of the sixteenth PMOS transistor MP16, the drain and gate of the fourteenth NMOS transistor, the gate of the fifteenth NMOS transistor, the drain of the sixteenth NMOS transistor, the gate of the seventeenth NMOS transistor, the gate of the twentieth NMOS transistor, the gate of the twenty-second NMOS transistor, the gate of the twenty-fourth NMOS transistor, and the gate of the twenty-sixth NMOS transistor.

[0020] The sixth PMOS transistor has its source connected to the power supply, its drain connected to the source of the seventh PMOS transistor, and its gate connected to the gate and drain of the seventh PMOS transistor, the drain of the fifth NMOS transistor, the drain of the eighth NMOS transistor, the gate of the ninth PMOS transistor, the drain of the tenth PMOS transistor, the gate of the fifteenth PMOS transistor, the gate of the sixteenth PMOS transistor, and the gate of the seventeenth PMOS transistor.

[0021] The eighth PMOS transistor has its source connected to the power supply, its drain connected to the source of the ninth PMOS transistor, and its gate connected to the drain of the ninth PMOS transistor, the gate of the twelfth PMOS transistor, the gate of the thirteenth PMOS transistor, the gate of the fourteenth PMOS transistor, the drain of the eleventh PMOS transistor, the drain of the sixth NMOS transistor, and the drain of the seventh NMOS transistor.

[0022] The fifth NMOS transistor has its source connected to ground.

[0023] The sixth NMOS transistor has its source connected to ground.

[0024] The second NMOS transistor has its source connected to its gate, drain, and the other end of the first resistor.

[0025] Furthermore, the reference current generation module includes:

[0026] The seventh NMOS transistor has its gate connected to the gate of the twelfth NMOS transistor, the drain of the tenth NMOS transistor, and the drain of the fifteenth PMOS transistor. It is also connected to the drain of the twelfth NMOS transistor through a third resistor. Its source is connected to the drain of the ninth NMOS transistor.

[0027] The eighth NMOS transistor has its gate connected to the gate of the ninth NMOS transistor, the gate of the thirteenth NMOS transistor, the drain of the twelfth NMOS transistor, and the drain of the eleventh NMOS transistor, and its source is connected to the emitter of the first transistor.

[0028] The source of the ninth NMOS transistor is connected to the emitter of the second transistor through the second resistor.

[0029] The tenth NMOS transistor has its source connected to ground.

[0030] The eleventh NMOS transistor has its source connected to ground.

[0031] The tenth PMOS transistor has its source connected to the power supply.

[0032] The eleventh PMOS transistor has its source connected to the power supply.

[0033] The twelfth PMOS transistor has its source connected to the power supply and its drain connected to the source of the fifteenth PMOS transistor.

[0034] The thirteenth PMOS transistor has its source connected to the power supply and its drain connected to the source of the sixteenth PMOS transistor.

[0035] The source of the fourteenth PMOS transistor is connected to the power supply, and its drain is connected to the source of the seventeenth PMOS transistor.

[0036] The thirteenth NMOS transistor has its drain connected to the source of the twelfth NMOS transistor, and its source connected to the emitter of the third NMOS transistor.

[0037] The drain of the fifteenth NMOS transistor is connected to the source of the fourteenth NMOS transistor, and the source of the fourteenth NMOS transistor is connected to ground.

[0038] The sixteenth NMOS transistor has its source connected to ground.

[0039] The drain of the seventeenth NMOS transistor is connected to the drain of the seventeenth PMOS transistor, the gate of the eighteenth NMOS transistor, the gate of the second-first NMOS transistor, the gate of the second-third NMOS transistor, the gate of the second-fifth NMOS transistor, the gate of the second-seventh NMOS transistor, and the drain of the nineteenth NMOS transistor, while its source is connected to the drain of the eighteenth NMOS transistor.

[0040] The source of the eighteenth NMOS transistor is connected to ground.

[0041] The nineteenth NMOS transistor has its source connected to ground.

[0042] The first transistor has its base and collector both connected to ground.

[0043] The base and collector of the second transistor are both connected to ground.

[0044] The third transistor has its base and collector both connected to ground.

[0045] Furthermore, the startup circuit module includes:

[0046] The output current generating module includes:

[0047] The source of the second NMOS transistor is connected to ground, and its drain is connected to the source of the twentieth NMOS transistor.

[0048] The source of the second NMOS transistor is connected to ground, and its drain is connected to the source of the second NMOS transistor.

[0049] The source of the second fifth NMOS transistor is connected to ground, and its drain is connected to the source of the second fourth NMOS transistor.

[0050] The source of the second seven NMOS transistor is connected to ground, and its drain is connected to the source of the second six NMOS transistor.

[0051] The drains of the 20th NMOS transistor, the 22nd NMOS transistor, the 24th NMOS transistor, and the 26th NMOS transistor are four sets of output voltages, and their source-drain currents are four sets of output currents.

[0052] Furthermore, the startup circuit module employs an inverting transistor design, resulting in a slow charging speed to ensure normal circuit startup. After the current reference moves away from its degeneracy point and enters normal operating condition, the current mirror provides a feedback signal to shut down the startup circuit, preventing it from drawing current from the reference current module.

[0053] Furthermore, the reference current generation module clamps the second and third transistors through a current mirror clamping action, so that the source voltage of the ninth NMOS transistor is equal to the source voltage of the thirteenth NMOS transistor.

[0054] Furthermore, the voltage drop ΔV across the second and third transistors in this circuit... be It is a positive temperature coefficient, and its expression is:

[0055]

[0056] Where n is the ratio of the emitter area of ​​the second transistor to that of the third transistor, which is 9 in this case.

[0057] Furthermore, the circuit uses two resistors with different temperature coefficients to compensate for the characteristics of the compensation resistor R2, serving as a second resistor to make its temperature characteristics consistent with ΔV. be The temperature characteristics remain consistent.

[0058] Furthermore, the expression for the reference current of the compensation is as follows:

[0059]

[0060] Furthermore, in this circuit design, ΔV be Typically, the voltage is 50-60mV, the compensation resistor is 9.57kΩ, and the reference current is approximately 6uA.

[0061] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this invention are as follows:

[0062] First, the reference current circuit of the present invention, which is approximately independent of temperature, can operate over a wide power supply range and has a self-starting circuit. The ratio of the output stage current mirror can be adjusted according to the usage requirements to obtain the required current output.

[0063] (1) Remove the op-amp clamping form in the conventional bandgap reference to make the base voltage of the transistor virtually short, thus eliminating the offset introduced by the op-amp.

[0064] (2) The current mirror adopts the Cascode common source and common gate form to eliminate the channel length modulation effect.

[0065] (3) Use feedback technology to turn off the self-starting circuit.

[0066] (4) The output current generation module provides a current mirror group that can be selected according to different situations to generate a current output that meets the usage requirements.

[0067] Secondly, this invention eliminates the operational amplifier clamping mechanism from the conventional reference, reducing the impact of operational amplifier offset voltage on the reference current and reference voltage. Therefore, it avoids the impact on subsequent circuit modules caused by errors in the reference module in large-scale circuits.

[0068] Furthermore, the current mirror adopts a cascode structure to reduce the channel modulation effect, thereby ensuring that the current of each path is replicated more accurately and avoiding the impact of current errors caused by the current mirror on subsequent circuit modules.

[0069] Furthermore, the feedback effect of the current mirror in the circuit is used to turn off the startup circuit. The current generated by the reference current generation module flows through the fifth and sixth NMOS transistors, causing the current reference to move away from the degeneracy point, thereby enabling the circuit to enter normal operating mode.

[0070] Furthermore, this technical solution can generate one or more sets of reference current outputs depending on the actual usage.

[0071] Third, the expected benefits and commercial value of the technical solution of the present invention after transformation are as follows: The technical solution of the present invention, a current reference circuit that is approximately independent of current, can be used as a circuit IP in various large-scale integrated circuits to provide a reference source for various circuits.

[0072] The technical solution of this invention solves a long-standing but unsolved technical problem: a current reference circuit that is approximately independent of current, thus solving the problem of providing high-precision current and voltage references. The reference source is a core module of an analog system, widely used as a reference source in ADCs (Analog-to-Digital Converters) or LDOs (Low Dropout Linear Regulators). Providing a reliable and accurate reference source plays a crucial role in the entire chip system.

[0073] Fourth, the significant technological advancements brought about by the temperature-independent current reference circuit of the present invention include:

[0074] 1) Temperature stability: The circuit design can effectively reduce the impact of temperature fluctuations on the current reference, so that the output current remains stable under different temperature conditions, which is especially important for applications that require precise current control.

[0075] 2) High-precision output: Through meticulously designed circuit modules, including a startup circuit module, a reference current generation module, and an output current generation module, high-precision current output can be provided, which is of great significance for improving the performance and reliability of electronic equipment.

[0076] 3) Circuit efficiency: This circuit utilizes efficient current control technology, which can reduce energy consumption and improve the overall circuit energy efficiency without sacrificing performance.

[0077] 4) Wide range of applications: Because this circuit can provide stable current output under different temperature conditions, it is suitable for a wide range of industrial and consumer electronics applications, such as precision instruments, medical equipment and communication equipment.

[0078] 5) Improve equipment reliability: In environments with large temperature fluctuations, the circuit can maintain stable performance, thereby improving the reliability and durability of the entire system.

[0079] 6) Innovative circuit design: This circuit demonstrates innovation in the field of electronic circuit design through its unique circuit design, which includes the combined use of multiple PMOS and NMOS transistors, and provides new ideas for the design of future current reference circuits.

[0080] The current reference circuit provided by this invention has achieved significant technological progress in terms of temperature stability, accuracy, efficiency, wide range of applications, equipment reliability, and circuit design innovation. Attached Figure Description

[0081] Figure 1 This is a schematic diagram of the startup circuit provided in an embodiment of the present invention.

[0082] Figure 2 This is a diagram of a current reference circuit structure that is approximately independent of temperature, provided in an embodiment of the present invention.

[0083] Figure 3 This is a simulation effect diagram of an embodiment of the present invention. Detailed Implementation

[0084] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0085] like Figure 1 As shown, an embodiment of the present invention provides a current reference circuit that is approximately independent of temperature. The circuit includes a startup circuit module, a reference current generation module, and an output current generation module.

[0086] The startup circuit module is used to power on the circuit, enabling the current reference circuit to enter normal working state.

[0087] The reference current generating module is connected to the startup circuit module and is used to generate a reference current that is approximately independent of temperature.

[0088] The output current generating module is connected to the reference current generating module to generate one or more sets of required output currents.

[0089] PMOS refers to a MOSFET with an N-type substrate and a P-type channel, which carries current through the flow of holes.

[0090] NMOS refers to a MOS transistor with a P-type substrate and an N-type channel, which relies on the flow of electrons to carry current.

[0091] like Figure 2 As shown, the startup circuit module includes:

[0092] The first PMOS transistor has its gate connected to the gate of the first NMOS transistor and one end of the first resistor, its source connected to the power supply, and its drain connected to the drain of the first NMOS transistor, the gate of the second NMOS transistor, the gate of the second PMOS transistor, the gate of the tenth PMOS transistor, and the gate of the eleventh PMOS transistor.

[0093] The first NMOS transistor has its source connected to ground.

[0094] The source of the second PMOS transistor is connected to the power supply, and its drain is connected to the drain of the second NMOS transistor and the gate of the third PMOS transistor.

[0095] The source of the second NMOS transistor is connected to ground.

[0096] The source of the third PMOS transistor is connected to the power supply, and its drain is connected to the source of the fourth PMOS transistor.

[0097] The fourth PMOS transistor has its gate and drain connected to the source of the fifth PMOS transistor.

[0098] The fifth PMOS transistor has its gate and drain connected to the drain of the third NMOS transistor, the drain of the fourth NMOS transistor, the gate of the fifth NMOS transistor, and the gate of the sixth NMOS transistor.

[0099] The third NMOS transistor has its source connected to ground, and its gate connected to the gate of the third PMOS transistor, the drain of the second NMOS transistor, the drain of the second PMOS transistor, the gate of the tenth NMOS transistor, the gate of the eleventh NMOS transistor, the gate of the sixteenth NMOS transistor, and the gate of the nineteenth NMOS transistor.

[0100] The fourth NMOS transistor has its source connected to ground, and its gate connected to the drain of the sixteenth PMOS transistor MP16, the drain and gate of the fourteenth NMOS transistor, the gate of the fifteenth NMOS transistor, the drain of the sixteenth NMOS transistor, the gate of the seventeenth NMOS transistor, the gate of the twentieth NMOS transistor, the gate of the twenty-second NMOS transistor, the gate of the twenty-fourth NMOS transistor, and the gate of the twenty-sixth NMOS transistor.

[0101] The sixth PMOS transistor has its source connected to the power supply, its drain connected to the source of the seventh PMOS transistor, and its gate connected to the gate and drain of the seventh PMOS transistor, the drain of the fifth NMOS transistor, the drain of the eighth NMOS transistor, the gate of the ninth PMOS transistor, the drain of the tenth PMOS transistor, the gate of the fifteenth PMOS transistor, the gate of the sixteenth PMOS transistor, and the gate of the seventeenth PMOS transistor.

[0102] The eighth PMOS transistor has its source connected to the power supply, its drain connected to the source of the ninth PMOS transistor, and its gate connected to the drain of the ninth PMOS transistor, the gate of the twelfth PMOS transistor, the gate of the thirteenth PMOS transistor, the gate of the fourteenth PMOS transistor, the drain of the eleventh PMOS transistor, the drain of the sixth NMOS transistor, and the drain of the seventh NMOS transistor.

[0103] The fifth NMOS transistor has its source connected to ground.

[0104] The sixth NMOS transistor has its source connected to ground.

[0105] The second NMOS transistor has its source connected to its gate, drain, and the other end of the first resistor.

[0106] Furthermore, the reference current generation module includes:

[0107] The seventh NMOS transistor has its gate connected to the gate of the twelfth NMOS transistor, the drain of the tenth NMOS transistor, and the drain of the fifteenth PMOS transistor. It is also connected to the drain of the twelfth NMOS transistor through a third resistor. Its source is connected to the drain of the ninth NMOS transistor.

[0108] The eighth NMOS transistor has its gate connected to the gate of the ninth NMOS transistor, the gate of the thirteenth NMOS transistor, the drain of the twelfth NMOS transistor, and the drain of the eleventh NMOS transistor, and its source is connected to the emitter of the first transistor.

[0109] The source of the ninth NMOS transistor is connected to the emitter of the second transistor through the second resistor.

[0110] The tenth NMOS transistor has its source connected to ground.

[0111] The eleventh NMOS transistor has its source connected to ground.

[0112] The tenth PMOS transistor has its source connected to the power supply.

[0113] The eleventh PMOS transistor has its source connected to the power supply.

[0114] The twelfth PMOS transistor has its source connected to the power supply and its drain connected to the source of the fifteenth PMOS transistor.

[0115] The thirteenth PMOS transistor has its source connected to the power supply and its drain connected to the source of the sixteenth PMOS transistor.

[0116] The source of the fourteenth PMOS transistor is connected to the power supply, and its drain is connected to the source of the seventeenth PMOS transistor.

[0117] The thirteenth NMOS transistor has its drain connected to the source of the twelfth NMOS transistor, and its source connected to the emitter of the third NMOS transistor.

[0118] The drain of the fifteenth NMOS transistor is connected to the source of the fourteenth NMOS transistor, and the source of the fourteenth NMOS transistor is connected to ground.

[0119] The sixteenth NMOS transistor has its source connected to ground.

[0120] The drain of the seventeenth NMOS transistor is connected to the drain of the seventeenth PMOS transistor, the gate of the eighteenth NMOS transistor, the gate of the second-first NMOS transistor, the gate of the second-third NMOS transistor, the gate of the second-fifth NMOS transistor, the gate of the second-seventh NMOS transistor, and the drain of the nineteenth NMOS transistor, while its source is connected to the drain of the eighteenth NMOS transistor.

[0121] The source of the eighteenth NMOS transistor is connected to ground.

[0122] The nineteenth NMOS transistor has its source connected to ground.

[0123] The first transistor has its base and collector both connected to ground.

[0124] The base and collector of the second transistor are both connected to ground.

[0125] The third transistor has its base and collector both connected to ground.

[0126] Furthermore, the startup circuit module includes:

[0127] The output current generating module includes:

[0128] The source of the second NMOS transistor is connected to ground, and its drain is connected to the source of the twentieth NMOS transistor.

[0129] The source of the second NMOS transistor is connected to ground, and its drain is connected to the source of the second NMOS transistor.

[0130] The source of the second fifth NMOS transistor is connected to ground, and its drain is connected to the source of the second fourth NMOS transistor.

[0131] The source of the second seven NMOS transistor is connected to ground, and its drain is connected to the source of the second six NMOS transistor.

[0132] The drains of the 20th NMOS transistor, the 22nd NMOS transistor, the 24th NMOS transistor, and the 26th NMOS transistor are four sets of output voltages, and their source-drain currents are four sets of output currents.

[0133] The startup circuit module employs an inverting ratio transistor design, resulting in a slow charging speed to ensure normal circuit startup. After the current reference moves away from its degeneracy point and enters normal operating condition, the current mirror provides a feedback signal to shut down the startup circuit, ceasing to draw current from the reference current module.

[0134] The reference current generation module clamps the second and third transistors through a current mirror clamping action, so that the source voltage of the ninth NMOS transistor is equal to the source voltage of the thirteenth NMOS transistor.

[0135] The voltage drop ΔV across the second and third transistors in this circuit be It is a positive temperature coefficient, and its expression is:

[0136]

[0137] Where n is the ratio of the emitter area of ​​the second transistor to that of the third transistor, which is 9 in this case.

[0138] This circuit uses two resistors with different temperature coefficients to compensate for the characteristics of the compensation resistor R2, serving as a second resistor to make its temperature characteristics consistent with ΔV. be The temperature characteristics remain consistent.

[0139] The expression for the reference current for compensation is:

[0140]

[0141] The circuit design uses ΔV be Typically, the voltage is 50-60mV, the compensation resistor is 9.57kΩ, and the reference current is approximately 6uA.

[0142] from Figure 1 The startup circuit shown employs an inverting ratio transistor design, resulting in a slow charging speed to ensure proper circuit startup. After the current reference moves away from its degeneracy point and enters normal operating condition, the current mirror provides a feedback signal to shut down the startup circuit, preventing it from drawing current from the reference current module.

[0143] from Figure 2 In the case of a reference current structure diagram that is approximately independent of temperature, the current reference generation module clamps the second and third transistors through a current mirror clamping action, so that the source voltage of the ninth NMOS transistor is equal to the source voltage of the thirteenth NMOS transistor.

[0144] In the aforementioned startup circuit module, VDD rises from 0V to the supply voltage upon power-up. The cascaded inverter input capacitor and the first resistor form an RC delay circuit. During power-up, the RC port charges slowly, generating a pulse. This pulse, after being shaped by two stages of inverters, pulls down the third NMOS transistor, which then releases the gate charge of the fifth and sixth NMOS transistors. When the pulse signal ends, the third PMOS transistor injects charge into the gates of the fifth and sixth NMOS transistors. Because this invention uses an inverting transistor design, the charging speed is relatively slow to ensure normal circuit startup.

[0145] When charge is injected into the gates of the fifth and sixth NMOS transistors, the low-resistance nodes such as the current mirror of the reference current generation module are pulled down, so that the current of the reference current generation module flows through the fifth and sixth NMOS transistors, and the current reference is removed from the degeneracy point and enters the normal working state.

[0146] Under normal operating conditions, the current mirror pulls the current in the startup circuit to ground through feedback, shutting off the startup circuit and no longer drawing current from the reference current generation module.

[0147] The output current module, employing a current mirror design, can obtain one or more sets of required output currents. The width-to-length ratio of the MOSFETs at the corresponding output nodes can be configured to amplify or reduce the reference current, thereby obtaining one or more sets of output currents.

[0148] Furthermore, due to the replication effect of the current mirror, the ratio of the corresponding current mirror can be adjusted in the output current generation module to obtain a large or small current that is consistent with the current change curve of the reference current, thus providing a reference current for the next stage circuit.

[0149] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A current reference circuit that is approximately independent of temperature, characterized in that, The circuit includes a startup circuit module, a reference current generation module, and an output current generation module; The startup circuit module is used to start the circuit and power it on, so that the current reference circuit can enter the normal working state. The reference current generating module is connected to the startup circuit module and is used to generate a reference current that is approximately independent of temperature. The output current generating module is connected to the reference current generating module to generate one or more sets of required output currents. The startup circuit module includes: The first PMOS transistor has its gate connected to the gate of the first NMOS transistor and one end of the first resistor, its source connected to the power supply, and its drain connected to the drain of the first NMOS transistor, the gate of the second NMOS transistor, the gate of the second PMOS transistor, the gate of the tenth PMOS transistor, and the gate of the eleventh PMOS transistor. The first NMOS transistor has its source connected to ground; The second PMOS transistor has its source connected to the power supply and its drain connected to the drain of the second NMOS transistor and the gate of the third PMOS transistor. The source of the second NMOS transistor is connected to ground. The source of the third PMOS transistor is connected to the power supply, and its drain is connected to the source of the fourth PMOS transistor. The fourth PMOS transistor has its gate and drain connected to the source of the fifth PMOS transistor; The fifth PMOS transistor has its gate and drain connected to the drain of the third NMOS transistor, the drain of the fourth NMOS transistor, the gate of the fifth NMOS transistor, and the gate of the sixth NMOS transistor. The third NMOS transistor has its source connected to ground, and its gate connected to the gate of the third PMOS transistor, the drain of the second NMOS transistor, the drain of the second PMOS transistor, the gate of the tenth NMOS transistor, the gate of the eleventh NMOS transistor, the gate of the sixteenth NMOS transistor, and the gate of the nineteenth NMOS transistor. The fourth NMOS transistor has its source connected to ground, and its gate connected to the drain of the sixteenth PMOS transistor MP16, the drain and gate of the fourteenth NMOS transistor, the gate of the fifteenth NMOS transistor, the drain of the sixteenth NMOS transistor, the gate of the seventeenth NMOS transistor, the gate of the twentieth NMOS transistor, the gate of the twenty-second NMOS transistor, the gate of the twenty-fourth NMOS transistor, and the gate of the twenty-sixth NMOS transistor. The sixth PMOS transistor has its source connected to the power supply, its drain connected to the source of the seventh PMOS transistor, and its gate connected to the gate and drain of the seventh PMOS transistor, the drain of the fifth NMOS transistor, the drain of the eighth NMOS transistor, the gate of the ninth PMOS transistor, the drain of the tenth PMOS transistor, the gate of the fifteenth PMOS transistor, the gate of the sixteenth PMOS transistor, and the gate of the seventeenth PMOS transistor. The eighth PMOS transistor has its source connected to the power supply, its drain connected to the source of the ninth PMOS transistor, and its gate connected to the drain of the ninth PMOS transistor, the gate of the twelfth PMOS transistor, the gate of the thirteenth PMOS transistor, the gate of the fourteenth PMOS transistor, the drain of the eleventh PMOS transistor, the drain of the sixth NMOS transistor, and the drain of the seventh NMOS transistor. The fifth NMOS transistor has its source connected to ground; The sixth NMOS transistor has its source connected to ground; The second NMOS transistor has its source connected to its gate, drain, and the other end of the first resistor; The reference current generation module includes: The seventh NMOS transistor has its gate connected to the gate of the twelfth NMOS transistor, the drain of the tenth NMOS transistor, and the drain of the fifteenth PMOS transistor. It is also connected to the drain of the twelfth NMOS transistor through the third resistor. Its source is connected to the drain of the ninth NMOS transistor. The eighth NMOS transistor has its gate connected to the gate of the ninth NMOS transistor, the gate of the thirteenth NMOS transistor, the drain of the twelfth NMOS transistor, and the drain of the eleventh NMOS transistor, and its source is connected to the emitter of the first transistor. The source of the ninth NMOS transistor is connected to the emitter of the second transistor through the second resistor; The tenth NMOS transistor has its source connected to ground; The eleventh NMOS transistor has its source connected to ground. The tenth PMOS transistor has its source connected to the power supply. The eleventh PMOS transistor has its source connected to the power supply. The twelfth PMOS transistor has its source connected to the power supply and its drain connected to the source of the fifteenth PMOS transistor. The thirteenth PMOS transistor has its source connected to the power supply and its drain connected to the source of the sixteenth PMOS transistor. The source of the fourteenth PMOS transistor is connected to the power supply, and its drain is connected to the source of the seventeenth PMOS transistor. The thirteenth NMOS transistor has its drain connected to the source of the twelfth NMOS transistor, and its source connected to the emitter of the third transistor. The drain of the fifteenth NMOS transistor is connected to the source of the fourteenth NMOS transistor, and its source is connected to ground. The sixteenth NMOS transistor has its source connected to ground. The drain of the seventeenth NMOS transistor is connected to the drain of the seventeenth PMOS transistor, the gate of the eighteenth NMOS transistor, the gate of the second-first NMOS transistor, the gate of the second-third NMOS transistor, the gate of the second-fifth NMOS transistor, the gate of the second-seventh NMOS transistor, and the drain of the nineteenth NMOS transistor, and its source is connected to the drain of the eighteenth NMOS transistor. The eighteenth NMOS transistor has its source connected to ground. The nineteenth NMOS transistor has its source connected to ground. The first transistor has its base and collector both connected to ground; The base and collector of the second transistor are both connected to ground; The third transistor has its base and collector both connected to ground.

2. The current reference circuit that is approximately independent of temperature as described in claim 1, characterized in that, The startup circuit module includes: The output current generating module includes: The source of the second NMOS transistor is connected to ground, and its drain is connected to the source of the twentieth NMOS transistor. The source of the second NMOS transistor is connected to ground, and its drain is connected to the source of the second NMOS transistor. The source of the second fifth NMOS transistor is connected to ground, and its drain is connected to the source of the second fourth NMOS transistor. The source of the second seven NMOS transistor is connected to ground, and its drain is connected to the source of the second six NMOS transistor. The drains of the 20th NMOS transistor, the 22nd NMOS transistor, the 24th NMOS transistor, and the 26th NMOS transistor are four sets of output voltages, and their source-drain currents are four sets of output currents.

3. The current reference circuit that is approximately independent of temperature as described in claim 1, characterized in that, The startup circuit module adopts an inverted ratio transistor design, which slows down the charging speed to ensure that the circuit can start normally. After the current reference moves away from the degeneracy point and enters the normal working state, the current mirror provides a feedback signal to turn off the startup circuit and stop drawing current from the reference current module.

4. The current reference circuit that is approximately independent of temperature as described in claim 1, characterized in that, The reference current generation module clamps the second and third transistors through a current mirror clamping action, so that the source voltage of the ninth NMOS transistor is equal to the source voltage of the thirteenth NMOS transistor.

5. The current reference circuit that is approximately independent of temperature as described in claim 1, characterized in that, The voltage drop ΔV across the second and third transistors of the circuit be is positive and is expressed by Where n is the ratio of the emitter area of ​​the second transistor to that of the third transistor, which is 9 in this case.

6. The current reference circuit that is approximately independent of temperature as described in claim 1, characterized in that, This circuit uses two resistors with different temperature coefficients to compensate for the characteristics of the compensation resistor R2, serving as a second resistor to make its temperature characteristics consistent with ΔV. be The temperature characteristics remain consistent.

7. The current reference circuit that is approximately independent of temperature as described in claim 6, characterized in that, The expression for the compensation reference current is: 。 8. The current reference circuit that is approximately independent of temperature as described in claim 7, characterized in that, The circuit design uses ΔV be Typically, the voltage is 50-60mV, the compensation resistor R2 is 9.57kΩ, and the reference current is 6uA.

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