Quantum circuit mapping method, device and electronic device

Abstract

The present disclosure provides a quantum circuit mapping method, device and electronic device, which relates to the field of quantum computing technology, and specifically to the field of quantum circuit technology. The specific implementation scheme is: based on the arrangement structure information of quantum bits on the quantum chip, obtain the coupling graph of the quantum chip; obtain the interaction graph of the first logical quantum circuit precompiled on the quantum chip; search for the first subgraph isomorphic to the interaction graph in the reduced search space of the coupling graph, and the reduced search space includes a set of nodes in the coupling graph whose distance from the generated set does not exceed a specified distance; using the grid structure of the coupling graph, the first subgraph is translated on the coupling graph to obtain the second subgraph; determine the first mapping scheme corresponding to each subgraph in the subgraph set; based on the fidelity of the physical quantum gate on the quantum chip, determine the target mapping scheme from the first mapping scheme corresponding to the subgraph set.

Description

Technical Field

[0001] The present disclosure relates to the field of quantum computing technology, in particular to the field of quantum circuit technology, and specifically to a quantum circuit mapping method, device and electronic device. Background Art

[0002] Quantum circuit mapping is an important problem in quantum computing and plays an important role in alleviating the impact of noise on quantum computing. It involves selecting a set of physical quantum bits in a quantum processor (also known as a quantum chip) to construct quantum gates to execute a given logical quantum circuit.

[0003] In essence, the quantum circuit mapping problem is about determining the mapping relationship between the quantum bits (or quantum gates) in the logical quantum circuit and the physical quantum bits (or quantum gates) in the quantum processor. Due to the limitations of existing micro-nano processing and measurement and control technologies, the performance of the quantum bits (or quantum gates) on the quantum processor varies.

[0004] Generally, quantum circuit mapping should avoid quantum bits and quantum gates with poor quality, and select appropriate quantum bits and quantum gates to execute quantum algorithms to reduce errors that may occur during the operation of quantum circuits and obtain high-fidelity computing results. Summary of the invention

[0005] The present disclosure provides a quantum circuit mapping method, device and electronic device.

[0006] According to a first aspect of the present disclosure, a quantum circuit mapping method is provided, comprising:

[0007] Based on the arrangement structure information of the quantum bits on the quantum chip, obtaining a coupling diagram of the quantum chip; and obtaining an interaction diagram of a first logic quantum circuit precompiled onto the quantum chip, wherein the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in a grid structure;

[0008] searching for a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, the reduced search space comprising a set of nodes in the coupling graph whose distances from a spanning set do not exceed a specified distance, the specified distance being greater than or equal to a radius of the interaction graph, the spanning set comprising at least one adjacent node in the coupling graph;

[0009] Using the grid structure of the coupling graph, performing a translation operation on the first subgraph on the coupling graph to obtain a second subgraph isomorphic to the interaction graph;

[0010] Determine each subgraph in the subgraph collection Figure 1a corresponding first mapping scheme, wherein the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph;

[0011] Based on the fidelity of the physical quantum gates on the quantum chip, a target mapping scheme from the first logical quantum circuit to the quantum chip is determined from the first mapping schemes corresponding to the subgraph set.

[0012] According to a second aspect of the present disclosure, a quantum circuit mapping device is provided, comprising:

[0013] An acquisition module is used to acquire a coupling diagram of the quantum chip based on the arrangement structure information of the quantum bits on the quantum chip; and to acquire an interaction diagram of a first logic quantum circuit precompiled onto the quantum chip, wherein the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in a grid structure;

[0014] A search module, configured to search a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, the reduced search space comprising a set of nodes in the coupling graph whose distances from a spanning set do not exceed a specified distance, the specified distance being greater than or equal to a radius of the interaction graph, the spanning set comprising at least one adjacent node in the coupling graph;

[0015] A translation operation module, used to perform a translation operation on the first subgraph on the coupling graph by using the grid structure of the coupling graph, so as to obtain a second subgraph isomorphic to the interaction graph;

[0016] The first determination module is used to determine each subgraph in the subgraph set. Figure 1 a corresponding first mapping scheme, wherein the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph;

[0017] The second determination module is used to determine a target mapping scheme from the first logical quantum circuit to the quantum chip from the first mapping scheme corresponding to the subgraph set based on the fidelity of the physical quantum gate on the quantum chip.

[0018] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0019] at least one processor; and

[0020] a memory communicatively connected to at least one processor; wherein,

[0021] The memory stores instructions that can be executed by at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform any method in the first aspect.

[0022] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to execute any one of the methods in the first aspect.

[0023] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program, which implements any one of the methods in the first aspect when executed by a processor.

[0024] The technology disclosed in the present invention solves the problem of low mapping efficiency of quantum circuits on quantum chips with a grid structure in the related art, and can improve the mapping efficiency of quantum circuits on quantum chips with a grid structure.

[0025] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0027] Figure 1 is a flowchart of a quantum circuit mapping method according to the first embodiment of the present disclosure;

[0028] Figure 2 It is a schematic diagram of the structure of an example of a logic quantum circuit;

[0029] Figure 3 It is a schematic diagram of the structure of an interaction diagram of an example logic quantum circuit;

[0030] Figure 4 is a schematic diagram of the structure of a coupling diagram of an example quantum chip;

[0031] Figure 5 It is a performance operation diagram of different subgraph matching schemes;

[0032] Figure 6 is a schematic diagram of the performance operation of different circuit mapping scoring schemes;

[0033] Figure 7 It is a performance operation diagram of different circuit mapping schemes;

[0034] Figure 8 is a schematic structural diagram of a quantum circuit mapping device according to a second embodiment of the present disclosure;

[0035] Fig. 9 is a schematic block diagram of an example electronic device for implementing an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0037] First embodiment

[0038] like Figure 1 As shown, the present disclosure provides a quantum circuit mapping method, comprising the following steps:

[0039] Step S101: based on the arrangement structure information of the quantum bits on the quantum chip, obtaining a coupling diagram of the quantum chip; and obtaining an interaction diagram of a first logic quantum circuit precompiled onto the quantum chip, wherein the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in a grid structure;

[0040] Among them, the coupling diagram is used to characterize the physical connection between quantum bits, the coupling diagram is a grid structure, and the interaction diagram is used to characterize the interaction between quantum bits involved in the execution process of the first logical quantum circuit.

[0041] In this embodiment, the quantum circuit mapping method relates to the field of quantum computing technology, and in particular to the field of quantum circuit technology. It can be widely used in quantum circuit mapping scenarios, and has important significance for the practical applications of quantum computing, such as code breaking, drug development, and machine learning. The quantum circuit mapping method of the disclosed embodiment can be performed by the quantum circuit mapping device of the disclosed embodiment. The quantum circuit mapping device of the disclosed embodiment can be configured in any electronic device to perform the quantum circuit mapping method of the disclosed embodiment.

[0042] Quantum computing is a new computing model that uses the characteristics of quantum mechanics to perform calculations. Unlike classical computing, quantum computing uses phenomena such as quantum superposition and entanglement of quantum bits (qubits), allowing more efficient calculations in some cases. In quantum computing, calculations are no longer based solely on the 0 and 1 of classical bits, but allow for a certain degree of superposition of 0 and 1 at the same time, as well as entanglement between different quantum bits.

[0043] These quantum properties allow the design of quantum algorithms that are more efficient than classical algorithms. For example, Shor's algorithm can speed up the factorization of large numbers, which helps in password cracking; quantum algorithms such as the HHL algorithm can speed up the solution of linear equations and have great application value in engineering practice.

[0044] Noise is a major challenge facing quantum computers, limiting their performance and reliability. Noise can come from many sources, including hardware processing defects, environmental interference, and crosstalk between quantum bits. In order to reduce the impact of noise on quantum computing, a variety of solutions have been proposed, including hardware technologies such as environmental isolation, and software technologies such as quantum error correction codes and quantum circuit mapping.

[0045] This embodiment is aimed at quantum circuit mapping in software to reduce noise during the operation of logical quantum circuits. Quantum circuit mapping is an important issue in quantum computing and plays an important role in alleviating the impact of noise on quantum computing. It involves selecting a set of physical quantum bits and quantum gates in a quantum processor (also known as a quantum chip) to execute a given quantum algorithm (i.e., a logical quantum circuit).

[0046] Essentially, the quantum circuit mapping problem is about determining the mapping relationship between the qubits (or quantum gates) in the logical quantum circuit and the physical qubits (or quantum gates) in the quantum processor. In particular, due to the limitations of existing micro-nano processing and measurement and control technologies, the performance of qubits (or quantum gates) on quantum processors varies. An ideal quantum circuit mapping should avoid qubits and quantum gates of poor quality, thereby reducing the errors that may occur during the operation of the quantum circuit.

[0047] Due to the complex entanglement and coupling between quantum bits, and the fact that actual quantum gate operations may be affected by noise and errors, mapping logical quantum circuits to physical quantum circuits is a complex optimization problem. This usually involves solving problems such as quantum bit connection restrictions, noise tolerance, and reordering and optimization of quantum gates.

[0048] Current quantum processors are susceptible to environmental noise during operation. Specifically, as the depth of the quantum circuit and the number of quantum gates increase, the fidelity of the quantum circuit decays exponentially, and the decrease in fidelity means that the probability of obtaining the correct result of the quantum computing operation decreases. Therefore, in order to achieve large-scale quantum computing, an effective error mitigation scheme must be used to suppress the decrease in the fidelity of the quantum circuit.

[0049] Quantum circuit mapping reduces the impact of noise during the operation of quantum circuits by selecting a set of high-quality quantum bits and quantum gates to run a given quantum algorithm. The use of appropriate quantum circuit mapping can significantly improve the fidelity of quantum algorithm operation. However, selecting a better quantum circuit mapping is itself an NP-hard problem, which means that searching for a better quantum circuit mapping is usually accompanied by a lot of computational overhead. Therefore, how to design an efficient quantum circuit mapping algorithm is a key problem that needs to be solved.

[0050] This embodiment is aimed at the grid-type chip structure widely used in quantum processors, and proposes an efficient quantum circuit mapping scheme for this type of quantum hardware. That is, by utilizing the structural characteristics of quantum chips, an efficient quantum circuit mapping scheme suitable for quantum chips with grid structures is implemented.

[0051] The following is an explanation of the basic concepts related to quantum circuit mapping.

[0052] Quantum circuit: A qubit is the basic unit of quantum information and the quantum counterpart of a classical bit. A qubit can exist in a superposition of states or be entangled with other qubits, enabling powerful quantum computing. A quantum gate is an operation that acts on one or more qubits. Specifically, a quantum gate defines a specific evolution of a quantum state, which can be considered the basic building block of a quantum circuit, similar to a classical logic gate. A sequence of multiple quantum gates is called a quantum circuit. A quantum circuit essentially defines the evolution of an initial quantum state. By designing / programming a quantum circuit, any quantum algorithm can be implemented.

[0053] Quantum circuit interaction graph: A quantum circuit interaction graph is a graph representation of a quantum circuit. This is a structure consisting of a set of nodes and edges connecting some nodes. Specifically, given a quantum circuit, each quantum bit in the quantum circuit is represented by a node. For each two-qubit gate in the circuit, an edge is used to connect the nodes corresponding to the quantum bits acted on by the quantum gate. In this way, a graph is constructed. This graph is the interaction graph of the quantum circuit, which is used to represent the interaction between the quantum bits involved in the execution of the quantum circuit, or the connectivity between the logical quantum bits.

[0054] Quantum processor coupling graph: A quantum processor is a quantum chip. The coupling graph of a quantum hardware device represents the physical connection between the quantum bits used to implement a two-qubit gate. In other words, it shows which quantum bits can interact directly with each other, and these interactions are essential for performing the multi-qubit operations required for quantum computing. The structure of the coupling graph can significantly affect the functionality of a quantum processor. A dense (well-connected) coupling graph means that the quantum chip can effectively execute quantum algorithms and reduce noise interference. A sparse (poorly connected) coupling graph may pose challenges to the implementation of certain algorithms because it may require quantum bits that are not directly coupled to interact.

[0055] In particular, a grid-type coupling graph is one of the most common quantum chip coupling graphs, and the quantum bits and connections between the bits on a quantum chip with a grid-type coupling graph form a grid. In view of this, this embodiment is aimed at the quantum circuit mapping problem of a quantum chip with a grid structure.

[0056] Quantum circuit compilation: Quantum circuit compilation refers to the process of converting advanced quantum algorithms or quantum gate operations into physical quantum gate sequences that can be executed on a specific hardware platform. The main goal of quantum circuit compilation is to optimize the sequence of quantum gate operations to minimize errors and noise in the calculation process, while converting quantum gates that are not supported by the hardware so that the quantum circuit meets the limitations of the hardware. The workflow of quantum circuit compilation is as follows:

[0057] 1. Determine the initial circuit mapping;

[0058] 2. Introduce SWAP gates to meet the qubit connection requirements (i.e. pre-compilation);

[0059] 3. Perform secondary mapping on the circuit to enhance fidelity (secondary quantum circuit mapping after circuit compilation); the secondary mapping of quantum circuits involves subgraph matching and quantum circuit mapping scoring;

[0060] 4. Convert the quantum gates in the circuit into hardware-native quantum gates;

[0061] 5. Optimize the circuit to minimize the total number of quantum gates;

[0062] 6. Output quantum circuit.

[0063] Among them, quantum circuit mapping is a sub-process of quantum circuit compilation, and in this embodiment, a secondary quantum circuit mapping is performed on the pre-compiled quantum circuit, that is, the first logic quantum circuit is the logic quantum circuit obtained after pre-compilation. In an optional implementation, the original logic quantum circuit can be pre-compiled onto the quantum chip to obtain the pre-compiled first logic quantum circuit. In another optional implementation, a local area of ​​the quantum chip can be selected, and the original logic quantum circuit can be pre-compiled onto the local area of ​​the quantum chip to obtain the pre-compiled first logic quantum circuit.

[0064] Correspondingly, based on the operation instructions of the first logic quantum circuit, an interaction diagram of the first logic quantum circuit can be obtained.

[0065] The coupling graph of a quantum chip can be obtained based on the arrangement structure information of the physical quantum bits in the quantum chip, wherein the structure of the quantum chip is a grid structure, and accordingly, its coupling graph is also a grid structure. Based on the arrangement structure information, each quantum bit on the quantum chip can be obtained, and a node can be created for each quantum bit on the quantum chip to construct the coupling graph of the quantum chip.

[0066] The following describes in detail the logic of the quantum circuit quadratic mapping algorithm.

[0067] The first logical quantum circuit obtained by pre-compilation of the quantum circuit can be used as input. The goal is to identify the area on the quantum chip that is topologically equivalent to the input circuit (called an isomorphic subgraph) so that the circuit can be physically realized.

[0068] This involves solving the subgraph matching problem. After completing this step, a set of isomorphic subgraphs on the quantum chip can be obtained. Each subgraph corresponds to a mapping from logical qubits in the quantum circuit to actual physical qubits on the quantum hardware, which is called a feasible quantum circuit mapping scheme.

[0069] Then, for these feasible quantum circuit mapping schemes, the corresponding quantum circuit fidelity can be estimated, the feasible quantum circuit mappings can be ranked according to their scores, and the corresponding target mapping scheme can be selected based on the score ranking. In an optional implementation, the quantum circuit mapping with the highest score (the corresponding quantum circuit with the lowest error rate) can be selected as the output. In essence, the circuit mapping is optimized under the premise of meeting the hardware limitations of the quantum chip to minimize the probability of errors during the execution of the quantum circuit.

[0070] It is worth noting that the quantum circuit remapping involves searching for a set of physical qubits on the quantum hardware whose connectivity is equivalent to the connectivity between the logical bits in the input quantum circuit. Specifically, it is necessary to search for a subgraph in the coupling graph of the quantum chip that is isomorphic to the interaction graph of the quantum circuit. This problem is called the subgraph matching problem.

[0071] However, the subgraph matching problem is an NP-complete problem, which means that the quantum circuit remapping requires a relatively large computational overhead and has poor scalability. The relevant technology cannot handle the circuit mapping problem on large-scale quantum chips. In addition, the research and development of quantum computers has made significant progress in recent years. The latest quantum computers already have hundreds of qubits, and this number is expected to increase thousands of times in the next few years. In view of these developments, the relevant quantum circuit remapping schemes will be difficult to apply to recent quantum computers.

[0072] The purpose of this embodiment is to use the symmetry of the grid chip structure to accelerate the search process of circuit mapping, which has the advantage of significantly improving the search speed and realizing an efficient quantum circuit mapping scheme suitable for grid structure quantum chips. In addition, based on pre-compilation, the second mapping of quantum circuits is used to obtain the target mapping scheme from the first logical quantum circuit to the quantum chip, which can optimize the mapping of quantum circuits and improve the fidelity of quantum circuits, thereby obtaining high-fidelity quantum computing results.

[0073] Step S102: Search for a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, wherein the reduced search space includes a set of nodes in the coupling graph whose distance from a generation set does not exceed a specified distance, and the specified distance is greater than or equal to the radius of the interaction graph, and the generation set includes at least one adjacent node in the coupling graph.

[0074] The core problem of the quadratic mapping of quantum circuits is the subgraph matching problem. In the subgraph matching problem, given two graphs, usually called pattern graph G and target graph P, the goal is to find all subgraphs G′ in the target graph that are isomorphic to the pattern graph (i.e., have the same structure and connection mode). Indicates that graphs G′ and G are isomorphic.

[0075] A first subgraph isomorphic to the interaction graph may be searched in a reduced search space of the coupling graph. The reduced search space may be determined based on a spanning set, which includes a set of nodes in the coupling graph whose distances to the spanning set do not exceed a specified distance.

[0076] As long as the selected generation set can cover the entire target graph under the corresponding translation transformation, all isomorphic subgraphs can be searched based on the first subgraph under the translation transformation, and the logical correctness can be guaranteed. Optionally, the generation set includes four nodes at the center of the coupling graph, which is a four-node ring, and the corresponding translation transformation is a translation in the horizontal or vertical direction. This set of generation sets and translation transformations meet the above requirements of covering the complete target graph.

[0077] The specified distance needs to be greater than or equal to the radius of the interaction graph, so that the first subgraph isomorphic to the interaction graph can be found in the reduced search space. The radius of the interaction graph can be the maximum step length from a node to the central node in the graph.

[0078] An existing or new subgraph search method may be used to search for all first subgraphs isomorphic to the interaction graph in the reduced search space of the coupling graph, which is not specifically limited here.

[0079] In this step, by limiting the reduced search space of the coupling graph and searching for a subgraph isomorphic to the interaction graph in the reduced search space of the coupling graph, the scope of the subgraph search can be narrowed and the amount of computation of the subgraph search can be reduced.

[0080] Step S103: utilizing the grid structure of the coupling graph, performing a translation operation on the first subgraph on the coupling graph to obtain a second subgraph isomorphic to the interaction graph.

[0081] In the field of quantum computing, symmetry plays a key role and provides a wide range of applications. It has been exploited to optimize resource usage efficiency in variational quantum eigensolvers, reduce error rates in quantum approximate optimization algorithms, efficiently design quantum error correction codes, and promote the development of quantum machine learning models.

[0082] A given logical quantum circuit can be mapped to a set of quantum bits and quantum gates on quantum hardware, so that the interaction graph of the quantum circuit and the coupling graph of the hardware are compatible, and the fidelity of the quantum circuit is high. In particular, the symmetry of the quantum chip structure can be used to significantly improve the efficiency of quantum circuit mapping.

[0083] In this step, when the first subgraph is obtained, for each first subgraph, the symmetry of the grid structure of the coupling graph of the quantum chip can be used to simulate the movement of the first subgraph to various positions of the coupling graph by translation, and the node coordinates of the moved subgraph are determined based on the number of translation steps to obtain the second subgraph, so that all subgraphs that are isomorphic to the interaction graph can be searched to form a subgraph set, thereby realizing subgraph matching of the secondary mapping of the quantum circuit, and the search speed is very efficient.

[0084] In an optional embodiment, the translation operation of the first subgraph in the coupling graph can be simulated by software to obtain a second subgraph isomorphic to the interaction graph. In another optional embodiment, the symmetry of the grid structure of the coupling graph can be used to construct an update range of the translation transformation of the coordinates of the first subgraph in the coupling graph, and based on the update range, the coordinates of the first subgraph are updated to obtain a second subgraph isomorphic to the interaction graph.

[0085] Step S104: Determine each subgraph in the subgraph set. Figure 1 A corresponding first mapping scheme, where the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph.

[0086] Each subgraph corresponds to a mapping from the interaction graph of the first logic quantum circuit to the quantum chip, and based on the pre-compilation, a mapping from the first logic quantum circuit to the quantum chip can be obtained. Accordingly, through the double mapping, all first mapping schemes from the first logic quantum circuit to the quantum chip can be obtained, and the first mapping scheme can be called a feasible quantum circuit mapping scheme.

[0087] Step S105: Based on the fidelity of the physical quantum gate on the quantum chip, determine a target mapping scheme from the first logical quantum circuit to the quantum chip from the first mapping scheme corresponding to the subgraph set.

[0088] In this step, the target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip in each first mapping scheme can be obtained based on the fidelity of the physical quantum gate on the quantum chip. Based on the target fidelity, the first mapping schemes are sorted, and the first mapping scheme with the largest target fidelity can be selected as the target mapping scheme, or any first mapping scheme with a target fidelity greater than or equal to a specified threshold can be selected as the target mapping scheme.

[0089] In this embodiment, a secondary circuit mapping technique is used. After the circuit is precompiled, a subgraph matching search is performed in a reduced search space of a coupling graph determined based on a generation set to obtain a first subgraph isomorphic to the interaction graph of the precompiled first logic quantum circuit. Then, a translation operation is performed on the first subgraph on the coupling graph using a grid structure of the coupling graph to obtain a second subgraph isomorphic to the interaction graph. Accordingly, all quantum circuit mappings can be searched through subgraph matching. Based on the fidelity of the physical quantum gates on the quantum chip, a target mapping scheme that makes the fidelity of the quantum circuit high is selected from all the first mapping schemes. In this way, the difference in error rates of different physical quantum gates is fully considered, and the mapping of the quantum circuit can be optimized to improve the fidelity of the quantum circuit. Moreover, by effectively reducing the search space for subgraph matching and by utilizing the structural characteristics of quantum hardware, that is, utilizing the symmetry of the grid structure of the quantum chip to perform translational transformation of subgraphs to search for other subgraphs, the subgraph search process of circuit mapping can be accelerated, and efficient translational transformation of a group of quantum bits can be achieved. This significantly simplifies the process of searching for quantum circuit mapping, has the advantage of significantly improving the search speed, and realizes an efficient quantum circuit mapping scheme suitable for quantum chips with grid structures.

[0090] Accordingly, after the input circuit is precompiled onto the quantum chip to obtain the first logical quantum circuit and the target mapping scheme is determined, the first logical quantum circuit is mapped onto the quantum chip with a grid structure according to the target mapping scheme, so as to actually run the input circuit on the quantum chip to perform actual quantum computing tasks, such as quantum communication, quantum computing protocols, and quantum key distribution protocols. Moreover, the accuracy of quantum algorithm operation on large quantum processors can be improved, making up for the shortcomings of current quantum computing that is easily affected by environmental noise, which is of great significance to the practical applications of quantum computing, such as code breaking, drug development, and machine learning.

[0091] Optionally, the step S101 specifically includes:

[0092] Selecting a local area in the area range of the quantum chip, wherein the number of physical quantum bits deployed in the local area is greater than or equal to the number of logical quantum bits of the second logical quantum circuit;

[0093] The second logic quantum circuit is precompiled onto the local region to obtain an interaction graph of the first logic quantum circuit.

[0094] In this embodiment, a local area of ​​the quantum chip can be selected to precompile the second logic quantum circuit, in which the physical quantum bits are connected to each other and can be any area, and the number of physical quantum bits deployed in the local area is greater than or equal to the number of logical quantum bits of the second logic quantum circuit. The second logic quantum circuit is a precompiled input circuit and is transformed into the first logic quantum circuit after precompilation.

[0095] A quantum circuit compiler can be used to precompile the input second logic quantum circuit to the selected local area to obtain the precompiled first logic quantum circuit and a mapping scheme from the first logic quantum circuit to the quantum chip.

[0096] For the original logic quantum circuit, that is, the second logic quantum circuit, after pre-compilation, it can be equivalently converted into the first logic quantum circuit. The running effect of the first logic quantum circuit on the quantum chip is consistent with the execution effect of the second logic quantum circuit. Therefore, through secondary mapping, the mapping of the original logic quantum circuit on the quantum chip can be realized.

[0097] In this implementation, by selecting a local area of ​​the quantum chip to precompile the second logic quantum circuit, the execution efficiency of the precompile can be improved, thereby further improving the mapping efficiency of the quantum circuit.

[0098] Optionally, before searching the reduced search space of the coupling graph for a first subgraph isomorphic to the interaction graph, the method further includes:

[0099] Determining an r-order neighborhood of the generated set, where r is the radius of the interaction graph;

[0100] The r-order neighborhood is determined as a reduced search space of the coupling graph.

[0101] Among them, the k-order neighborhood of a node subset S of graph P is defined as the set of all nodes whose distance from S does not exceed k, denoted as If all nodes of the subgraph G′ of graph P are in the neighborhood, In addition, Indicates that G′ is a subgraph of P.

[0102] Among them, the node subset S is the generated set, and the radius r of the interaction graph can be used as the limit of the neighborhood range. In this way, the determination of the reduced search space can be achieved and the complexity of the subgraph search can be reduced.

[0103] Since there may be more than one center of the interaction graph, optionally, the radius of the interaction graph is determined by:

[0104] Taking the node located in the central area of ​​the interaction graph as the target node, obtaining the maximum step length from the node in the interaction graph to the target node, and obtaining the target step length corresponding to the target node;

[0105] The step length with the shortest distance among the target step lengths corresponding to the target nodes in the central area is determined as the radius of the interaction graph.

[0106] In this way, determination of the radius of the interaction graph may be achieved.

[0107] Optionally, the step S103 specifically includes:

[0108] determining a width and a height of the coupling graph;

[0109] Based on the width and the node coordinates of the first subgraph, determine the number of steps required for the first subgraph to move horizontally to the boundary of the coupling graph in units of grids; and based on the height and the node coordinates of the first subgraph, determine the number of steps required for the first subgraph to move vertically to the boundary of the coupling graph in units of grids;

[0110] Based on the number of steps required to move horizontally and vertically to the boundary of the coupling graph, construct an update range of the node coordinates of the first subgraph during the movement on the coupling graph;

[0111] Based on the update range, the node coordinates of the first subgraph are updated to obtain a second subgraph isomorphic to the interaction graph.

[0112] The following is a detailed description of the process of using the grid symmetry structure to perform subgraph matching. The nodes are labeled with the row and column coordinates of the grid graph, and the node in the xth row and yth column of the graph P is recorded as (x, y), where (x, y)∈P, and x, y are natural numbers. It should be noted that the definition of translation symmetry in the following process is paired with the selection of the generating set, that is, the number of steps required for horizontal and vertical movement in the translation process is different if the selection of the generating set is different.

[0113] Input: pattern graph G (i.e. interaction graph), grid target graph P (i.e. coupling graph);

[0114] Output: All subgraphs in the target graph P that are isomorphic to G.

[0115] Step 1: Locate the four nodes at the center of the grid-type target graph P, and define the set of these nodes as the generating set S of the target graph P;

[0116] Step 2: Calculate the radius r of the pattern graph G by using a related algorithm such as an algorithm built into the Python toolkit NetworkX;

[0117] Step 3: Calculate the r-order neighborhood of the generating set S As a reduced search space for subsequent subgraph matching;

[0118] Step 4: Find a subgraph isomorphic to the pattern graph G in the reduced search space Get a set of isomorphic subgraphs (i.e. the first subgraph);

[0119] Step 5: Traverse the coordinates of all nodes of the target graph P and calculate the width width = max{x:(x,y)∈P}+1 and height height = max{y:(x,y)∈P}+1 of the target graph;

[0120] Step 6: Initialize an empty list R;

[0121] Step 7: For G'∈R reduced Make a loop (i.e., for each first subgraph, execute steps 7.1 and 7.2):

[0122] Step 7.1: Calculate the number of steps required for G' to move horizontally to the left to the boundary with P, recorded as n left = min{x:(x,y)∈G'}; calculate the number of steps required for G' to move horizontally to the right to the boundary with P, recorded as n right =width-max{x:(x,y)∈G'}-1; calculate the number of steps required for G' to move vertically upward to the boundary with P, recorded as m up= height-max{y:(x,y)∈G'}-1; calculate the number of steps required for G' to move vertically downward to the boundary with P, recorded as m down =min{y:(x,y)∈G'}; change n∈{-n left +1,-n left +2,...,n right -1} as the outer loop, m∈{-m up +1,-m up +2,...,m down -1} as inner loop:

[0123] Step 7.2: Shift G' to the right by n steps (i.e., increase the column coordinates of all nodes in G' by n); shift G' downward by m steps (i.e., decrease the row coordinates of all nodes in G' by m); add the shifted graph G' (i.e., the second subgraph) to R;

[0124] Step 8: Return a list R of isomorphic subgraphs as output.

[0125] In this way, the symmetry of the grid structure of the quantum chip can be used to obtain the update range of the node coordinates of each first subgraph during the movement on the coupling graph, and through the coordinate update method, the subgraph matching in the secondary mapping of the quantum circuit can be efficiently realized, and all subgraphs that are isomorphic to the interaction graph can be searched.

[0126] Optionally, the step S104 specifically includes:

[0127] Obtain a second mapping scheme from the first logic quantum circuit to the quantum chip, and obtain a third mapping scheme corresponding to each subgraph in the subgraph set, respectively, wherein the third mapping scheme is a mapping scheme from the interaction graph to the quantum chip;

[0128] The second mapping scheme is associated with each of the third mapping schemes to obtain a subgraph set for each subgraph. Figure 1 A corresponding first mapping scheme.

[0129] In this implementation, by associating the mapping schemes of the two mappings, all feasible quantum circuit mapping schemes from the first logic quantum circuit to the quantum chip can be obtained, thereby achieving determination of feasible quantum circuit mapping schemes.

[0130] The specific process of quantum circuit mapping is as follows:

[0131] Input: the second logic quantum circuit C, the coupling graph P of the grid structure of the quantum processor;

[0132] Output: Optimal mapping of quantum circuit

[0133] Step 1: Select a local area of ​​the quantum processor with a grid structure;

[0134] Step 2: Use the quantum circuit compiler to precompile the input second logic quantum circuit C to the local area of ​​the selected quantum processor. The precompiled first logic quantum circuit is denoted as C′, and the quantum circuit mapping given by the precompilation is denoted as F pre ;

[0135] Step 3: Calculate the interaction graph G of the pre-compiled first logic quantum circuit C′;

[0136] Step 4: Using the grid structure of the coupling graph, find all subgraphs in the coupling graph P of the quantum processor that are isomorphic to the interaction graph G. Each subgraph G j Corresponding to a mapping from G to P, denoted by F j ;

[0137] Step 5: Map the precompiled quantum circuit to the mapping F from G to P j To associate, All feasible first mapping schemes from the first logic quantum circuit to the quantum chip are obtained, where A connection symbol for two maps.

[0138] Step 6: Map all quantum circuits based on the fidelity of the physical quantum gates on the quantum chip Conduct ratings;

[0139] Step 7: Output the optimal mapping of the quantum circuit with the highest score

[0140] The computational time complexity of the quantum chip mapping of this embodiment increases linearly with the number of quantum bits in the quantum chip. Compared with the computational time complexity of the quantum chip mapping in the related art, which increases exponentially or at least polynomially with the number of quantum bits in the quantum chip, its operating efficiency is significantly improved.

[0141] Optionally, the step S105 specifically includes:

[0142] Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip under each first mapping scheme;

[0143] A mapping scheme corresponding to a physical quantum circuit with the largest target fidelity is selected from the first mapping schemes corresponding to the subgraph set to obtain the target mapping scheme.

[0144] In this embodiment, by selecting the mapping scheme corresponding to the physical quantum circuit with the highest target fidelity from the first mapping scheme corresponding to the subgraph set, the symmetry of the grid chip structure can be used to efficiently search for feasible mappings of the quantum circuit, and the optimality of the quantum circuit mapping is guaranteed, thereby improving the fidelity of the quantum circuit.

[0145] In an optional implementation, the fidelity of each physical quantum gate under the first mapping scheme may be superimposed to obtain the fidelity of the physical quantum circuit.

[0146] Optionally, obtaining a target fidelity of mapping the first logical quantum circuit to a physical quantum circuit on the quantum chip under each first mapping scheme based on the fidelity of the physical quantum gate on the quantum chip includes:

[0147] Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the fidelity of the physical quantum gate of the logical quantum gate in the first logical quantum circuit under each first mapping scheme;

[0148] For each first mapping scheme, the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme is multiplied to obtain a target fidelity of the physical quantum circuit under the first mapping scheme.

[0149] In this implementation, by multiplying the fidelity of each physical quantum gate under the first mapping scheme, the target fidelity of the physical quantum circuit under the first mapping scheme is obtained, which can improve the fidelity accuracy and calculation speed of the quantum circuit.

[0150] Optionally, for each logical quantum gate, a mapping relationship of the logical quantum gate to a physical quantum gate under each first mapping scheme and the fidelity of the physical quantum gate are both stored and calculated in a vector form;

[0151] The step of multiplying the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme for each first mapping scheme to obtain a target fidelity of the physical quantum circuit under the first mapping scheme includes:

[0152] The first vectors corresponding to the logic quantum gates in the first logic quantum circuit are multiplied by corresponding elements at the same position to obtain a target vector, wherein the target vector includes the target fidelity of the physical quantum circuit under each of the first mapping schemes, and the first vector is a vector of the fidelity of the physical quantum gate of the logic quantum gate under each of the first mapping schemes.

[0153] After finding a set of feasible quantum circuit mappings, it is necessary to evaluate these mappings and select the circuit mapping that maximizes the quantum circuit fidelity (minimizes the error rate). In this embodiment, a scheme for efficiently estimating the quantum circuit fidelity is proposed, which is based on vectorized acceleration and can simultaneously calculate the quantum circuit fidelity corresponding to a large number of quantum circuit mappings. Among them, vectors are represented by bold symbols. The specific process is as follows:

[0154] Input: the first logical quantum circuit, a set of quantum circuit mappings L to be scored, and a mapping V from quantum gates to fidelity;

[0155] Output: The first logical quantum circuit is mapped to the quantum circuit fidelity estimate S of the quantum chip.

[0156] Step 1: Convert the first logical quantum circuit into a quantum gate sequence (i.e., a list of quantum operation instructions) C list ;

[0157] Step 2: The logical quantum gate g in the first logical quantum circuit j ∈C list To loop:

[0158] Step 2.1: Retrieve the logical quantum gate g j The corresponding physical quantum gate g under the mapping of all first mapping schemes i =L(g j ), where g i is a vector containing multiple quantum gate indices;

[0159] Step 2.2: Retrieve the fidelity F corresponding to the physical quantum gate j =V(g i );

[0160] Step 3: Calculate the quantum circuit fidelity S = ∏ corresponding to the quantum circuit mapping j F j ,∏ j F j is the vector F j The product of corresponding elements in the same position;

[0161] Step 4: Return the calculated quantum circuit fidelity S.

[0162] In this way, the fidelity of the quantum circuit can be efficiently estimated, thereby efficiently determining the optimal mapping scheme for the quantum circuit.

[0163] The quantum circuit mapping method of this embodiment is described in detail with a specific example as follows.

[0164] You can enter Figure 2The logical quantum circuit shown in Figure 1, each horizontal line represents a quantum bit, denoted by The symbols on the horizontal line represent quantum gates (i.e., logical operations), the symbols on the right side of the horizontal line represent measurements on quantum bits, and quantum gates spanning multiple lines represent dual-qubit gates.

[0165] This quantum circuit can be precompiled using related modules such as Qiskit. It can be seen that the interaction diagram of this quantum circuit can be directly adapted to the coupling diagram of the quantum chip. Therefore, the precompilation process does not change the connectivity of the logical qubits in the quantum circuit.

[0166] like Figure 3 As shown, the interaction graph of the input quantum circuit is a 3×3 grid graph. In it, each quantum bit in the input quantum circuit corresponds to a node in the graph, and each two-qubit gate in the quantum circuit corresponds to an edge between nodes in the graph.

[0167] By calculating the graph radius r=2 of the interaction graph, the second-order neighborhood of the coupling graph generation set of the quantum processor can be defined as the reduced search space, and the generation set is the four nodes at the center of the coupling graph, forming a four-node ring. Figure 4 This is a schematic diagram of the coupling diagram of an example quantum chip. Figure 4 As shown, each circular mark represents a node, that is, a physical quantum bit, and the edges between nodes represent the coupling connection between quantum bits. The nodes in the box 401 are a generation set of the coupling graph of the quantum chip, and the second-order neighborhood of the generation set is represented by the large circle 402. The subgraph formed by the nodes in the large circle 402 is defined as the reduced search space.

[0168] Figure 4 Each node in the grid represents a quantum bit, denoted by (i is a natural number), each edge connecting the nodes represents a coupler between quantum bits, which provides hardware support for two-qubit gate operations.

[0169] In the reduced search space, we search for a subgraph that is isomorphic to the above interaction graph, i.e., a 3×3 grid. There are 32 subgraph isomorphic mappings from the interaction graph to the quantum hardware coupling graph. For example, the following mapping. In which, the superscript L represents the logical bit, the superscript P represents the physical bit, and the subscript represents the number of the quantum bit, see Figure 2 and Figure 4 Number.

[0170]

[0171]

[0172]

[0173] For each isomorphic subgraph in the reduced search space, perform horizontal and vertical translation until it intersects with the boundary of the quantum processor coupling graph. In particular, consider the case where the quantum processor coupling graph is a 300×300 grid graph, and the processor contains 9×10 4 Through translation, 710,432 subgraphs that are isomorphic to the quantum circuit interaction graph can be found in the coupling graph.

[0174] In order to test the efficiency of the subgraph matching, numerical experiments were performed on a MacBook Pro 2020 (subsequent experiments were also based on this computing platform). Experiments show that by using the subgraph matching of this embodiment, the search for all isomorphic subgraphs can be completed within 5 seconds. In comparison, the VF2 algorithm can be used to solve the problem, which takes 357 seconds, while VF2++ takes 367 seconds. In other words, the scheme in this embodiment, by exploiting the symmetry of the grid structure, reduces the solution time of the subgraph matching problem (the core problem of secondary circuit mapping) by 98.6% compared to related schemes.

[0175] The isomorphic subgraphs searched during each subgraph matching process correspond to a feasible quantum circuit mapping. All these feasible circuit mappings need to be evaluated, and the mapping that maximizes the quantum circuit fidelity is selected as the output. To this end, a heuristic quantum circuit fidelity estimation function is used. This function multiplies the fidelity of all quantum gates in the quantum circuit as an estimate of the quantum circuit fidelity.

[0176] For example, suppose the quantum circuit mapping M is Figure 2 The 30 quantum gates contained in the quantum circuit Mapping to actual quantum gates on a quantum processor Further, suppose the fidelity of these actual quantum gates is F i P (i=1, 2, ..., 30) The quantum circuit mapping M is scored as follows according to the following formula (1).

[0177]

[0178] Using the vectorized accelerated circuit mapping scoring function, all searched quantum circuit mappings {M j}Perform this evaluation process to obtain the fidelity of all circuit mappings and store them in the form of a binary array S = {(M j ,Score(M j ))}.

[0179] For a 300×300 grid quantum chip and Figure 2Given the quantum circuit, as mentioned above, there are a total of 710432 feasible quantum circuit mappings. Using the vectorized circuit mapping scoring function, it takes a total of 4.6 seconds to score these feasible circuit mappings; as a comparison, using the serial circuit mapping scoring function, it takes 46.9 seconds. This means that the proposed vectorized circuit mapping scoring scheme reduces the running time by about 90% compared to the related schemes.

[0180] We can traverse all quantum circuit mappings in S and search for the mapping M with the highest score (i.e., the highest fidelity) opt :=argmax j Score(M j ) and returns it as the target mapping scheme.

[0181] In order to demonstrate the scalability of the quantum circuit mapping scheme of this embodiment, this scheme can be used to Figure 2 The quantum circuit in is mapped onto an l×l grid structure quantum chip. In this process, the running time required for subgraph matching, circuit mapping scoring and complete circuit mapping proposed in this embodiment is tested respectively, and compared with related solutions.

[0182] Figure 2 The interaction graph of the quantum circuit in is a 3×3 grid graph. Therefore, in the subgraph matching step, it is necessary to search for all isomorphic mappings from the grid graph to the quantum hardware coupling graph (i.e., an l×l grid graph). The efficient subgraph matching scheme based on the grid symmetry structure of this embodiment, the VF2 scheme, and the VF2++ scheme are used to complete this task. The corresponding running times are shown in Figure 5 .

[0183] Figure 5 The horizontal axis in the middle represents the number of quantum bits in the quantum chip N = l 2 The vertical axis represents the time required to complete the subgraph isomorphic mapping search. The three curves, namely curve 501, curve 502 and curve 503, respectively represent the running time of the efficient subgraph matching solution based on the grid symmetry structure, the VF2 solution and the VF2++ solution of this embodiment.

[0184] The circuit mappings corresponding to all isomorphic subgraphs found in the subgraph matching step are scored, that is, the corresponding quantum circuit fidelity is estimated. The running time of the circuit mapping scoring step is shown in Figure 6 , wherein the horizontal axis represents the number of quantum bits in the quantum chip, and the vertical axis represents the running time of the scoring function. The two curves in the figure, namely curve 601 and curve 602, respectively represent the running time required for the vectorized circuit mapping scoring function of this embodiment and other circuit mapping scoring functions to score all circuit mappings.

[0185] Considering the running time required for the complete circuit mapping scheme in this embodiment, the numerical experimental test is conducted for quantum chips of different sizes to find Figure 2 The running time required for the optimal mapping of the input quantum circuit shown. The quantum chip is set to an l×l grid structure quantum bit array, which is the same as the previous two numerical experiments. The experimental results are shown in Figure 7 .

[0186] Figure 7 The horizontal axis in the middle represents the number of quantum bits in the quantum chip N = l 2 , the vertical axis represents the running time of the quantum circuit mapping scheme, and the two curves in the figure, namely curve 701 and curve 702, respectively represent the efficient circuit mapping scheme based on the grid symmetry structure of this embodiment and other mapping schemes.

[0187] Figure 7 It shows that the time required for the quantum circuit mapping scheme of this embodiment to determine the optimal circuit mapping from a given quantum circuit to a quantum chip is significantly lower than that of other schemes. As the number of quantum bits in the quantum chip increases, the running time of other schemes increases significantly. Through linear extension, it can be estimated that the quantum circuit mapping scheme of this embodiment can complete the search for the optimal circuit mapping from a given quantum circuit to a large-scale quantum chip containing 1 million quantum bits in less than 1 minute. In comparison, other schemes take more than an hour to complete the task. This shows that the quantum circuit mapping scheme of this embodiment has a significant advantage in computational complexity compared to related schemes, and is particularly suitable for quantum circuit mapping of large-scale quantum chips.

[0188] Second embodiment

[0189] like Figure 8 As shown, the present disclosure provides a quantum circuit mapping device 800, comprising:

[0190] An acquisition module 801 is used to acquire a coupling diagram of the quantum chip based on arrangement structure information of quantum bits on the quantum chip; and to acquire an interaction diagram of a first logic quantum circuit precompiled onto the quantum chip, wherein the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in a grid structure;

[0191] A search module 802 is configured to search for a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, the reduced search space comprising a set of nodes in the coupling graph whose distance from a spanning set does not exceed a specified distance, the specified distance being greater than or equal to a radius of the interaction graph, the spanning set comprising at least one adjacent node in the coupling graph;

[0192] A translation operation module 803 is used to perform a translation operation on the first subgraph on the coupling graph by using the grid structure of the coupling graph to obtain a second subgraph isomorphic to the interaction graph;

[0193] The first determining module 804 is used to determine each subgraph in the subgraph set. Figure 1 a corresponding first mapping scheme, wherein the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph;

[0194] The second determination module 805 is used to determine a target mapping scheme from the first logical quantum circuit to the quantum chip from the first mapping scheme corresponding to the subgraph set based on the fidelity of the physical quantum gate on the quantum chip.

[0195] Optionally, the device further comprises:

[0196] A third determination module is used to determine the r-order neighborhood of the generated set, where r is the radius of the interaction graph;

[0197] The fourth determination module is used to determine the r-order neighborhood as the reduced search space of the coupling graph.

[0198] Optionally, the radius of the interaction graph is determined by:

[0199] Taking the node located in the central area of ​​the interaction graph as the target node, obtaining the maximum step length from the node in the interaction graph to the target node, and obtaining the target step length corresponding to the target node;

[0200] The step length with the shortest distance among the target step lengths corresponding to the target nodes in the central area is determined as the radius of the interaction graph.

[0201] Optionally, the generated set includes four nodes at the center of the coupling graph.

[0202] Optionally, the translation operation module 803 is specifically used to:

[0203] determining a width and a height of the coupling graph;

[0204] Based on the width and the node coordinates of the first subgraph, determine the number of steps required for the first subgraph to move horizontally to the boundary of the coupling graph in units of grids; and based on the height and the node coordinates of the first subgraph, determine the number of steps required for the first subgraph to move vertically to the boundary of the coupling graph in units of grids;

[0205] Based on the number of steps required to move horizontally and vertically to the boundary of the coupling graph, construct an update range of the node coordinates of the first subgraph during the movement on the coupling graph;

[0206] Based on the update range, the node coordinates of the first subgraph are updated to obtain a second subgraph isomorphic to the interaction graph.

[0207] Optionally, the first determining module 804 is specifically configured to:

[0208] Obtain a second mapping scheme from the first logic quantum circuit to the quantum chip, and obtain a third mapping scheme corresponding to each subgraph in the subgraph set, respectively, wherein the third mapping scheme is a mapping scheme from the interaction graph to the quantum chip;

[0209] The second mapping scheme is associated with each of the third mapping schemes to obtain a subgraph set for each subgraph. Figure 1 A corresponding first mapping scheme.

[0210] Optionally, the second determining module 805 includes:

[0211] A second acquisition unit is used to acquire, based on the fidelity of the physical quantum gate on the quantum chip, the target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip under each first mapping scheme;

[0212] A selection unit is used to select a mapping scheme corresponding to a physical quantum circuit with the largest target fidelity from the first mapping schemes corresponding to the subgraph set to obtain the target mapping scheme.

[0213] Optionally, the second acquiring unit is specifically configured to:

[0214] Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the fidelity of the physical quantum gate of the logical quantum gate in the first logical quantum circuit under each first mapping scheme;

[0215] For each first mapping scheme, the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme is multiplied to obtain a target fidelity of the physical quantum circuit under the first mapping scheme.

[0216] Optionally, for each logical quantum gate, a mapping relationship of the logical quantum gate to a physical quantum gate under each first mapping scheme and the fidelity of the physical quantum gate are both stored and calculated in a vector form;

[0217] The second acquisition unit is specifically used to:

[0218] The first vectors corresponding to the logic quantum gates in the first logic quantum circuit are multiplied by corresponding elements at the same position to obtain a target vector, wherein the target vector includes the target fidelity of the physical quantum circuit under each of the first mapping schemes, and the first vector is a vector of the fidelity of the physical quantum gate of the logic quantum gate under each of the first mapping schemes.

[0219] Optionally, the acquisition module 801 is specifically used to:

[0220] Selecting a local area in the area range of the quantum chip, wherein the number of physical quantum bits deployed in the local area is greater than or equal to the number of logical quantum bits of the second logical quantum circuit;

[0221] The second logic quantum circuit is precompiled onto the local region to obtain an interaction graph of the first logic quantum circuit.

[0222] The quantum circuit mapping device 800 provided in the present disclosure can implement each process implemented by the quantum circuit mapping method embodiment and can achieve the same beneficial effects. To avoid repetition, it will not be described here.

[0223] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0224] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0225] Fig. 9 A schematic block diagram of an example electronic device that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0226] like Fig. 9As shown, the device 900 includes a computing unit 901, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 902 or a computer program loaded from a storage unit 908 into a random access memory (RAM) 903. In the RAM 903, various programs and data required for the operation of the device 900 can also be stored. The computing unit 901, the ROM 902, and the RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0227] A number of components in the device 900 are connected to the I / O interface 905, including: an input unit 906, such as a keyboard, a mouse, etc.; an output unit 907, such as various types of displays, speakers, etc.; a storage unit 908, such as a disk, an optical disk, etc.; and a communication unit 909, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 909 allows the device 900 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0228] The computing unit 901 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 901 performs the various methods and processes described above, such as the quantum circuit mapping method. For example, in some embodiments, the quantum circuit mapping method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 900 via the ROM 902 and / or the communication unit 909. When the computer program is loaded into the RAM 903 and executed by the computing unit 901, one or more steps of the quantum circuit mapping method described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform the quantum circuit mapping method by any other appropriate means (e.g., by means of firmware).

[0229] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0230] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0231] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0232] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0233] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0234] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0235] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0236] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A quantum circuit mapping method, comprising: Based on the arrangement structure information of quantum bits on the quantum chip, the coupling diagram of the quantum chip is obtained; and obtaining an interaction diagram of a first logic quantum circuit precompiled onto the quantum chip, wherein the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in a grid structure; Searching for a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, the reduced search space comprising a set of nodes in the coupling graph whose distances from a spanning set do not exceed a specified distance, the specified distance being greater than or equal to a radius of the interaction graph, the spanning set comprising at least one adjacent node in the coupling graph; the spanning set comprising four nodes at the center of the coupling graph; Using the grid structure of the coupling graph, performing a translation operation on the first subgraph on the coupling graph to obtain a second subgraph isomorphic to the interaction graph; Determine a first mapping scheme that corresponds one-to-one to each subgraph in a subgraph set, where the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph; Based on the fidelity of the physical quantum gate on the quantum chip, determine a target mapping scheme from the first logical quantum circuit to the quantum chip from the first mapping scheme corresponding to the subgraph set; Utilizing the grid structure of the coupling graph, performing a translation operation on the first subgraph on the coupling graph to obtain a second subgraph isomorphic to the interaction graph includes: for each first subgraph, utilizing the symmetry of the grid structure of the coupling graph of the quantum chip, simulating the movement of the first subgraph to various positions of the coupling graph by translation, and determining the node coordinates of the subgraph after the movement based on the number of translation steps to obtain the second subgraph.

2. The method according to claim 1, before searching the first subgraph isomorphic to the interaction graph in the reduced search space of the coupling graph, further comprising: Determining an r-order neighborhood of the generated set, where r is the radius of the interaction graph; The r-order neighborhood is determined as a reduced search space of the coupling graph.

3. The method according to claim 1, wherein: The radius of the interaction map is determined by: Taking the node located in the central area of ​​the interaction graph as the target node, obtaining the maximum step length from the node in the interaction graph to the target node, and obtaining the target step length corresponding to the target node; The step length with the shortest distance among the target step lengths corresponding to the target nodes in the central area is determined as the radius of the interaction graph.

4. The method according to claim 1, wherein: The method of utilizing the grid structure of the coupling graph to perform a translation operation on the first subgraph on the coupling graph to obtain a second subgraph isomorphic to the interaction graph includes: determining a width and a height of the coupling graph; Based on the width and the node coordinates of the first subgraph, determine the number of steps required for the first subgraph to move horizontally to the boundary of the coupling graph in units of grids; and based on the height and the node coordinates of the first subgraph, determine the number of steps required for the first subgraph to move vertically to the boundary of the coupling graph in units of grids; Based on the number of steps required to move horizontally and vertically to the boundary of the coupling graph, construct an update range of the node coordinates of the first subgraph during the movement on the coupling graph; Based on the update range, the node coordinates of the first subgraph are updated to obtain a second subgraph isomorphic to the interaction graph.

5. The method according to claim 1, wherein: The determining of a first mapping scheme in which each subgraph in the subgraph set corresponds to each other includes: Obtain a second mapping scheme from the first logic quantum circuit to the quantum chip, and obtain a third mapping scheme corresponding to each subgraph in the subgraph set, respectively, wherein the third mapping scheme is a mapping scheme from the interaction graph to the quantum chip; The second mapping scheme is associated with each of the third mapping schemes to obtain a first mapping scheme corresponding to each subgraph in the subgraph set.

6. The method according to claim 1, wherein: The step of determining a target mapping scheme from the first logical quantum circuit to the quantum chip from a first mapping scheme corresponding to the subgraph set based on the fidelity of the physical quantum gate on the quantum chip comprises: Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip under each first mapping scheme; A mapping scheme corresponding to a physical quantum circuit with the largest target fidelity is selected from the first mapping schemes corresponding to the subgraph set to obtain the target mapping scheme.

7. The method according to claim 6, wherein: The obtaining, based on the fidelity of the physical quantum gate on the quantum chip, a target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip under each first mapping scheme comprises: Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the fidelity of the physical quantum gate of the logical quantum gate in the first logical quantum circuit under each first mapping scheme; For each first mapping scheme, the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme is multiplied to obtain a target fidelity of the physical quantum circuit under the first mapping scheme.

8. The method according to claim 7, wherein: For each logical quantum gate, the mapping relationship of the logical quantum gate to the physical quantum gate under each first mapping scheme and the fidelity of the physical quantum gate are stored and calculated in vector form; The step of multiplying the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme for each first mapping scheme to obtain a target fidelity of the physical quantum circuit under the first mapping scheme includes: The first vectors corresponding to the logic quantum gates in the first logic quantum circuit are multiplied by corresponding elements at the same position to obtain a target vector, wherein the target vector includes the target fidelity of the physical quantum circuit under each of the first mapping schemes, and the first vector is a vector of the fidelity of the physical quantum gate of the logic quantum gate under each of the first mapping schemes.

9. The method according to claim 1, wherein: The obtaining of the interaction graph of the first logic quantum circuit precompiled onto the quantum chip comprises: Selecting a local area in the area range of the quantum chip, wherein the number of physical quantum bits deployed in the local area is greater than or equal to the number of logical quantum bits of the second logical quantum circuit; The second logic quantum circuit is precompiled onto the local region to obtain an interaction graph of the first logic quantum circuit.

10. A quantum circuit mapping device, comprising: An acquisition module, used to acquire a coupling diagram of the quantum chip based on the arrangement structure information of the quantum bits on the quantum chip; and obtaining an interaction diagram of a first logic quantum circuit precompiled onto the quantum chip, wherein the arrangement structure information indicates that the quantum bits on the quantum chip are arranged in a grid structure; A search module, configured to search a first subgraph isomorphic to the interaction graph in a reduced search space of the coupling graph, the reduced search space comprising a set of nodes in the coupling graph whose distance from a generation set does not exceed a specified distance, the specified distance being greater than or equal to a radius of the interaction graph, the generation set comprising at least one adjacent node in the coupling graph; the generation set comprising four nodes at the center of the coupling graph; A translation operation module, used to perform a translation operation on the first subgraph on the coupling graph by using the grid structure of the coupling graph, so as to obtain a second subgraph isomorphic to the interaction graph; A first determining module is used to determine a first mapping scheme corresponding one-to-one to each subgraph in a subgraph set, wherein the first mapping scheme is a mapping scheme from the first logic quantum circuit to the quantum chip, and the subgraph set includes the first subgraph and the second subgraph; A second determination module is used to determine a target mapping scheme from the first logic quantum circuit to the quantum chip from the first mapping scheme corresponding to the subgraph set based on the fidelity of the physical quantum gate on the quantum chip; The translation operation module is specifically used to utilize the grid structure of the coupling graph to perform a translation operation on the first subgraph on the coupling graph to obtain a second subgraph isomorphic to the interaction graph, including: for each first subgraph, utilizing the symmetry of the grid structure of the coupling graph of the quantum chip, simulating the movement of the first subgraph to various positions of the coupling graph by translation, and determining the node coordinates of the subgraph after the movement based on the number of translation steps to obtain the second subgraph.

11. The apparatus according to claim 10, further comprising: A third determination module is used to determine the r-order neighborhood of the generated set, where r is the radius of the interaction graph; The fourth determination module is used to determine the r-order neighborhood as the reduced search space of the coupling graph.

12. The device according to claim 10, wherein: The radius of the interaction map is determined by: Taking the node located in the central area of ​​the interaction graph as the target node, obtaining the maximum step length from the node in the interaction graph to the target node, and obtaining the target step length corresponding to the target node; The step length with the shortest distance among the target step lengths corresponding to the target nodes in the central area is determined as the radius of the interaction graph.

13. The device according to claim 10, wherein: The translation operation module is specifically used for: determining a width and a height of the coupling graph; Based on the width and the node coordinates of the first subgraph, determining the number of steps required for the first subgraph to be horizontally moved to the boundary of the coupling graph in units of grids; and determining, based on the height and the node coordinates of the first subgraph, the number of steps required for the first subgraph to vertically move to the boundary of the coupling graph in units of grids; Based on the number of steps required to move horizontally and vertically to the boundary of the coupling graph, construct an update range of the node coordinates of the first subgraph during the movement on the coupling graph; Based on the update range, the node coordinates of the first subgraph are updated to obtain a second subgraph isomorphic to the interaction graph.

14. The device according to claim 10, wherein: The first determining module is specifically configured to: Obtain a second mapping scheme from the first logic quantum circuit to the quantum chip, and obtain a third mapping scheme corresponding to each subgraph in the subgraph set, respectively, wherein the third mapping scheme is a mapping scheme from the interaction graph to the quantum chip; The second mapping scheme is associated with each of the third mapping schemes to obtain a first mapping scheme corresponding to each subgraph in the subgraph set.

15. The device according to claim 10, wherein: The second determining module comprises: A fidelity acquisition unit, configured to acquire, based on the fidelity of the physical quantum gate on the quantum chip, a target fidelity of mapping the first logical quantum circuit to the physical quantum circuit on the quantum chip under each first mapping scheme; A selection unit is used to select a mapping scheme corresponding to a physical quantum circuit with the largest target fidelity from the first mapping schemes corresponding to the subgraph set to obtain the target mapping scheme.

16. The device according to claim 15, wherein: The fidelity acquisition unit is specifically used for: Based on the fidelity of the physical quantum gate on the quantum chip, obtaining the fidelity of the physical quantum gate of the logical quantum gate in the first logical quantum circuit under each first mapping scheme; For each first mapping scheme, the fidelity of each physical quantum gate corresponding to the first logical quantum circuit under the first mapping scheme is multiplied to obtain a target fidelity of the physical quantum circuit under the first mapping scheme.

17. The device according to claim 16, wherein: For each logical quantum gate, the mapping relationship of the logical quantum gate to the physical quantum gate under each first mapping scheme and the fidelity of the physical quantum gate are stored and calculated in vector form; The fidelity acquisition unit is specifically used for: The first vectors corresponding to the logic quantum gates in the first logic quantum circuit are multiplied by corresponding elements at the same position to obtain a target vector, wherein the target vector includes the target fidelity of the physical quantum circuit under each of the first mapping schemes, and the first vector is a vector of the fidelity of the physical quantum gate of the logic quantum gate under each of the first mapping schemes.

18. The device according to claim 10, wherein: The acquisition module is specifically used for: Selecting a local area in the area range of the quantum chip, wherein the number of physical quantum bits deployed in the local area is greater than or equal to the number of logical quantum bits of the second logical quantum circuit; The second logic quantum circuit is precompiled onto the local region to obtain an interaction graph of the first logic quantum circuit.

19. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 9.

20. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-9.

21. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 9.

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