Gate driving circuit and display panel

Abstract

The application provides a gate drive circuit and a display panel. The gate drive circuit comprises a pull-up control module, a first pull-up output module, a second pull-up output module and a random row selection module. The pull-up control module raises the potential of a first node according to a pull-up control signal. The first pull-up output module outputs a first clock signal transmitted by a plurality of first clock signal lines to a plurality of first output ends according to the potential of the first node, and the plurality of first output ends output a plurality of scanning signals. The second pull-up output module outputs a second clock signal transmitted by a second clock signal line to a stage transmission output end according to the potential of the first node. The random row selection module raises the potential of the first node and lowers the potential of a second node in a blanking stage according to a row selection control signal, a reset signal and the pull-up control signal. In a first stage in which a second active pulse of the second clock signal is output to the stage transmission output end, a first active pulse of the plurality of first clock signals is output to the plurality of first output ends.

Description

Technical Field

[0001] This invention relates to the field of display technology, specifically to a gate driving circuit and a display panel. Background Technology

[0002] When using a 3T1C (3 transistors and 1 capacitor) pixel driving circuit to achieve real-time mobility detection and compensation line by line sequentially, uneven linearity in the displayed image will occur, affecting the display quality. Using random line selection for mobility detection and compensation, by outputting a random line mobility detection control signal within the blanking interval of each frame, can achieve random line selection and mobility detection compensation. However, the start or end times of the effective pulses of adjacent scan signals differ significantly, still causing uneven display. Summary of the Invention

[0003] The present invention provides a gate driving circuit and a display panel, which can improve the problem of uneven display caused by large differences in the start or end times of the effective pulses of adjacent scanning signals.

[0004] This invention provides a gate driving circuit, including a pull-up control module, a first pull-up output module, a second pull-up output module, and a random selection module. The pull-up control module is electrically connected to a first node and configured to output a preset voltage to the first node according to a pull-up control signal, thereby raising the potential of the first node. The first pull-up output module is electrically connected to the first node, multiple first clock signal lines, and multiple first output terminals of the gate driving circuit, and is configured to output multiple first clock signals transmitted by the multiple first clock signal lines to the multiple first output terminals according to the potential of the first node. The multiple first output terminals are configured to output multi-level scanning signals. The second pull-up output module is electrically connected to the first node, second clock signal lines, and a stage transmission output terminal of the gate driving circuit, and is configured to output a second clock signal transmitted by the second clock signal lines to the stage transmission output terminal according to the potential of the first node. The random row selection module is electrically connected to the first node and the second node, and is configured to output the preset voltage to the first node and output the first voltage output from the first power supply terminal to the second node during the blanking phase, based on the row selection control signal, the reset signal, and the pull-up control signal, to raise the potential of the first node and lower the potential of the second node. Specifically, during the first phase when the second valid pulse of the second clock signal is output to the stage transmission output terminal, multiple first valid pulses of the first clock signal are output to multiple first output terminals; during the first phase, the start times of the multiple first valid pulses are all delayed compared to the start times of the second valid pulses, and the end times of the multiple first valid pulses are all advanced compared to the end times of the second valid pulses.

[0005] The present invention also provides a display panel including any of the above-described gate driving circuits.

[0006] This invention provides a gate driving circuit and a display panel. The gate driving circuit includes a pull-up control module, a first pull-up output module, a second pull-up output module, and a random row selection module. The pull-up control module is configured to raise the potential of a first node according to a pull-up control signal. The first pull-up output module is configured to output multiple first clock signals transmitted from multiple first clock signal lines to multiple first output terminals according to the potential of the first node, and the multiple first output terminals are configured to output multi-level scanning signals. The second pull-up output module is configured to output a second clock signal transmitted from a second clock signal line to a stage transmission output terminal according to the potential of the first node. The random row selection module is configured to raise the potential of the first node and pull down the potential of the second node during the blanking phase according to a row selection control signal, a reset signal, and a pull-up control signal. Specifically, during the first phase when the second valid pulse of the second clock signal is output to the stage transmission output terminal, the first valid pulses of multiple first clock signals are output to multiple first output terminals to improve the problem of uneven display of the display screen including the gate driving circuit caused by large differences in the start or end times of the valid pulses of adjacent scanning signals. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of the gate driving circuit provided in an embodiment of the present invention;

[0009] Figures 2A to 2C This is a timing diagram provided in an embodiment of the present invention. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0011] Specifically, such as Figure 1 This is a schematic diagram of the gate driving circuit provided in an embodiment of the present invention. The present invention provides a gate driving circuit including a pull-up control module 100, a first pull-up output module 201, a second pull-up output module 202, and a random row selection module 300.

[0012] The pull-up control module 100 is electrically connected to the first node Q(n) and is configured to output a preset voltage VGH to the first node Q(n) according to the pull-up control signal Count(ny), so as to raise the potential of the first node Q(n). Wherein, y≥1.

[0013] Optionally, the pull-up control module 100 includes a first pull-up control transistor T11, a second pull-up control transistor T12, a third pull-up control transistor T13, and a fourth pull-up control transistor T14.

[0014] The gates of the first pull-up control transistor T11 and the second pull-up control transistor T12 are both configured to receive the pull-up control signal Count(ny). The gates of the third pull-up control transistor T13 and the fourth pull-up control transistor T14 are both configured to receive the preset voltage VGH. One of the source and drain of the first pull-up control transistor T11 and one of the source and drain of the third pull-up control transistor T13 are both configured to receive the preset voltage VGH. The source and drain of the second pull-up control transistor T12 are electrically connected between the other of the source and drain of the first pull-up control transistor T11 and the first node Q(n). The source and drain of the fourth pull-up control transistor T14 are electrically connected between the other of the source and drain of the third pull-up control transistor T13 and the other of the source and drain of the first pull-up control transistor T11.

[0015] The first pull-up output module 201 is electrically connected to the first node Q(n), multiple first clock signal lines CKb, and multiple first output terminals of the gate drive circuit. It is configured to output multiple first clock signals CKB transmitted by the multiple first clock signal lines CKb to multiple first output terminals according to the potential of the first node Q(n). The multiple first output terminals are configured to output multi-level scan signals.

[0016] Optionally, the first pull-up output module 201 includes a first pull-up output unit, a second pull-up output unit, a third pull-up output unit, and a fourth pull-up output unit.

[0017] Optionally, the first pull-up output unit includes a first pull-up transistor T21 and a first capacitor C1. The gate of the first pull-up transistor T21 is electrically connected to the first node Q(n). The source and drain of the first pull-up transistor T21 are electrically connected between the first sub-clock signal line CKb1 and the first sub-output terminal WR(n). The first capacitor C1 is connected in series between the first node Q(n) and the first sub-output terminal WR(n). The plurality of first output terminals include the first sub-output terminal WR(n) configured to output the nth level scan signal, where n≥1. The plurality of first clock signal lines CKb include the first sub-clock signal line CKb1. The first sub-clock signal line CKb1 outputs a first sub-valid pulse corresponding to the first duration ti1 in the first stage.

[0018] Optionally, the second pull-up output unit includes a second pull-up transistor T22 and a second capacitor C2. The gate of the second pull-up transistor T22 is electrically connected to the first node Q(n). The source and drain of the second pull-up transistor T22 are electrically connected between the second sub-clock signal line CKb2 and the second sub-output terminal WR(n+1). The second capacitor C2 is connected in series between the first node Q(n) and the second sub-output terminal WR(n+1). The plurality of first output terminals include the second sub-output terminal WR(n+1) configured to output the (n+1)th level scan signal. The plurality of first clock signal lines CKb include the second sub-clock signal line CKb2. The second sub-clock signal line CKb2 outputs a second sub-valid pulse corresponding to the second duration ti2 during the first stage.

[0019] Optionally, the third pull-up output unit includes a third pull-up transistor T23 and a third capacitor C3. The gate of the third pull-up transistor T23 is electrically connected to the first node Q(n). The source and drain of the third pull-up transistor T23 are electrically connected between the third sub-clock signal line CKb3 and the third sub-output terminal WR(n+2). The third capacitor C3 is connected in series between the first node Q(n) and the third sub-output terminal WR(n+2). The plurality of first output terminals include the third sub-output terminal WR(n+2) configured to output the (n+2)th level scan signal. The plurality of first clock signal lines CKb include the third sub-clock signal line CKb3. The third sub-clock signal line CKb3 outputs a third sub-valid pulse corresponding to the third duration ti3 during the first stage.

[0020] Optionally, the fourth pull-up output unit includes a fourth pull-up transistor T24 and a fourth capacitor C4. The gate of the fourth pull-up transistor T24 is electrically connected to the first node Q(n). The source and drain of the fourth pull-up transistor T24 are electrically connected between the fourth sub-clock signal line CKb4 and the fourth sub-output terminal WR(n+3). The fourth capacitor C4 is connected in series between the first node Q(n) and the fourth sub-output terminal WR(n+3). The plurality of first output terminals include the fourth sub-output terminal WR(n+3) configured to output the (n+3)th level scan signal. The plurality of first clock signal lines CKb include the fourth sub-clock signal line CKb4. The fourth sub-clock signal line CKb4 outputs a fourth sub-valid pulse corresponding to the fourth duration ti4 during the first stage.

[0021] The first valid pulse of the plurality of first clock signals CKB includes the first sub-valid pulse, the second sub-valid pulse, the third sub-valid pulse, and the fourth sub-valid pulse.

[0022] The second pull-up output module 202 is electrically connected to the first node Q(n), the second clock signal line CKa, and the stage transmission output terminal Cout(n) of the gate drive circuit, and is configured to output the second clock signal CKA transmitted by the second clock signal line CKa to the stage transmission output terminal Cout(n) according to the potential of the first node Q(n).

[0023] Optionally, the second pull-up output module 202 includes a stage output transistor T25 and a fifth capacitor C5. The gate of the stage output transistor T25 is electrically connected to the first node Q(n), and the source and drain of the stage output transistor T25 are electrically connected between the second clock signal line CKa and the stage output terminal Cout(n); the fifth capacitor C5 is connected in series between the first node Q(n) and the stage output terminal Cout(n).

[0024] The random row selection module 300 is electrically connected to the first node Q(n) and the second node QB(n), and is configured to output the preset voltage VGH to the first node Q(n) and output the first voltage output from the first power supply terminal VGL1 to the second node QB(n) during the blanking phase according to the row selection control signal LSP, the reset signal Reset and the pull-up control signal Count(ny), so as to raise the potential of the first node Q(n) and pull down the potential of the second node QB(n).

[0025] Optionally, the random selection module 300 includes a first selection control transistor T31, a second selection control transistor T32, a third selection control transistor T33, a fourth selection control transistor T34, a fifth selection control transistor T35, a sixth selection control transistor T36, a seventh selection control transistor T37, and a sixth capacitor C6.

[0026] The gates of the first control transistor T31 and the second control transistor T32 are configured to receive the row selection control signal LSP. The gates of the third control transistor T33, the fourth control transistor T34, and the sixth control transistor T36 are electrically connected to one of the source and drain of the second control transistor T32. The gate of the fifth control transistor T35 is configured to receive the reset signal VST, and the gate of the seventh control transistor T37 is configured to receive the reset signal Reset. One of the source and drain of the first selection transistor T31 is configured to receive the pull-up control signal Count(ny); one of the source and drain of the third selection transistor T33 and one of the source and drain of the fourth selection transistor T34 are configured to receive the preset voltage VGH; one of the source and drain of the sixth selection transistor T36 is configured to receive the first voltage; the other of the source and drain of the second selection transistor T32 and the other of the source and drain of the third selection transistor T33 are connected to the first selection transistor T36. The source and drain of the fifth control transistor T31 are electrically connected; the source and drain of the fifth control transistor T35 are electrically connected between the other of the source and drain of the fourth control transistor T34 and the first node Q(n); the source and drain of the seventh control transistor T37 are electrically connected between the other of the source and drain of the sixth control transistor T36 and the second node QB(n); and the sixth capacitor C6 is connected in series between the gate of the fourth control transistor T34 and one of the source and drain of the fourth control transistor T34.

[0027] By reusing the first node Q(n), the second node QB(n), the pull-up control module 100, and the random row selection module 300, and by including multiple pull-up output units in the pull-up output module, the gate drive circuit can realize the output of multi-level scanning signals, and can also realize the mobility detection and compensation of random row selection. This is beneficial to reducing the number of transistors included in the gate drive circuit, and is beneficial to realizing a narrow bezel design for the display panel using the gate drive circuit.

[0028] The inventors of this invention discovered through research that during the normal driving phase (such as the phase preceding the blanking phase within a frame duration when the gate driving circuit is applied to a display panel), the duration of the second effective pulse of the second clock signal CKA and the duration of the first effective pulse of the first clock signal CKB affect the difference in rising edge time, falling edge time, and the output capability of the mobility detection waveform of the effective pulses of adjacent scan signals. Therefore, to improve the problem of uneven display caused by large differences in the start and end times of the effective pulses of adjacent scan signals, the first effective pulses of multiple first clock signals CKB can be output to multiple first output terminals during the first phase when the second effective pulse of the second clock signal CKA is output to the stage transmission output terminal Cout(n).

[0029] Optionally, in the first stage, the start times of the plurality of first effective pulses are all delayed after the start time of the second effective pulse, and the end times of the plurality of first effective pulses are all advanced before the end time of the second effective pulse, so that the action times of the plurality of first effective pulses are all within the action times of the second effective pulse, and the start time of the second effective pulse is different from the start time of the plurality of first effective pulses, and the end time of the second effective pulse is different from the end time of the plurality of first effective pulses, so as to improve the effect of mitigating the problem of uneven display on the display panel caused by the large difference in the start and end times of the effective pulses of adjacent scanning signals.

[0030] Specifically, such as Figures 2A to 2CThis is a timing diagram provided in an embodiment of the present invention. Taking the first sub-clock signal transmitted by the first sub-clock signal line CKb1 as CKB1, the second sub-clock signal transmitted by the second sub-clock signal line CKb2 as CKB2, the third sub-clock signal transmitted by the third sub-clock signal line CKb3 as CKB3, the fourth sub-clock signal transmitted by the fourth sub-clock signal line CKb4 as CKB4, and the second clock signal transmitted by the second clock signal line CKa as CKA1 as an example. Within the first stage t13, the start time ST1 of the first sub-valid pulse output by the first sub-clock signal line CKb1, the start time ST2 of the second sub-valid pulse output by the second sub-clock signal line CKb2, the start time ST3 of the third sub-valid pulse output by the third sub-clock signal line CKb3, and the start time ST4 of the fourth sub-valid pulse output by the fourth sub-clock signal line CKb4 are all delayed by the start time ST5 of the second valid pulse of the second clock signal CKA1; within the first stage t13, the end time ET1 of the first sub-valid pulse output by the first sub-clock signal line CKb1, the end time ET2 of the second sub-valid pulse output by the second sub-clock signal line CKb2, the end time ET3 of the third sub-valid pulse output by the third sub-clock signal line CKb3, and the end time ET4 of the fourth sub-valid pulse output by the fourth sub-clock signal line CKb4 are all advanced by the end time ET5 of the second valid pulse of the second clock signal CKA1, such as... Figure 2A As shown.

[0031] Optionally, the first duration ti1 is equal to the second duration ti2, the second duration ti2 is equal to the third duration ti3, and the third duration ti3 is equal to the fourth duration ti4, so as to further reduce the difference between the start times of the effective pulses of adjacent scan signals and the difference between the end times of the effective pulses of adjacent scan signals.

[0032] Optionally, the fifth duration ti5 corresponding to the second effective pulse output by the second clock signal line CKa during the first stage can be greater than or equal to the sum of the durations corresponding to the first effective pulses output by multiple first clock signal lines CKa during the first stage. Optionally, the fifth duration ti5 can be greater than or equal to the sum of the first duration ti1, the second duration ti2, the third duration ti3, and the fourth duration ti4, so that the action times of multiple first effective pulses are all within the action times of the second effective pulses.

[0033] Optionally, to improve the output efficiency of the scanning signal, the action times of multiple first effective pulses may partially overlap. Optionally, the fifth duration ti5 may be greater than, less than, or equal to the sum of the first duration ti1, the second duration ti2, the third duration ti3, and the fourth duration ti4. Optionally, the fifth duration ti5 may be less than or equal to the difference between the sum of the first duration ti1 to the fourth duration ti4 and a unit duration.

[0034] Optionally, the second clock signal line CKa outputs a second valid pulse corresponding to a fifth duration ti5 during the first stage. The fifth duration ti5 is equal to 7 times the unit duration, and the first duration ti1, the second duration ti2, the third duration ti3, and the fourth duration ti4 are all twice the unit duration. That is, t5 = 7H, t1 = t2 = t3 = t4 = 2H. It is understood that the unit duration can be set according to actual needs.

[0035] Optionally, the gate drive circuit further includes a first pull-down output module 401 and a second pull-down output module 402.

[0036] The first pull-down output module 401 includes a first pull-down output transistor T41, a second pull-down output transistor T42, a third pull-down output transistor T43, and a fourth pull-down output transistor T44. The gates of the first pull-down output transistor T41, the second pull-down output transistor T42, the third pull-down output transistor T43, and the fourth pull-down output transistor T44 are all electrically connected to the second node QB(n). The source and drain of the first pull-down output transistor T41 are electrically connected between the second power supply terminal VGL2 and the first sub-output terminal WR(n). The source and drain of the second pull-down output transistor T42 are electrically connected between the second power supply terminal VGL2 and the second sub-output terminal WR(n+1). The source and drain of the third pull-down output transistor T43 are electrically connected between the second power supply terminal VGL2 and the third sub-output terminal WR(n+2). The source and drain of the fourth pull-down output transistor T44 are electrically connected between the second power supply terminal VGL2 and the fourth sub-output terminal WR(n+3).

[0037] The second pull-down output module 402 includes a fifth pull-down output transistor T45. The gate of the fifth pull-down output transistor T45 is electrically connected to the second node QB(n). The source and drain of the fifth pull-down output transistor T45 are electrically connected between the first power supply terminal VGL1 and the stage transmission output terminal Cout(n).

[0038] Optionally, the gate drive circuit further includes a pull-down control module 500. The pull-down control module 500 includes a first pull-down control transistor T51, a second pull-down control transistor T52, a third pull-down control transistor T53, a fourth pull-down control transistor T54, a fifth pull-down control transistor T55, and a sixth pull-down control transistor T56.

[0039] The gates of the first pull-down control transistor T51 and the second pull-down control transistor T52 are both configured to receive the pull-down control signal Count(n+y), the gates of the third pull-down control transistor T53 and the fourth pull-down control transistor T54 are both electrically connected to the second node QB(n), and the gates of the fifth pull-down control transistor T55 and the sixth pull-down control transistor T56 are both configured to receive the reset signal VST. The source and drain of the first pull-down control transistor T51 are electrically connected between one of the source and drain of the second pull-down control transistor T52 and the first power supply terminal VGL1, and the other of the source and drain of the second pull-down control transistor T52 is electrically connected to the first node Q(n); the source and drain of the third pull-down control transistor T53 are electrically connected between one of the source and drain of the fourth pull-down control transistor T54 and the first power supply terminal VGL1, and the other of the source and drain of the fourth pull-down control transistor T54 is electrically connected to the first node Q(n); the source and drain of the fifth pull-down control transistor T55 are electrically connected between one of the source and drain of the sixth pull-down control transistor T56 and the first power supply terminal VGL1, and the other of the source and drain of the sixth pull-down control transistor T56 is electrically connected to the first node Q(n).

[0040] Optionally, the first pull-down control transistor T51 is electrically connected to one of the source and drain of the second pull-down control transistor T52 through a third node N(n), and the third pull-down control transistor T53 is electrically connected to one of the source and drain of the fourth pull-down control transistor T54 through a fourth node N1(n).

[0041] The gate drive circuit further includes a leakage protection module 600, which includes a first leakage protection transistor T61 and a second leakage protection transistor T62. The gates of both the first and second leakage protection transistors T61 and T62 are electrically connected to the first node Q(n). One of the source and drain of the first leakage protection transistor T61 is configured to receive the preset voltage VGH. The other of the source and drain of the first leakage protection transistor T61 is electrically connected to one of the source and drain of the second leakage protection transistor T62. The other of the source and drain of the second leakage protection transistor T62 is configured to be electrically connected to the third node N(n) and the fourth node N1(n).

[0042] Optionally, the gate drive circuit further includes a pull-down sustaining module 700, which includes a first pull-down sustaining transistor T71, a second pull-down sustaining transistor T72, a third pull-down sustaining transistor T73, a fourth pull-down sustaining transistor T74, a fifth pull-down sustaining transistor T75, and a sixth pull-down sustaining transistor T76.

[0043] The gates of the first pull-down sustaining transistor T71 and the second pull-down sustaining transistor T72 are configured to receive a low-frequency clock signal LC1, and the gate of the sixth pull-down sustaining transistor T76 is configured to receive the pull-up control signal Count(ny). One of the source and drain of the first pull-down sustaining transistor T71 and one of the source and drain of the third pull-down sustaining transistor T73 are configured to receive the low-frequency clock signal LC1. The source and drain of the second pull-down sustaining transistor T72 are electrically connected between the other of the source and drain of the first pull-down sustaining transistor T71 and the gate of the third pull-down sustaining transistor T73. The source and drain of transistor T73 are electrically connected to the second node QB(n). The gates of the fourth pull-down sustaining transistor T74 and the fifth pull-down sustaining transistor T75 are electrically connected to the first node Q(n). The source and drain of the fourth pull-down sustaining transistor T74 are electrically connected between the second node QB(n) and the first power supply terminal VGL1. The source and drain of the fifth pull-down sustaining transistor T75 are electrically connected between the gate of the third pull-down sustaining transistor T73 and the third power supply terminal VGL3. The source and drain of the sixth pull-down sustaining transistor T76 are electrically connected between the second node QB(n) and the first power supply terminal VGL1.

[0044] Please continue reading. Figure 2A The working principle of the gate driving circuit applied in a display panel is explained. Within one frame, it may include a normal driving phase and a mobility detection output phase.

[0045] The normal drive phase includes a reset phase t11, a potential pull-up phase t12, an effective pulse output phase, a potential drop phase t14, and a node pull-down phase t15. The mobility detection output phase may correspond to the blanking phase. Optionally, the blanking phase includes a horizontal blanking interval and / or a vertical blanking interval.

[0046] During the reset phase t11, the reset signal VST is high. The fifth pull-down control transistor T55 and the sixth pull-down control transistor T56 turn on in response to the reset signal VST, and the first voltage is transmitted to the first node Q(n) to reset the potential of the first node Q(n).

[0047] During the pull-up phase t12, when the row selection control signal LSP and the pull-up control signal Count(ny) are high, the first control transistor T31 and the second control transistor T32 turn on in response to the row selection control signal LSP. The high level of the pull-up control signal Count(ny) is transmitted to the detection node M(n). The third control transistor T33, the fourth control transistor T34 and the sixth control transistor T36 turn on as the potential of the detection node M(n) rises, thereby transmitting the preset voltage VGH to the detection node M(n). The sixth capacitor C6 maintains the potential of the detection node M(n). The first pull-up control transistor T11 and the second pull-up control transistor T12 are turned on in response to the pull-up control signal Count(ny), and the third pull-up control transistor T13 and the fourth pull-up control transistor T14 are turned on. The preset voltage VGH is transmitted to the first node Q(n) to raise the potential of the first node Q(n). As the potential of the first node Q(n) rises, the first pull-up transistor T21, the second pull-up transistor T22, the third pull-up transistor T23, the fourth pull-up transistor T24, the stage output transistor T25, the first leakage protection transistor T61, and the second leakage protection transistor T62 are turned on. The first pull-up transistor T21 is turned on, so that the first sub-clock signal CKB1 is transmitted to the first sub-output terminal WR(n), and the second pull-up transistor T22 is turned on. The first sub-clock signal CKB2 is transmitted to the second sub-output terminal WR(n+1), the third pull-up transistor T23 is turned on, the third sub-clock signal CKB3 is transmitted to the third sub-output terminal WR(n+2), the fourth pull-up transistor T24 is turned on, the fourth sub-clock signal CKB4 is transmitted to the fourth sub-output terminal WR(n+3), the first anti-leakage transistor T61 and the second anti-leakage transistor T62 are turned on, the preset voltage VGH is output to the third node N(n) and the fourth node N1(n), making the first pull-down control transistor T51, the second pull-down control transistor T52, the third pull-down control transistor T53 and the fourth pull-down control transistor T54 more completely turned off, reducing the probability of leakage from the first node Q(n) to the first power supply terminal VGL1. The stage output transistor T25 is turned on, the second clock signal CKA1 is transmitted to the stage output terminal Cout(n). The sixth pull-down sustaining transistor T76 is turned on in response to the pull-up control signal Count(ny), and the first voltage is transmitted to the second node QB(n) to pull down the potential of the second node QB(n).

[0048] The effective pulse output stage includes the first stage t13; in the first stage t13, the second clock signal CKA1 is high, and the first sub-clock signal CKB1, the second sub-clock signal CKB2, the third sub-clock signal CKB3, and the fourth sub-clock signal CKB4 are successively high. Due to the bootstrap effect of the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5, the potential of the first node Q(n) is pulled high again. The high level of the second clock signal CKA1 (i.e., the second effective pulse) is used as the effective pulse of the stage transmission signal and output through the stage transmission output terminal Cout(n); the high level of the first sub-clock signal CKB1... The first sub-effective pulse (i.e., the first sub-effective pulse) is output as the effective pulse of the nth level scan signal through the first sub-output terminal WR(n). The high level of the second sub-clock signal CKB2 (i.e., the second sub-effective pulse) is output as the effective pulse of the (n+1)th level scan signal through the second sub-output terminal WR(n+1). The high level of the third sub-clock signal CKB3 (i.e., the third sub-effective pulse) is output as the effective pulse of the (n+2)th level scan signal through the third sub-output terminal WR(n+2). The high level of the fourth sub-clock signal CKB4 (i.e., the fourth sub-effective pulse) is output as the effective pulse of the (n+3)th level scan signal through the fourth sub-output terminal WR(n+3).

[0049] During the potential drop phase t14, the second clock signal CKA1, the first sub-clock signal CKB1, the second sub-clock signal CKB2, the third sub-clock signal CKB3, and the fourth sub-clock signal CKB4 are all at low levels, the potential of the first node Q(n) drops, the low level of the second clock signal CKA1 is output through the stage output terminal Cout(n); the low level of the first sub-clock signal CKB1 is output through the first sub-output terminal WR(n), the low level of the second sub-clock signal CKB2 is output through the second sub-output terminal WR(n+1), the low level of the third sub-clock signal CKB3 is output through the third sub-output terminal WR(n+2), and the low level of the fourth sub-clock signal CKB4 is output through the fourth sub-output terminal WR(n+3).

[0050] During the node pull-down phase t15, the pull-down control signal Count(n+y) is high. The first pull-down control transistor T51 and the second pull-down control transistor T52 turn on in response to the pull-down control signal Count(n+y), and the first voltage is transmitted to the first node Q(n), causing the potential of the first node Q(n) to decrease again. In addition, because the low-frequency clock signal LC1 is high, the first pull-down sustaining transistor T71, the second pull-down sustaining transistor T72, and the third pull-down sustaining transistor T73 turn on, and the voltage of the second node QB(n) is raised, causing the third pull-down control transistor T53, the fourth pull-down control transistor T54, the first pull-down output transistor T41, the second pull-down output transistor T42, the third pull-down output transistor T43, the fourth pull-down output transistor T44, and the fifth pull-down output transistor T45 to turn on. The third pull-down control transistor T53 and the fourth pull-down control transistor T54 are turned on, causing the first voltage to be transmitted to the first node Q(n) to pull down the potential of the first node Q(n); the first pull-down output transistor T41 is turned on, causing the first voltage to be transmitted to the first sub-output terminal WR(n); the second pull-down output transistor T42 is turned on, causing the first voltage to be transmitted to the second sub-output terminal WR(n+1); the third pull-down output transistor T43 is turned on, causing the first voltage to be transmitted to the third sub-output terminal WR(n+2); the fourth pull-down output transistor T44 is turned on, causing the first voltage to be transmitted to the fourth sub-output terminal WR(n+3); and the fifth pull-down output transistor T45 is turned on, causing the first voltage to be transmitted to the stage output terminal Cout(n).

[0051] In the node pull-down phase t15, although the second clock signal CKA1 still has a valid pulse, the stage output transistor T25 is in the off state because the potential of the corresponding first node Q(n) is low. As a result, the valid pulse of the corresponding second clock signal CKA1 cannot be output to the stage output terminal Cout(n). Therefore, the valid pulse of the second clock signal CKA after the node pull-down phase t15 is different from the second valid pulse.

[0052] In the first sub-stage t21 of the mobility detection output stage, the reset signal Reset is high, and the fifth control transistor T35 and the seventh control transistor T37 are turned on. The fifth control transistor T35 turns on, causing the preset voltage VGH to be transmitted to the first node Q(n) to raise the potential of the first node Q(n). As the potential of the first node Q(n) rises, the first pull-up transistor T21, the second pull-up transistor T22, the third pull-up transistor T23, the fourth pull-up transistor T24, the stage output transistor T25, the first leakage protection transistor T61, and the second leakage protection transistor T62 are turned on. The seventh control transistor T37 turns on, causing the first voltage to be transmitted to the second node QB(n) to pull down the potential of the second node QB(n).

[0053] In the second sub-stage t22 of the mobility detection output stage, the second sub-clock signal CKB2 is at a high level. Due to the bootstrap effect of the second capacitor C2, the potential of the first node Q(n) is pulled up again. The high level of the second sub-clock signal CKB2 is used as an effective pulse to realize the detection and compensation of mobility and is output through the second sub-output terminal WR(n+1).

[0054] In the third sub-stage t23 of the mobility detection output stage, the row selection control signal LSP is high, the first control transistor T31 and the second control transistor T32 are turned on in response to the row selection control signal LSP, the low level of the pull-up control signal Count(ny) is transmitted to the detection node M(n), and the third control transistor T33, the fourth control transistor T34 and the sixth control transistor T36 are turned off.

[0055] By randomly selecting rows to output effective pulses for detecting and compensating mobility during the blanking phase of each frame, the purpose of random row selection for mobility detection and compensation can be achieved, thereby improving the display quality of the display panel.

[0056] It is understood that when the gate driving circuit is applied to the display panel, the display panel may include multiple gate driving circuits. Correspondingly, multiple first clock signals CKB (e.g., CKB1 to CKB16) cycle and second clock signals CKA (e.g., CKA1 to CKA4) cycle are electrically connected to the multiple gate driving circuits. Correspondingly, the mobility detection and compensation of different pixel rows within the display panel also correspond to the cycle of the multiple first clock signals CKB (e.g., CKB1 to CKB16), and the reset signal Reset in the multiple gate driving circuits also corresponds to the cycle of the second clock signals CKA (e.g., CKA1 to CKA4), as shown in Table 1.

[0057]

[0058] To verify the effectiveness of the invention, the inventors adopted different design schemes for the second clock signal CKA (Scheme 1: the duration of the second effective pulse of the second clock signal CKA is 2H, such as...). Figure 2B As shown; Scheme 2: The duration of the second valid pulse of the second clock signal CKA is 6H, as shown. Figure 2C As shown in Table 2; Scheme 3: The duration of the second effective pulse of the second clock signal CKA is designed according to the present invention) was compared experimentally, and the verification results are shown in Table 2. Wherein, RT(x) represents the rising edge time of the x-th level scan signal, and FT(x) represents the falling edge time of the x-th level scan signal; x≥1.

[0059] Alternatively, x can be equal to n, n+1, n+2, or n+3.

[0060]

[0061] As shown in Table 2, the difference in rising edge time and falling edge time of adjacent scan signals obtained by Scheme 1 is relatively large, the difference in falling edge time of adjacent scan signals obtained by Scheme 2 can only be improved, while the difference in rising edge time and falling edge time of adjacent scan signals obtained by this application is improved.

[0062] The present invention also provides a display panel including any of the aforementioned gate driving circuits, to improve the reliability of mobility detection output while achieving random row selection mobility detection compensation, and to alleviate the problems of excessive difference in rising edge time and falling edge time between adjacent scan signals. Furthermore, since multiple scan signals can be generated by the same gate driving circuit, the reduction in the number of transistors included in the gate driving circuit facilitates a narrow bezel design for the display panel.

[0063] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A gate driving circuit, characterized in that, include: The pull-up control module is electrically connected to the first node and is configured to output a preset voltage to the first node according to the pull-up control signal, so as to raise the potential of the first node; The first pull-up output module is electrically connected to the first node, multiple first clock signal lines, and multiple first output terminals of the gate drive circuit. It is configured to output multiple first clock signals transmitted by the multiple first clock signal lines to multiple first output terminals according to the potential of the first node; wherein, the multiple first output terminals are configured to output multi-level scan signals. The second pull-up output module is electrically connected to the first node, the second clock signal line, and the stage output terminal of the gate drive circuit. It is configured to output the second clock signal transmitted via the second clock signal line to the stage output terminal based on the potential of the first node. A random row selection module, electrically connected to the first node and the second node, is configured to output the preset voltage to the first node and output the first voltage output from the first power supply terminal to the second node during the blanking phase, based on the row selection control signal, the reset signal, and the pull-up control signal, so as to raise the potential of the first node and pull down the potential of the second node; the random row selection module includes a first selection control transistor, a second selection control transistor, a third selection control transistor, a fourth selection control transistor, a fifth selection control transistor, a sixth selection control transistor, a seventh selection control transistor, and a sixth capacitor; Specifically, during the first stage in which the second valid pulse of the second clock signal is output to the stage output terminal, the first valid pulses of multiple first clock signals are output to multiple first output terminals; during the first stage, the start time of multiple first valid pulses is delayed after the start time of the second valid pulse, and the end time of multiple first valid pulses is advanced before the end time of the second valid pulse.

2. The gate driving circuit according to claim 1, characterized in that, The first pull-up output module includes: The first pull-up output unit includes a first pull-up transistor and a first capacitor. The gate of the first pull-up transistor is electrically connected to the first node. The source and drain of the first pull-up transistor are electrically connected between a first sub-clock signal line and a first sub-output terminal. The first capacitor is connected in series between the first node and the first sub-output terminal. The plurality of first output terminals include a first sub-output terminal configured to output an nth level scan signal, where n ≥ 1. The plurality of first clock signal lines include first sub-clock signal lines, and the first sub-clock signal lines output a first sub-valid pulse corresponding to a first duration during the first stage. The second pull-up output unit includes a second pull-up transistor and a second capacitor. The gate of the second pull-up transistor is electrically connected to the first node. The source and drain of the second pull-up transistor are electrically connected between the second sub-clock signal line and the second sub-output terminal. The second capacitor is connected in series between the first node and the second sub-output terminal. The plurality of first output terminals include a second sub-output terminal configured to output a scan signal of the (n+1)th level. The plurality of first clock signal lines include second sub-clock signal lines. The second sub-clock signal lines output a second sub-valid pulse corresponding to a second duration during the first stage. The third pull-up output unit includes a third pull-up transistor and a third capacitor. The gate of the third pull-up transistor is electrically connected to the first node. The source and drain of the third pull-up transistor are electrically connected between a third sub-clock signal line and a third sub-output terminal. The third capacitor is connected in series between the first node and the third sub-output terminal. The plurality of first output terminals include the third sub-output terminal configured to output a scan signal of the (n+2)th level. The plurality of first clock signal lines include the third sub-clock signal line. The third sub-clock signal line outputs a third sub-valid pulse corresponding to a third duration within the first stage. The fourth pull-up output unit includes a fourth pull-up transistor and a fourth capacitor. The gate of the fourth pull-up transistor is electrically connected to the first node. The source and drain of the fourth pull-up transistor are electrically connected between the fourth sub-clock signal line and the fourth sub-output terminal. The fourth capacitor is connected in series between the first node and the fourth sub-output terminal. The plurality of first output terminals include the fourth sub-output terminal configured to output the (n+3)th level scan signal. The plurality of first clock signal lines include the fourth sub-clock signal line. The fourth sub-clock signal line outputs a fourth sub-valid pulse corresponding to the fourth duration during the first stage. The first valid pulse of the plurality of first clock signals includes a first sub-valid pulse, a second sub-valid pulse, a third sub-valid pulse, and a fourth sub-valid pulse; the first duration is equal to the second duration, the second duration is equal to the third duration, and the third duration is equal to the fourth duration.

3. The gate driving circuit according to claim 2, characterized in that, The second pull-up output module includes: A stage output transistor, wherein the gate of the stage output transistor is electrically connected to the first node, and the source and drain of the stage output transistor are electrically connected between the second clock signal line and the stage output terminal; The fifth capacitor is connected in series between the first node and the stage output terminal; In this process, the second clock signal line outputs a second valid pulse corresponding to a fifth duration within the first stage. The fifth duration is equal to 7 times the unit duration, and the first duration, the second duration, the third duration, and the fourth duration are all twice the unit duration.

4. The gate driving circuit according to claim 2, characterized in that, Also includes: The first pull-down output module includes a first pull-down output transistor, a second pull-down output transistor, a third pull-down output transistor, and a fourth pull-down output transistor; The gates of the first pull-down output transistor, the second pull-down output transistor, the third pull-down output transistor, and the fourth pull-down output transistor are all electrically connected to the second node. The source and drain of the first pull-down output transistor are electrically connected between the second power supply terminal and the first sub-output terminal. The source and drain of the second pull-down output transistor are electrically connected between the second power supply terminal and the second sub-output terminal. The source and drain of the third pull-down output transistor are electrically connected between the second power supply terminal and the third sub-output terminal. The source and drain of the fourth pull-down output transistor are electrically connected between the second power supply terminal and the fourth sub-output terminal. as well as The second pull-down output module includes a fifth pull-down output transistor, the gate of which is electrically connected to the second node, and the source and drain of which are electrically connected between the first power supply terminal and the stage transmission output terminal.

5. The gate driving circuit according to claim 4, characterized in that, It also includes a pull-down control module, which includes a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, a fourth pull-down control transistor, a fifth pull-down control transistor, and a sixth pull-down control transistor; In this configuration, the gates of the first and second pull-down control transistors are both configured to receive pull-down control signals; the gates of the third and fourth pull-down control transistors are both electrically connected to the second node; and the gates of the fifth and sixth pull-down control transistors are both configured to receive reset signals. The source and drain of the first pull-down control transistor are electrically connected between one of the source and drain of the second pull-down control transistor and the first power supply terminal, while the other of the source and drain of the second pull-down control transistor is electrically connected to the first node. Similarly, the source and drain of the third pull-down control transistor are electrically connected between one of the source and drain of the fourth pull-down control transistor and the first power supply terminal, while the other of the source and drain of the fourth pull-down control transistor is electrically connected to the first node. Finally, the source and drain of the fifth pull-down control transistor are electrically connected between one of the source and drain of the sixth pull-down control transistor and the first power supply terminal, while the other of the source and drain of the sixth pull-down control transistor is electrically connected to the first node.

6. The gate driving circuit according to claim 5, characterized in that, The first pull-down control transistor is electrically connected to one of the source and drain of the second pull-down control transistor through a third node, and the third pull-down control transistor is electrically connected to one of the source and drain of the fourth pull-down control transistor through a fourth node. The gate drive circuit further includes a leakage protection module, which includes a first leakage protection transistor and a second leakage protection transistor. The gates of both the first and second leakage protection transistors are electrically connected to the first node. One of the source and drain of the first leakage protection transistor is configured to receive the preset voltage. The other of the source and drain of the first leakage protection transistor is electrically connected to one of the source and drain of the second leakage protection transistor. The other of the source and drain of the second leakage protection transistor is configured to be electrically connected to the third and fourth nodes.

7. The gate driving circuit according to claim 4, characterized in that, It also includes a pull-down sustaining module, which includes a first pull-down sustaining transistor, a second pull-down sustaining transistor, a third pull-down sustaining transistor, a fourth pull-down sustaining transistor, a fifth pull-down sustaining transistor, and a sixth pull-down sustaining transistor; In this configuration, the gates of the first and second pull-down sustaining transistors are configured to receive a low-frequency clock signal, the gate of the sixth pull-down sustaining transistor is configured to receive the pull-up control signal, one of the source and drain of the first pull-down sustaining transistor and one of the source and drain of the third pull-down sustaining transistor are configured to receive the low-frequency clock signal; the source and drain of the second pull-down sustaining transistor are electrically connected between the other of the source and drain of the first pull-down sustaining transistor and the gate of the third pull-down sustaining transistor, the other of the source and drain of the third pull-down sustaining transistor is electrically connected to the second node, the gates of the fourth and fifth pull-down sustaining transistors are electrically connected to the first node, the source and drain of the fourth pull-down sustaining transistor are electrically connected between the second node and the first power supply terminal, the source and drain of the fifth pull-down sustaining transistor are electrically connected between the gate of the third pull-down sustaining transistor and the third power supply terminal, and the source and drain of the sixth pull-down sustaining transistor are electrically connected between the second node and the first power supply terminal.

8. The gate driving circuit according to claim 1, characterized in that, The gates of the first and second control transistors are configured to receive the row selection control signal. The gates of the third, fourth, and sixth control transistors are electrically connected to one of the source and drain of the second control transistor. The gate of the fifth control transistor is configured to receive a reset signal, and the gate of the seventh control transistor is configured to receive the reset signal. One of the source and drain of the first control transistor is configured to receive the pull-up control signal. One of the source and drain of the third and fourth control transistors is configured to receive the preset voltage. One of the source and drain of the six-selection transistor is configured to receive the first voltage; the other of the source and drain of the second-selection transistor and the other of the source and drain of the third-selection transistor are electrically connected to the other of the source and drain of the first-selection transistor; the source and drain of the fifth-selection transistor are electrically connected between the other of the source and drain of the fourth-selection transistor and the first node; the source and drain of the seventh-selection transistor are electrically connected between the other of the source and drain of the sixth-selection transistor and the second node; and the sixth capacitor is connected in series between the gate of the fourth-selection transistor and one of the source and drain of the fourth-selection transistor.

9. The gate driving circuit according to claim 1, characterized in that, The pull-up control module includes a first pull-up control transistor, a second pull-up control transistor, a third pull-up control transistor, and a fourth pull-up control transistor. The gates of the first and second pull-up control transistors are both configured to receive the pull-up control signal. The gates of the third and fourth pull-up control transistors are both configured to receive the preset voltage. One of the source and drain of the first and third pull-up control transistors is configured to receive the preset voltage. The source and drain of the second pull-up control transistor are electrically connected between the other of the source and drain of the first pull-up control transistor and the first node. The source and drain of the fourth pull-up control transistor are electrically connected between the other of the source and drain of the third pull-up control transistor and the other of the source and drain of the first pull-up control transistor.

10. A display panel, characterized in that, Includes the gate drive circuit as described in any one of claims 1 to 9.

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