Charge pump circuit

Abstract

A charge pump circuit includes a pump-up unit including a first capacitor, a second capacitor, a first transistor, and a second transistor, the pump-up unit configured to perform a voltage pump-up operation on a supply voltage in response to a first clock signal and a second clock signal to generate a first pumped-up voltage at a first node and a second pumped-up voltage at a second node; a self-unlock unit connected between the second end of the first transistor and the second transistor and the supply voltage, the self-unlock unit configured to raise the voltage at the second end of one of the first transistor and the second transistor when the supply voltage decreases from a first voltage value to a second voltage value to limit the on degree of one of the first transistor and the second transistor, thereby ensuring that the charge pump circuit can work normally.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a charge pump circuit. Background Technology

[0002] Charge pump circuits, which can convert a single power supply into different voltages, are widely used in integrated circuits. In DC-DC switching power supplies and LDO (low-dropout linear regulator) systems, when the source voltage of the driven NMOS (N-Metal-Oxide-Semiconductor) transistor is close to its power supply voltage, its gate voltage can only be the power supply voltage at most without any processing. At this time, the NMOS transistor cannot work normally because the voltage difference between its gate and source is less than its threshold voltage. In this case, a charge pump circuit is needed to boost the power supply voltage so that the gate voltage of the NMOS transistor is higher than the power supply voltage, thereby enabling the NMOS transistor to work normally.

[0003] Figure 1 A schematic diagram of a charge pump circuit according to the prior art is shown. See also Figure 1 The charge pump circuit includes transistors Mn1 and Mn2, capacitors C1 and C2, and inverter 10. Transistors Mn1 and Mn2 are NMOS transistors. Capacitor C1 is connected between clock signal CLK and node A, capacitor C2 is connected between clock signal CLK1 and node B, transistor Mn1 is connected between node A and the power supply voltage VCC, and the control terminal of transistor Mn1 is connected to node B. Transistor Mn2 is connected between node B and the power supply voltage VCC, and the control terminal of transistor Mn2 is connected to node A. Inverter 10 is connected between clock signal CLK and clock signal CLK1.

[0004] Before the charge pump circuit starts, the voltage across capacitors C1 and C2 is zero. When the charge pump circuit starts and the clock signal CLK is low (zero), the voltage at the first terminal of capacitor C1 (the terminal receiving the clock signal CLK) is zero, and the voltage at the first terminal of capacitor C2 (the terminal receiving the clock signal CLK1) is the power supply voltage VCC. Since the capacitor voltage cannot change abruptly, the voltage at the second terminal of capacitor C1, i.e., node A, is zero, and the voltage at the second terminal of capacitor C2, i.e., node B, is the power supply voltage VCC. At this time, since the source terminal of transistor Mn1 is connected to the power supply voltage VCC, it will charge node A through the body diode, causing the voltage at node A to quickly reach VCC-V1 (V1 is the voltage drop across the body diode). At this time, the voltage across capacitor C1 is also VCC-V1. When the clock signal CLK jumps high (to the power supply voltage VCC), the voltage across capacitor C1 is VCC-V1 and cannot change abruptly. Therefore, the voltage at node A is 2*VCC-V1, which is also the gate voltage of transistor Mn2. The source voltage of transistor Mn2 is the power supply voltage VCC, which is typically greater than 1.8V. Thus, the voltage difference between the gate and source of transistor Mn2 is higher than the threshold voltage, allowing transistor Mn2 to turn on normally. Ideally, this would charge the voltage at node B from zero to the power supply voltage VCC, which is also the voltage across capacitor C2. Then, the clock signal CLK drops to zero again. Since the voltage across capacitor C2 is now the power supply voltage VCC, and the voltage at its first terminal is also VCC, the voltage at node B is 2*VCC. At this point, transistor Mn1 turns on, charging the voltage at node A to the power supply voltage VCC. This alternating operation keeps the voltage across capacitors C1 and C2 at the power supply voltage VCC. This ensures that when the clock signal CLK is high, the voltage at node A is 2*VCC, and when the clock signal CLK is low, the voltage at node B is also 2*VCC.

[0005] However, in practical applications, if the power supply voltage VCC changes, for example, decreasing from vcc1 to vcc2, and vcc1 - vcc2 > Vth (where Vth is the threshold voltage of transistor Mn1 / Mn2), then... Figure 2The timing diagram shown assumes that the clock signal CLK is always zero during the change process. At this time, transistor Mn1 is turned on, and the voltage of node A and the voltage of capacitor C1 will change with the power supply voltage VCC. The voltage on capacitor C2 remains at the first voltage value vcc1 because transistor Mn2 is turned off. However, since the voltage at the first end of capacitor C2 changes to the second voltage value vcc2, the voltage of node B will become vcc1 + vcc2. Once the power supply voltage VCC stabilizes at the second voltage value vcc2, if the clock signal CLK goes high, the voltage at node B will be the voltage of capacitor C2, i.e., the first voltage value vcc1, which is higher than the second voltage value vcc2 by one Vth. This still allows transistor Mn1 to turn on. Therefore, the voltage at node A can reach 2*vcc2 when the clock signal CLK just goes high, but it will be quickly discharged by the turned-on transistor Mn1 and finally stabilize at the second voltage value vcc2. The voltage on capacitor C1 will also stabilize at zero. When the clock signal CLK changes from high voltage to zero, the voltage at node B will again reach vcc1+vcc2, thus continuing to turn on transistor Mn1 to charge capacitor C1. This alternating operation continues. Assuming there is no leakage in the capacitor, when the clock signal CLK is zero, the voltage at node B can be pumped to vcc1+vcc2. However, because transistor Mn1 is always on, the voltage at node A cannot be steadily pumped to exceed the power supply voltage VCC. As long as the power supply voltage VCC does not go high, this state will remain locked. When the power supply voltage VCC decreases from the first voltage value vcc1 to the second voltage value vcc2, and the clock signal CLK is high during the change, the situation is exactly the opposite of the above. When the clock signal CLK is high, node A can pump up, but not twice the power supply voltage VCC, while node B can only stabilize at the current power supply voltage VCC.

[0006] Therefore, a new charge pump circuit needs to be proposed to solve the above problems. Summary of the Invention

[0007] In view of the above problems, the object of the present invention is to provide a charge pump circuit that can operate normally when the power supply voltage is reduced from a first voltage value to a second voltage value, and the difference between the first voltage value and the second voltage value is greater than the turn-on threshold of the NMOS transistor.

[0008] According to one aspect of the present invention, a charge pump circuit is provided, comprising a pump-up unit including a first capacitor, a second capacitor, a first transistor, and a second transistor, wherein the first capacitor is connected between a first clock signal and a first node, the second capacitor is connected between a second clock signal and a second node, a first terminal of the first transistor and a control terminal of the second transistor are connected to the first node, and the control terminal of the first transistor and the first terminal of the second transistor are connected to the second node, the pump-up unit being configured to perform a voltage pump-up operation on a power supply voltage in response to the first clock signal and the second clock signal to generate a first pump-up voltage at the first node and a second pump-up voltage at the second node; and a self-unlocking unit connected between the second terminals of the first transistor and the second transistor and the power supply voltage, the self-unlocking unit being configured to raise the second terminal voltage of one of the first transistor and the second transistor when the power supply voltage decreases from a first voltage value to a second voltage value, thereby limiting the conduction level of one of the first transistor and the second transistor.

[0009] Optionally, the self-unlocking unit includes a third transistor, with its first end connected to the second end of the first transistor, the second end connected to the power supply voltage, and its control end connected to the first clock signal; and a fourth transistor, with its first end connected to the second end of the second transistor, the second end connected to the power supply voltage, and its control end connected to the second clock signal.

[0010] Optionally, both the first transistor and the second transistor are NMOS transistors.

[0011] Optionally, both the third transistor and the fourth transistor are PMOS transistors.

[0012] Optionally, the first clock signal and the second clock signal are inverted signals.

[0013] Optionally, the charge pump circuit further includes an inverter for generating the second clock signal based on the first clock signal.

[0014] Optionally, the high-level voltages of the first clock signal and the second clock signal follow the power supply voltage, and the low-level voltages of the first clock signal and the second clock signal are ground voltages.

[0015] Optionally, the difference between the first voltage value and the second voltage value is greater than the turn-on threshold of the NMOS transistor.

[0016] Optionally, the self-unlocking unit is used to raise the second terminal voltage of one of the first transistor and the second transistor to a value equal to the sum of the second voltage value and the turn-on threshold of the PMOS transistor when the power supply voltage drops from the first voltage value to the second voltage value.

[0017] Optionally, during the process of the power supply voltage decreasing from the first voltage value to the second voltage value, if the first clock signal is always low, the self-unlocking unit is used to raise the second terminal voltage of the first transistor to be equal to the sum of the second voltage value and the conduction threshold of the PMOS transistor; if the first clock signal is always high, the self-unlocking unit is used to raise the second terminal voltage of the second transistor to be equal to the sum of the second voltage value and the conduction threshold of the PMOS transistor.

[0018] The charge pump circuit provided by this invention includes a pump-up unit and a self-unlocking unit. The pump-up unit includes a first capacitor, a second capacitor, a first transistor, and a second transistor. The pump-up unit is configured to perform voltage pumping operation on the power supply voltage in response to a first clock signal and a second clock signal, so as to generate a first pump-up voltage at a first node and a second pump-up voltage at a second node. The self-unlocking unit is connected between the second terminal of the first transistor and the second transistor and the power supply voltage. The self-unlocking unit is used to raise the second terminal voltage of one of the first transistor and the second transistor when the power supply voltage drops from the first voltage value to the second voltage value, so as to limit the conduction degree of one of the first transistor and the second transistor, thereby ensuring that the charge pump circuit can work normally. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0020] Figure 1 A schematic diagram of a charge pump circuit according to the prior art is shown;

[0021] Figure 2 A timing diagram of a charge pump circuit according to the prior art is shown;

[0022] Figure 3 A schematic diagram of a charge pump circuit according to an embodiment of the present invention is shown;

[0023] Figure 4 A timing diagram of a charge pump circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0024] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0025] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0026] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0027] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0028] Figure 3 A schematic diagram of a charge pump circuit according to an embodiment of the present invention is shown. See also Figure 3 The charge pump circuit includes a self-unlocking unit 100, a pump-up unit 200, and an inverter 300.

[0029] The boost unit 200 includes capacitors C1 and C2, transistors Mn1 and Mn2. Capacitor C1 is connected between clock signal CLK and node A, capacitor C2 is connected between clock signal CLK1 and node B, the first terminal of transistor Mn1 and the control terminal of transistor Mn2 are connected to node A, and the control terminal of transistor Mn1 and the first terminal of transistor Mn2 are connected to node B. The boost unit 200 is configured to perform voltage boosting operation on the power supply voltage VCC in response to clock signals CLK and CLK1, generating a first boost voltage at node A and a second boost voltage at node B. Both transistors Mn1 and Mn2 are NMOS transistors.

[0030] Optionally, the control terminals of transistors Mn1 and Mn2 are gate terminals, the first terminal is the drain terminal, and the second terminal is the source terminal.

[0031] The self-unlocking unit 100 is connected between the second terminals of transistors Mn1 and Mn2 and the power supply voltage VCC. The self-unlocking unit 100 is used to raise the voltage of the second terminal of one of transistors Mn1 and Mn2 when the power supply voltage VCC drops from the first voltage value vcc1 to the second voltage value vcc2, so as to limit the conduction degree of one of transistors Mn1 and Mn2.

[0032] The self-unlocking unit 100 includes transistors Mp1 and Mp2. Transistor Mp1 is connected between the second terminal of transistor Mn1 and the power supply voltage VCC, and transistor Mp2 is connected between the second terminal of transistor Mn2 and the power supply voltage VCC. Transistors Mp1 and Mp2 are PMOS transistors.

[0033] Optionally, the control terminals of transistors Mp1 and Mp2 are gate terminals, the first terminal is the source terminal, and the second terminal is the drain terminal.

[0034] Inverter 300 is used to generate clock signal CLK1 based on clock signal CLK. The high-level voltages of clock signals CLK and CLK1 follow the power supply voltage VCC, while the low-level voltages of clock signals CLK and CLK1 are ground voltages.

[0035] Figure 4 A timing diagram of a charge pump circuit according to an embodiment of the present invention is shown. The following is in conjunction with... Figure 3 and Figure 4 The working principle of the charge pump circuit in the embodiment of the present invention will be explained.

[0036] Before the circuit starts up to time t1, the power supply voltage VCC of the charge pump circuit maintains the first voltage value vcc1. Assuming that the clock signal CLK is low when the charge pump circuit starts up, the voltage at the first terminal of capacitor C1 is zero, making the voltage at node A zero as well. The voltage at the first terminal of capacitor C2 is the first voltage value vcc1, making the voltage at node B also the first voltage value vcc1. At this time, the voltage at the control terminal of transistor Mp1 is zero, and the voltage at the second terminal of transistor Mp1 is the first voltage value vcc1, causing transistor Mp1 to conduct and charge the second terminal of transistor Mn1. After stabilization, the voltage at the second terminal of transistor Mn1 can be charged to the first voltage value vcc1. At the same time, during this process, when the voltage at the second terminal of transistor Mn1 is greater than the forward voltage of its body diode, it will charge node A through the body diode of transistor Mn1 until the voltage at node A is charged to vcc1-V1 (V1 is the voltage drop across the body diode of transistor Mn1). Since the voltage at the first terminal of capacitor C1 is zero at this time, vcc1-V1 is also the voltage of capacitor C1. Furthermore, when the charge pump circuit is first started, the voltage at the second terminal of transistor Mp2 is the first voltage value vcc1, and the voltage at the control terminal of transistor Mp2 is the first voltage value vcc1. Therefore, transistor Mp2 is in the off state. However, transistor Mp2 will charge the voltage at the second terminal of transistor Mn2 to vcc1-V2 (V2 is the voltage drop across the body diode of transistor Mp2) through its body diode. Since the voltage at the control terminal of transistor Mn2 is vcc1-V1, and the voltage values ​​of V1 and V2 are approximately the same, transistor Mn2 remains off.

[0037] Then, the clock signal CLK changes from low to high, causing the voltage at node A to jump to 2*vcc1-V1, and the voltage at node B to jump to zero. At this time, the voltage at the second terminal of transistor Mp1 is the first voltage value vcc1, and the voltage at the control terminal of transistor Mp1 is also the first voltage value vcc1, causing transistor Mp1 to turn off. The voltage at the control terminal of transistor Mn1 is zero, and the voltage at the second terminal of transistor Mn1 remains at the first voltage value vcc1, causing transistor Mn1 to turn off. Furthermore, at the same time that the clock signal CLK changes from low to high, the control terminal voltage of transistor Mp2 is zero, and the second terminal voltage of transistor Mp2 is the first voltage value vcc1. Therefore, transistor Mp2 is turned on, and the second terminal voltage of transistor Mn2 is charged by transistor Mp2 to the first voltage value vcc1. Since the control terminal voltage of transistor Mn2 is 2*vcc1-V1, transistor Mn2 is turned on, and the power supply voltage VCC charges node B through transistors Mn2 and Mp2, charging the voltage of node B to the first voltage value vcc1. At this time, the voltage on capacitor C2 is the first voltage value vcc1.

[0038] Next, the clock signal CLK changes from high to low, causing it to become zero. The clock signal CLK1 then becomes the first voltage value vcc1. The voltage at node A becomes vcc1-V1, and the voltage at node B becomes 2*vcc1. At this time, the control terminal voltage of transistor Mp1 is zero, and the voltage at the second terminal of transistor Mp1 is the first voltage value vcc1, turning transistor Mp1 on. The control terminal voltage of transistor Mn1 is 2*vcc1, and the voltage at the second terminal of transistor Mn1 maintains the first voltage value vcc1, turning transistor Mn1 on. The power supply voltage VCC charges node A through transistors Mn1 and Mp1, charging the voltage at node A to the first voltage value vcc1. At this time, the voltage across capacitor C1 is also the first voltage value vcc1. Furthermore, at the same time that the clock signal CLK changes from high level to low level, the control terminal voltage of transistor Mp2 is the first voltage value vcc1, and the second terminal voltage of transistor Mp2 is the first voltage value vcc1, so that transistor Mp2 is in the off state. At the same time, the control terminal voltage of transistor Mn2 is less than or equal to the first voltage value vcc1, and the second terminal voltage of transistor Mn2 maintains the first voltage value vcc1, so that transistor Mn2 is in the off state.

[0039] In summary, when the power supply voltage VCC remains constant, after the circuit stabilizes, the voltage across capacitors C1 and C2 will both be the power supply voltage VCC. Therefore, utilizing the principle that capacitor voltage cannot change abruptly, the voltages at nodes A and B alternate between 2*VCC following the clock signal CLK. See [link to details]. Figure 4 The timing diagram for t0-t1.

[0040] At time t1, the power supply voltage VCC decreases from the first voltage value vcc1 to the second voltage value vcc2, and the clock signal CLK remains zero during the change. Therefore, the voltage at the first terminal of capacitor C2 decreases from the first voltage value vcc1 to the second voltage value vcc2, causing the voltage at node B to become vcc1 + vcc2. Since transistors Mn1 and Mp1 are turned on, the voltage at node A discharges to the second voltage value vcc2. At this time, the voltage on capacitor C1 is also the second voltage value vcc2.

[0041] At time t2, the power supply voltage VCC stabilizes at the second voltage value vcc2. When the clock signal CLK just transitions from low to high, the voltage at the first terminal of capacitor C1 is the second voltage value vcc2, making the voltage at node A 2*vcc2. The voltage at the first terminal of capacitor C2 is zero, making the voltage at node B the first voltage value vcc1. Therefore, the voltage at the control terminal of transistor Mn1 is the first voltage value vcc1, and the voltage at the second terminal of transistor Mn1 is the second voltage value vcc2. If vcc1 - vcc2 < Vthn (Vthn is the turn-on threshold of the NMOS transistor), then the circuit can operate normally.

[0042] If vcc1-vcc2>Vthn, then at time t2, the control terminal voltage of transistor Mn1 is the first voltage value vcc1, and the second terminal voltage of transistor Mn1 maintains the second voltage value vcc2, making transistor Mn1 turn on. The control terminal voltage of transistor Mp1 is the second voltage value vcc2, and the first terminal voltage of transistor Mp1 maintains the second voltage value vcc2, making transistor Mp1 turn off. The control terminal voltage of transistor Mn2 is 2*vcc2, and the second terminal voltage of transistor Mn2 maintains the first voltage value vcc1, making transistor Mn2 turn on. The control terminal voltage of transistor Mp2 is zero, and the first terminal voltage of transistor Mp2 maintains the first voltage value vcc1, making transistor Mp2 turn on.

[0043] After time t2, transistor Mn1 charges its second terminal. After the voltage at its second terminal is charged to vcc2+Vthp (Vthp is the turn-on threshold of the PMOS transistor), the current path of transistors Mn1 and Mp1 is turned on, discharging to node A. Since Vgs1 = 2vcc2 - (vcc2 + Vthp) = vcc2 - Vthp of transistor Mn1 is smaller than Vgs = 2vcc2 - vcc2 = vcc2 of transistor Mn1 in the prior art, the conduction degree of transistor Mn1 is lower than that of the prior art. The discharge speed is also slower when the first pump-up voltage is generated at node A, and node A can only discharge up to vcc2 + Vthp. At time t2, transistors Mn2 and Mp2 turn on, making the source voltage of transistor Mn2 change to the second voltage value vcc2. Therefore, even if node A is stable at vcc2 + Vthp, transistor Mn2 can still be turned on, and it will not affect the discharge of capacitor C2 by the current path of transistors Mn2 and Mp2. After several cycles, at time t3, the voltage on capacitor C2 will stabilize to the second voltage value vcc2, causing the charge pump circuit to exit the faulty lockout.

[0044] It is understandable that even if the clock signal CLK remains high during the process of the power supply voltage VCC decreasing from the first voltage value vcc1 to the second voltage value vcc2, this application can still enable the charge pump circuit to exit the erroneous lockout. At this time, the self-unlocking unit 100 raises the second terminal voltage of transistor Mn2 when the power supply voltage VCC decreases from the first voltage value vcc1 to the second voltage value vcc2, so as to limit the conduction degree of transistor Mn2. The specific working principle of the charge pump circuit is the same as described above.

[0045] The charge pump circuit provided in this embodiment of the invention includes a pump-up unit 200 and a self-unlocking unit 100. The pump-up unit 200 includes capacitors C1 and C2, and transistors Mn1 and Mn2. The pump-up unit 200 is configured to perform voltage pumping operation on the power supply voltage VCC in response to clock signals CLK and CLK1, to generate a first pump-up voltage at node A and a second pump-up voltage at node B. The self-unlocking unit 100 is connected between the second terminals of transistors Mn1 and Mn2 and the power supply voltage VCC. The self-unlocking unit 100 is used to raise the voltage of the second terminal of one of transistors Mn1 and Mn2 when the power supply voltage VCC drops from a first voltage value vcc1 to a second voltage value vcc2, thereby limiting the conduction degree of one of transistors Mn1 and Mn2 and ensuring that the charge pump circuit can operate normally.

[0046] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.

Claims

1. A charge pump circuit, comprising: A boost unit includes a first capacitor, a second capacitor, a first transistor, and a second transistor. The first capacitor is connected between a first clock signal and a first node, and the second capacitor is connected between a second clock signal and a second node. A first terminal of the first transistor and a control terminal of the second transistor are connected to the first node, and a control terminal of the first transistor and a first terminal of the second transistor are connected to the second node. The boost unit is configured to perform a voltage boost operation on the power supply voltage in response to the first clock signal and the second clock signal to generate a first boost voltage at the first node and a second boost voltage at the second node. as well as A self-unlocking unit is connected between the second terminals of the first transistor and the second transistor and the power supply voltage. The self-unlocking unit is used to raise the voltage at the second terminal of one of the first transistors and the second transistor when the power supply voltage decreases from a first voltage value to a second voltage value, thereby limiting the conduction level of one of the first transistors and the second transistor. The self-unlocking unit includes: The third transistor has a first terminal connected to the second terminal of the first transistor, the second terminal connected to the power supply voltage, and a control terminal connected to the first clock signal. The fourth transistor has its first terminal connected to the second terminal of the second transistor, the second terminal connected to the power supply voltage, and its control terminal connected to the second clock signal. Wherein, the first clock signal and the second clock signal are inverted signals, and the difference between the first voltage value and the second voltage value is greater than the conduction threshold of the first transistor and the second transistor.

2. The charge pump circuit according to claim 1, wherein, Both the first transistor and the second transistor are NMOS transistors.

3. The charge pump circuit of claim 1, wherein, Both the third transistor and the fourth transistor are PMOS transistors.

4. The charge pump circuit according to claim 1, further comprising: An inverter is used to generate the second clock signal based on the first clock signal.

5. The charge pump circuit of claim 1, wherein, The high-level voltages of the first clock signal and the second clock signal follow the power supply voltage, and the low-level voltages of the first clock signal and the second clock signal are ground voltages.

6. The charge pump circuit of claim 3, wherein, The self-unlocking unit is used to raise the second terminal voltage of one of the first transistor and the second transistor to a value equal to the sum of the second voltage value and the turn-on threshold of the PMOS transistor when the power supply voltage drops from the first voltage value to the second voltage value.

7. The charge pump circuit of claim 6, wherein, During the process of the power supply voltage decreasing from the first voltage value to the second voltage value, if the first clock signal is always low, the self-unlocking unit is used to raise the voltage at the second terminal of the first transistor to be equal to the sum of the second voltage value and the conduction threshold of the PMOS transistor; if the first clock signal is always high, the self-unlocking unit is used to raise the voltage at the second terminal of the second transistor to be equal to the sum of the second voltage value and the conduction threshold of the PMOS transistor.

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