Charge pump circuit

Abstract

Disclosed in the present invention is a charge pump circuit, comprising: a boost module, which is used for performing a voltage pumping operation on a power supply voltage in response to a first clock signal and a second clock signal so as to generate a pumped voltage, wherein the first clock signal and the second clock signal are differential signals; a voltage generator circuit, which is used for generating a reference voltage on the basis of the power supply voltage, wherein the voltage difference between the power supply voltage and the reference voltage is less than a set threshold; and an oscillator circuit, which has power supply nodes connected to the power supply voltage and the reference voltage, wherein the oscillator circuit is used for generating the first clock signal and the second clock signal, and the potentials of the first clock signal and second clock signal are switched between the power supply voltage and the reference voltage. The charge pump circuit in the present invention can alleviate the problem of an excessive voltage difference across both ends of a pumping capacitor, and thus the performance and reliability of the charge pump circuit are maintained while the chip area and cost are significantly reduced, thereby satisfying the requirements of high-voltage applications.

Description

Charge pump circuit Cross-reference to related applications

[0001] This application claims priority to Chinese Patent Application No. 202411579923.7, filed on November 6, 2024, entitled “Charge Pump Circuit”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of integrated circuit technology, and in particular to a charge pump circuit. Background Technology

[0003] With the continuous improvement of integrated circuit integration, the advancement of process nodes towards the deep submicron limit, and the diversification of chip application environments, charge pump circuits, as a fundamental module circuit, are widely used in various integrated circuit products. The main function of a charge pump circuit is to provide a positive voltage source higher than the positive rail of the input power supply voltage, and it also has a certain load-carrying capacity, thereby better meeting the system design specifications.

[0004] Figure 1 shows a schematic diagram of a charge pump circuit according to the prior art. Referring to Figure 1, the charge pump circuit 100 includes a boost module 110, an oscillator circuit 120, and an inverter INV1. The oscillator circuit 120 generates a clock signal CLK, the inverter INV1 generates a clock signal CLKB that is a differential clock signal with respect to the clock signal CLK, and the boost module 110 is configured to perform a voltage boost operation on the power supply voltage VCC in response to the clock signals CLK and CLKB to generate a boosted voltage VP.

[0005] The boost module 110 includes transistors T1 to T4 and boost capacitors C1 and C2. One end of boost capacitor C1 is connected to the clock signal CLK, and the other end is connected to boost node A inside the boost module 110. One end of boost capacitor C2 is connected to the clock signal CLKB, and the other end is connected to boost node B inside the boost module 110. Transistors T1 to T4 adopt a differential cross-coupled architecture. Transistors T1 and T2 are N-type field-effect transistors, and transistors T3 and T4 are P-type field-effect transistors. The sources of transistors T1 and T2 are connected to the power supply voltage VCC. The drains of transistors T1 and T3 and the gates of transistors T2 and T4 are connected to boost node A. The drains of transistors T2 and T4 and the gates of transistors T1 and T3 are connected to boost node B. The sources of transistors T3 and T4 are connected to the output terminal of the boost voltage VP. The charge pump circuit 100 utilizes the characteristic that the voltage across the pump capacitors C1 and C2 cannot change abruptly, continuously superimposing the voltage difference between the high and low levels of the clock signals CLK and CLKB onto the power supply voltage VCC, thereby obtaining a pump voltage VP at the output that is higher than the power supply voltage VCC.

[0006] In charge pump circuits for high-voltage applications, traditional designs face the challenge of capacitor selection due to the large voltage difference across the boost capacitor. For example, in high-voltage applications, the input clock source is typically located in a low-voltage domain (e.g., power supply AVIN is approximately 5V), while the output voltage VP of the boost module 110 may be in a high-voltage domain. In this case, the voltage difference across the boost capacitor can be very large. To improve the circuit's withstand voltage, metal-oxide-metal (MOM) capacitors are required. However, MOM capacitors have a relatively small capacitance per unit area, typically about 1 / 5 that of metal-insulator-metal (MIM) capacitors. Therefore, when the charge pump circuit is heavily loaded, larger MOM capacitors are needed to reduce the circuit's internal resistance, posing new challenges to chip area and cost. Summary of the Invention

[0007] In view of the above problems, the purpose of this invention is to provide a charge pump circuit that helps to improve the problem of excessive voltage difference across the pump-up capacitor.

[0008] According to one aspect of the present invention, a charge pump circuit is provided, comprising: a boost module for performing a voltage boosting operation on a power supply voltage in response to a first clock signal and a second clock signal to generate a boosted voltage, wherein the first clock signal and the second clock signal are differential signals; a voltage generator circuit for generating a reference voltage based on the power supply voltage, wherein the voltage difference between the power supply voltage and the reference voltage is less than the set threshold; and an oscillator circuit having a power supply node connected to the power supply voltage and the reference voltage, the oscillator circuit being used to generate the first clock signal and the second clock signal, wherein the potentials of the first clock signal and the second clock signal switch between the power supply voltage and the reference voltage.

[0009] Optionally, the voltage generator circuit includes: a first reverse diode, the cathode of which is connected to the power supply voltage; a first transistor constituting a source follower, the first terminal of which is connected to the anode of the first reverse diode; a voltage regulator module connected between the power supply voltage and the control terminal of the first transistor; a first current source connected between the control terminal of the first transistor and a reference ground; a first resistor connected between the second terminal of the first transistor and the reference ground; and a first voltage regulator capacitor connected between the power supply voltage and the first terminal of the first transistor and outputting the reference voltage.

[0010] Optionally, the voltage regulator module includes: a second transistor and a second reverse diode connected in series, the first terminal of the second transistor being connected to the power supply voltage, the control terminal and the second terminal of the second transistor being connected to the cathode of the second reverse diode, and the anode of the second reverse diode being connected to the control terminal of the first transistor.

[0011] Optionally, the first reverse diode and the second reverse diode are Zener diodes.

[0012] Optionally, the voltage generator circuit includes: a step-down module for stepping down the power supply voltage using at least one MOS diode to obtain the reference voltage; a negative feedback module connected to the step-down module and the output terminal of the reference voltage for stabilizing the reference voltage; and a current bias module for providing bias current to the negative feedback module.

[0013] Optionally, the step-down module includes a third transistor and a fourth transistor connected in series between the output terminals of the power supply voltage and the reference voltage, wherein the third transistor and the fourth transistor are connected to form a MOS diode.

[0014] Optionally, the negative feedback module includes: a fifth transistor, the first terminal of which is connected to the output terminal of the reference voltage, and the second terminal of which is connected to reference ground; a sixth transistor, the first terminal of which is connected to the power supply voltage, and the control terminal of which is connected to the control terminal of the third transistor; a seventh transistor, the first terminal of which is connected to the second terminal of the sixth transistor; an eighth transistor, the first terminal of which is connected to the power supply voltage; and a ninth transistor, the first terminal of which is connected to the second terminal of the eighth transistor, and the second terminal of which is connected to the control terminal of the fifth transistor. The control terminals of the seventh, eighth, and ninth transistors are connected to the current bias module to obtain the bias current through mirroring; the tenth and eleventh transistors are current mirror structures, with their control terminals and the first terminal of the eleventh transistor connected to the second terminal of the seventh transistor, and the second terminals of the tenth and eleventh transistors connected to the reference ground; and the twelfth transistor, with its first terminal connected to the control terminal of the fifth transistor, its control terminal connected to the bias voltage, and its second terminal connected to the first terminal of the tenth transistor.

[0015] Optionally, the current biasing module includes: a thirteenth transistor, the first terminal of which is connected to the power supply voltage, the control terminal and the second terminal of which are short-circuited and connected to the control terminal of the eighth transistor; a fourteenth transistor, the first terminal of which is connected to the second terminal of the thirteenth transistor, the control terminal and the second terminal of which are short-circuited and connected to the control terminals of the seventh transistor and the ninth transistor; and a second current source connected between the second terminal of the fourteenth transistor and the reference ground.

[0016] Optionally, the voltage generator circuit further includes: a second voltage-regulating capacitor connected between the first terminal of the seventh transistor and the output terminal of the reference voltage; a third voltage-regulating capacitor connected between the power supply voltage and the output terminal of the reference voltage; a third reverse diode, the cathode of which is connected to the power supply voltage and the anode of which is connected to the output terminal of the reference voltage; and a Miller compensation capacitor connected between the first terminal of the fourteenth transistor and the output terminal of the reference voltage.

[0017] Optionally, the fifth transistor, the seventh transistor, and the ninth transistor are high-voltage transistors.

[0018] In summary, the charge pump circuit of this invention includes a boost module, a voltage generator circuit, and an oscillator circuit. The voltage generator circuit ensures that the power rail of the clock signal generated by the oscillator circuit is between the reference voltage and the power supply voltage, and the voltage difference between the power supply voltage and the reference voltage is less than a set threshold. This prevents the voltage difference across the boost capacitor from exceeding the set threshold, allowing a MIM capacitor to replace the MOM capacitor as the boost capacitor. Under the premise that the load conditions at the charge pump output remain unchanged, the internal resistance remains unchanged, and therefore the capacitance value remains unchanged. For the same capacitance value, the area of ​​the MIM capacitor is 1 / 5 of the area of ​​the MOM capacitor. Therefore, this invention can significantly reduce chip area and cost, ensure the performance and reliability of the charge pump circuit, and meet the requirements of high-voltage applications. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0020] Figure 1 shows a schematic diagram of a charge pump circuit according to the prior art.

[0021] Figure 2 shows a schematic diagram of a charge pump circuit according to an embodiment of the present invention.

[0022] Figure 3 shows a circuit diagram of a voltage generator circuit according to a first embodiment of the present invention.

[0023] Figure 4 shows a circuit diagram of another voltage generator circuit according to a second embodiment of the present invention. Detailed Implementation

[0024] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0025] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "coupled" to another element or "coupled" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between them.

[0026] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0027] Figure 2 shows a schematic diagram of a charge pump circuit according to an embodiment of the present invention. As shown in Figure 2, the charge pump circuit 200 includes a boost module 210, a voltage generator circuit 220, and an oscillator circuit 230. The boost module 210 is configured to perform a voltage boost operation on the power supply voltage VCC in response to clock signals CLK and CLKB to generate a boosted voltage VP. The voltage generator circuit 220 generates a reference voltage VREF based on the power supply voltage VCC, wherein the voltage difference between the power supply voltage VCC and the reference voltage VREF is less than a set threshold. The oscillator circuit 230 is, for example, a ring oscillator, having power supply nodes connected to the power supply voltage VCC and the reference voltage VREF, and generates the clock signals CLK and CLKB. The potentials of the clock signals CLK and CLKB switch between the power supply voltage VCC and the reference voltage VREF.

[0028] Furthermore, the boost module 210 includes transistors T1 to T4 and pump-up capacitors C1 and C2. One end of pump-up capacitor C1 is connected to the clock signal CLK, and the other end is connected to the boost node A inside the boost module 210. One end of pump-up capacitor C2 is connected to the clock signal CLKB, and the other end is connected to the boost node B inside the boost module 210. Transistors T1 to T4 adopt a differential cross-coupled architecture. Transistors T1 and T2 are N-type field-effect transistors, and transistors T3 and T4 are P-type field-effect transistors. The sources of transistors T1 and T2 are connected to the power supply voltage VCC. The drains of transistors T1 and T3 and the gates of transistors T2 and T4 are connected to boost node A. The drains of transistors T2 and T4 and the gates of transistors T1 and T3 are connected to boost node B. The sources of transistors T3 and T4 are connected to the output terminal of the pump-up voltage VP. The charge pump circuit 200 utilizes the characteristic that the voltage across the pump capacitors C1 and C2 cannot change abruptly, continuously superimposing the voltage difference between the high and low levels of the clock signals CLK and CLKB onto the power supply voltage VCC, thereby obtaining a pump voltage VP at the output that is higher than the power supply voltage VCC.

[0029] In this embodiment, the voltage difference across pump-up capacitors C1 and C2 is approximately equal to the voltage difference between the high and low levels of clock signals CLK and CLKB. The voltage generator circuit 220 brings the power rails of clock signals CLK and CLKB within the VREF~VCC voltage range, and the voltage difference between the power supply voltage VCC and the reference voltage VREF is less than a set threshold. This ensures that the voltage difference across pump-up capacitors C1 and C2 will not exceed the set threshold. In this case, pump-up capacitors C1 and C2 can be implemented using MIM capacitors. Under the same load conditions, the internal resistance remains unchanged, so the capacitance value remains unchanged. For the same capacitance value, the area of ​​a MIM capacitor is 1 / 5 of the area of ​​a MOM capacitor. Therefore, in high-voltage applications, the chip area and cost can be significantly reduced.

[0030] Therefore, it can be seen that the charge pump circuit 200 of this embodiment improves the problem of excessive voltage difference across the pump capacitor through the voltage generator circuit 220, thereby maintaining the performance and reliability of the charge pump circuit while significantly reducing chip area and cost, thus meeting the needs of high voltage applications.

[0031] Figure 3 shows a circuit diagram of a voltage generator circuit according to a first embodiment of the present invention. The voltage generator circuit 220-1 is used to generate a reference voltage VREF that is 5V lower than the power supply voltage VCC, so that MIM capacitors can be used to design pump-up capacitors C1 and C2 between the power supply voltage VCC and the reference voltage VREF. As shown in Figure 3, the voltage generator circuit 220-1 includes a PMOS transistor (P-Metal-Oxide-Semiconductor Field-Effect Transistor) Mp1, a reverse diode D1, a current source I1, a voltage regulator capacitor C3, a resistor R1, and a voltage regulator module 201. The cathode of the reverse diode D1 is connected to the power supply voltage VCC, and the anode of the reverse diode D1 is connected to the source of the PMOS transistor Mp1. The drain of the PMOS transistor Mp1 is connected to the reference ground VSS via the resistor R1. The voltage regulator module 201 is connected between the power supply voltage VCC and the gate of the PMOS transistor Mp1. The voltage regulator module 201 includes a PMOS transistor Mp2 and a reverse diode D2 connected in series. The source of PMOS transistor Mp2 is connected to the power supply voltage VCC, and the gate and drain of PMOS transistor Mp2 are connected to the cathode of reverse diode D2. The anode of reverse diode D2 is connected to the gate of PMOS transistor Mp1. A current source I1 is connected between the gate of PMOS transistor Mp1 and the reference ground VSS. A voltage regulator capacitor C3 is connected between the power supply voltage VCC and the source of PMOS transistor Mp1, and outputs the reference voltage VREF through the source of PMOS transistor Mp1.

[0032] In Figure 3, PMOS transistor Mp1 is a source follower transistor, employing a high-voltage PMOS transistor. Capacitor C3 is a Zener capacitor, and diodes D1 and D2 are Zener diodes. When the power supply voltage VCC exceeds approximately 6.5V, diode D2 is reverse-biased, with a reverse bias voltage of around 5.5V. Therefore, the gate voltage of PMOS transistor Mp1 can be approximately VCC - 5.5V - Vgs - Mp2. After passing through the source follower transistor Mp1, a reference voltage VREF of approximately VCC - 5V can be obtained. Diode D1 is used for clamping, ensuring that the reference voltage VREF does not fall significantly below the power supply voltage VCC.

[0033] In this embodiment, the voltage difference between the power supply voltage VCC and the reference voltage VREF is 5V. Therefore, the voltage generator circuit 220-1 can make the power rails of the clock signals CLK and CLKB between VCC-5V and VCC, so that the voltage difference across the pump capacitors C1 and C2 will not exceed 5V. Therefore, a MIM capacitor with a larger capacitance per unit area can be used to achieve this.

[0034] Figure 4 shows a circuit diagram of another voltage generator circuit according to a second embodiment of the present invention. In this embodiment, a closed-loop voltage generator scheme is provided. As shown in Figure 4, the voltage generator circuit 220-2 includes a buck module 211, a negative feedback module 212, and a current bias module 213. The buck module 211 is used to step down the power supply voltage VCC through at least one MOS diode to obtain the reference voltage VREF. The negative feedback module 212 is connected to the output terminal of the buck module 211 and the reference voltage VREF, and is used to stabilize the reference voltage VREF. The current bias module 213 is used to provide a bias current to the negative feedback module 212.

[0035] Furthermore, the step-down module 211 includes PMOS transistors Mp8 and Mp9 connected in series between the output terminals of the power supply voltage VCC and the reference voltage VREF. The gate and drain of PMOS transistors Mp8 and Mp9 are shorted to form a MOS diode structure.

[0036] The negative feedback module 212 includes NMOS transistors (N-Metal-Oxide-Semiconductor Field-Effect Transistors) Mn1 to Mn4, and PMOS transistors Mp5, Mp6, Mp7, and Mp9. The drain of NMOS transistor Mn1 is connected to the output terminal of the reference voltage VREF, the source of NMOS transistor Mn1 is connected to the reference ground VSS, the source of PMOS transistor Mp7 is connected to the power supply voltage VCC, the gate of PMOS transistor Mp7 is connected to the gate of PMOS transistor Mp8, the drain of PMOS transistor Mp7 is connected to the source of PMOS transistor Mp9, and the gate of PMOS transistor Mp9 is connected to the current bias module 213. The source of PMOS transistor Mp5 is connected to the power supply voltage VCC, the drain of PMOS transistor Mp5 is connected to the source of PMOS transistor Mp6, the drain of PMOS transistor Mp6 is connected to the gate of NMOS transistor Mn1, and the gates of PMOS transistors Mp5 and Mp6 are connected to the current bias module 213, thereby obtaining the bias current generated by the current bias module 213 in a mirror manner. NMOS transistors Mn3 and Mn4 form a current mirror structure. The gates of NMOS transistors Mn3 and Mn4, as well as the drain of NMOS transistor Mn4, are connected to the drain of PMOS transistor Mp9. The sources of NMOS transistors Mn3 and Mn4 are connected to the reference ground VSS. The drain of NMOS transistor Mn3 is connected to the source of NMOS transistor Mn2. The gate of NMOS transistor Mn2 is connected to the bias voltage VBN, and the drain of NMOS transistor Mn2 is connected to the gate of NMOS transistor Mn1.

[0037] In this embodiment, NMOS transistors Mn1 to Mn4 and PMOS transistors Mp5-Mp7 and Mp9 form a negative feedback loop. Through negative feedback adjustment, the reference voltage VREF is stabilized at VCC-Vgs_Mp8-Vgs_Mp10, meaning the reference voltage VREF equals the power supply voltage VCC minus two Vgs voltages. Furthermore, to ensure the stability of the negative feedback loop, the voltage generator circuit 220-2 in this embodiment also includes a Miller compensation capacitor C6 connected to the output terminal of the reference voltage VREF. One end of the Miller compensation capacitor C6 is connected to the common node of PMOS transistors Mp5 and Mp6, and the other end is connected to the output terminal of the reference voltage VREF.

[0038] The current bias module 213 includes PMOS transistors Mp3 and Mp4, and a current source I2. PMOS transistors Mp3 and Mp4 are connected in series as a MOS diode between the power supply voltage VCC and the first terminal of the current source I2. The second terminal of the current source I2 is connected to the reference ground VSS. Specifically, the source of PMOS transistor Mp3 is connected to the power supply voltage VCC, and its gate and drain are shorted together and connected to the gate of PMOS transistor Mp5. The source of PMOS transistor Mp4 is connected to the drain of PMOS transistor Mp3, and its gate and drain are shorted together and connected to the gates of PMOS transistors Mp6 and Mp9. The current source I2 is connected between the drain of PMOS transistor Mp4 and the reference ground VSS.

[0039] In this embodiment, NMOS transistor Mn1, PMOS transistor Mp6, and PMOS transistor Mp9 are high-voltage transistors, while the remaining transistors are low-voltage transistors. It should be noted that the terms "low-voltage MOS transistor" and "high-voltage MOS transistor" are generally relative. For example, transistors can be classified as high-voltage or low-voltage based on their turn-on threshold voltage. For instance, the turn-on threshold voltage of a low-voltage MOS transistor is typically around 0.7V, while that of a high-voltage MOS transistor is typically around 1.2V.

[0040] In this embodiment, the voltage difference between the power supply voltage VCC and the reference voltage VREF is 2*Vgs. Therefore, the voltage generator circuit 220-2 can make the power rails of the clock signals CLK and CLKB between VCC-2*Vgs and VCC, so that the voltage difference across the pump capacitors C1 and C2 will not exceed 2*Vgs. Therefore, a MIM capacitor with a larger capacitance per unit area can be used to achieve this.

[0041] In summary, the charge pump circuit of this embodiment includes a boost module, a voltage generator circuit, and an oscillator circuit. The voltage generator circuit ensures that the power rail of the clock signal generated by the oscillator circuit is between the reference voltage and the power supply voltage, and the voltage difference between the power supply voltage and the reference voltage is less than a set threshold. This prevents the voltage difference across the boost capacitor from exceeding the set threshold. In this case, a MIM capacitor can be used as the boost capacitor. Since the area of ​​a MIM capacitor is 1 / 5 that of a MOM capacitor for the same capacitance value, and if the charge pump output voltage VP needs to drive a large load, the values ​​of the boost capacitors C1 and C2 need to be relatively large to reduce internal resistance. Therefore, the circuit of this invention has the beneficial effect of saving more chip area under heavier loads, thus significantly reducing chip area and cost in high-voltage, high-load applications. Therefore, the charge pump circuit of this embodiment can improve the problem of excessive voltage difference across the boost capacitor, thereby maintaining the performance and reliability of the charge pump circuit while significantly reducing chip area and cost, thus meeting the requirements of high-voltage applications.

[0042] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0043] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.

Claims

1. A charge pump circuit, comprising: The boost module is used to perform voltage boosting operation on the power supply voltage in response to a first clock signal and a second clock signal to generate a boosted voltage, wherein the first clock signal and the second clock signal are differential signals; A voltage generator circuit is used to generate a reference voltage based on the power supply voltage, wherein the voltage difference between the power supply voltage and the reference voltage is less than a set threshold. as well as An oscillator circuit, having a power supply node connected to the power supply voltage and the reference voltage, is used to generate the first clock signal and the second clock signal. The potentials of the first clock signal and the second clock signal switch between the power supply voltage and the reference voltage.

2. The charge pump circuit according to claim 1, wherein, The voltage generator circuit includes: The first reverse diode, the cathode of the first reverse diode is connected to the power supply voltage; The first transistor constituting the source follower, wherein the first terminal of the first transistor is connected to the anode of the first reverse diode; A voltage regulator module is connected between the power supply voltage and the control terminal of the first transistor; A first current source is connected between the control terminal of the first transistor and the reference ground. A first resistor is connected between the second terminal of the first transistor and the reference ground; and A first voltage-regulating capacitor is connected between the power supply voltage and the first terminal of the first transistor and outputs the reference voltage.

3. The charge pump circuit according to claim 2, wherein, The voltage regulator module includes: A second transistor and a second reverse diode are connected in series. The first terminal of the second transistor is connected to the power supply voltage. The control terminal and the second terminal of the second transistor are connected to the cathode of the second reverse diode. The anode of the second reverse diode is connected to the control terminal of the first transistor.

4. The charge pump circuit according to claim 3, wherein, The first reverse diode and the second reverse diode are Zener diodes.

5. The charge pump circuit according to claim 1, wherein, The voltage generator circuit includes: A step-down module is used to step down the power supply voltage using at least one MOS diode to obtain the reference voltage; A negative feedback module, connected to the output of the step-down module and the reference voltage, is used to stabilize the reference voltage; and A current bias module is used to provide bias current to the negative feedback module.

6. The charge pump circuit according to claim 5, wherein, The step-down module includes: A third transistor and a fourth transistor are connected in series between the output terminals of the power supply voltage and the reference voltage, and the third transistor and the fourth transistor are connected to form a MOS diode.

7. The charge pump circuit according to claim 6, wherein, The negative feedback module includes: The fifth transistor has its first terminal connected to the output terminal of the reference voltage and its second terminal connected to reference ground. The sixth transistor has its first terminal connected to the power supply voltage and its control terminal connected to the control terminal of the third transistor. A seventh transistor, wherein the first terminal of the seventh transistor is connected to the second terminal of the sixth transistor; The eighth transistor, wherein the first terminal of the eighth transistor is connected to the power supply voltage; The ninth transistor has its first terminal connected to the second terminal of the eighth transistor, and its second terminal connected to the control terminal of the fifth transistor. The control terminals of the seventh, eighth, and ninth transistors are connected to the current bias module, thereby obtaining the bias current through mirroring. A tenth and eleventh transistor with a current mirror structure, wherein the control terminals of the tenth and eleventh transistors and the first terminal of the eleventh transistor are connected to the second terminal of the seventh transistor, and the second terminals of the tenth and eleventh transistors are connected to the reference ground; and The twelfth transistor has its first terminal connected to the control terminal of the fifth transistor, the control terminal of the twelfth transistor being connected to a bias voltage, and its second terminal connected to the first terminal of the tenth transistor.

8. The charge pump circuit according to claim 7, wherein, The current biasing module includes: The thirteenth transistor has its first terminal connected to the power supply voltage, and its control terminal and second terminal short-circuited and connected to the control terminal of the eighth transistor. The fourteenth transistor, wherein its first terminal is connected to the second terminal of the thirteenth transistor, its control terminal and second terminal are short-circuited, and it is connected to the control terminals of the seventh and ninth transistors; and A second current source is connected between the second terminal of the fourteenth transistor and the reference ground.

9. The charge pump circuit according to claim 8, wherein, The voltage generator circuit also includes: The second voltage-regulating capacitor is connected between the first terminal of the seventh transistor and the output terminal of the reference voltage; The third voltage-regulating capacitor is connected between the output terminals of the power supply voltage and the reference voltage; A third reverse-connected diode, wherein the cathode of the third reverse-connected diode is connected to the power supply voltage, and the anode of the third reverse-connected diode is connected to the output terminal of the reference voltage; and A Miller compensation capacitor is connected between the first terminal of the fourteenth transistor and the output terminal of the reference voltage.

10. The charge pump circuit according to claim 8, wherein, The fifth transistor, the seventh transistor, and the ninth transistor are high-voltage transistors.

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