Copper-ceramic joint and insulated circuit board

Abstract

The copper-ceramic joint of the present invention is a copper-ceramic joint (10) formed by joining a copper component (12, 13) made of copper or copper alloy and a ceramic component (11). At the joint interface between the ceramic component (11) and the copper component (12, 13), the distance between the ceramic component (11) and the copper component (12, 13) is in the range of 3 μm or more and 30 μm or less at the end of the copper component (12, 13), and the porosity of the end region (E) of the copper component (12, 13) is 10% or less.

Description

Technical Field

[0001] The present invention relates to a copper-ceramic bonding body formed by joining a copper component made of copper or a copper alloy and a ceramic component, and an insulating circuit board formed by bonding a copper plate made of copper or a copper alloy to the surface of a ceramic substrate.

[0002] This application claims priority based on Japanese Patent Application No. 2021-125531, filed on July 30, 2021, the contents of which are incorporated herein by reference. Background Technology

[0003] Power modules, LED modules, and thermoelectric modules are structures formed by bonding power semiconductor elements, LED elements, and thermoelectric elements onto an insulating circuit board on one side of an insulating layer where a circuit layer made of conductive material is formed.

[0004] For example, power semiconductor devices used for controlling high-power applications such as wind power generation, electric vehicles, and hybrid electric vehicles generate a lot of heat during operation. Therefore, as the substrate on which these power semiconductor devices are mounted, the following insulating circuit board has been widely used. This insulating circuit board includes: a ceramic substrate; a circuit layer formed by bonding a metal plate with excellent conductivity to one side of the ceramic substrate; and a heat dissipation metal layer formed by bonding a metal plate to the other side of the ceramic substrate.

[0005] For example, Patent Document 1 discloses an insulating circuit board in which a circuit layer and a metal layer are formed by bonding copper plates to one and the other sides of a ceramic substrate. In Patent Document 1, copper plates are placed on one and the other sides of a ceramic substrate with an Ag-Cu-Ti solder between them, and the copper plates are bonded by heat treatment (so-called active metal brazing).

[0006] Furthermore, Patent Document 2 proposes a power module substrate that uses a bonding material containing Ag and Ti to bond a copper plate made of copper or a copper alloy and a ceramic substrate made of AlN or Al2O3.

[0007] Furthermore, Patent Document 3 discloses a power module substrate that uses a solder composed of Al-Si, Al-Ge, Al-Cu, Al-Mg, or Al-Mn alloys to bond an aluminum plate or aluminum alloy to a ceramic substrate. In this Patent Document 3, protrusions are formed around a circuit layer formed on one side of the ceramic substrate and a heat dissipation layer formed on the other side. This ensures the insulation between the circuit layer and the heat dissipation layer and increases the heat capacity of both.

[0008] Patent Document 1: Japanese Patent No. 3211856 (B)

[0009] Patent Document 2: Japanese Patent No. 5757359 (B)

[0010] Patent Document 3: Japanese Patent No. 5957862 (B)

[0011] However, there has been a recent trend of increasing heat generation temperature of semiconductor devices mounted on insulating circuit boards. As a result, insulating circuit boards are required to have higher thermal cycling reliability than ever before, capable of withstanding severe thermal cycling.

[0012] In the case of an insulating circuit board formed by bonding a copper plate and a ceramic substrate, as described in Patent Document 3, when a protrusion is formed in the circuit layer, thermal stress is concentrated at the end of the circuit layer when subjected to thermal cycling, and the bonding reliability may decrease.

[0013] On the other hand, when the thickness of the bonding layer at the end is increased in order to ensure the strength of the copper component's end, the bonding material disposed between the copper component and the ceramic component may overflow, potentially causing a defect known as "solder stain". Summary of the Invention

[0014] The present invention was made in view of the above circumstances, and its object is to provide a copper-ceramic joint with excellent thermal cycling reliability and sufficient suppression of solder stains, and an insulating circuit board made of the copper-ceramic joint.

[0015] To address the aforementioned issues, one aspect of the present invention relates to a copper-ceramic joint formed by joining a copper component made of copper or a copper alloy and a ceramic component. The joint is characterized in that, at the interface between the ceramic component and the copper component, the distance between the ceramic component and the copper component is in the range of 3 μm to 30 μm at the end of the copper component, and the porosity of the end region of the copper component is 10% or less.

[0016] According to one aspect of the present invention, the copper-ceramic joint has a sufficient thickness of the bonding layer at the end face because the distance between the ceramic component and the copper component at the bonding interface is 3 μm or more at the end of the copper component, and the porosity of the end region of the copper component is less than 10%. This ensures sufficient end strength. Therefore, cracking or peeling of the ceramic component under thermal cycling is suppressed.

[0017] Furthermore, since the distance between the ceramic component and the copper component is less than 30 μm at the end of the copper component, the overflow of bonding material can be suppressed, and the generation of "solder stains" can be suppressed.

[0018] In this embodiment of the invention, a copper-ceramic joint preferably has an active metal compound layer formed on the ceramic component side at the interface between the ceramic component and the copper component, wherein the thickness t1 of the active metal compound layer at the end of the copper component is [not specified]. A The thickness t1 of the active metal compound layer at the center of the copper component B Within the range of 0.05 μm and 1.2 μm, the thickness ratio t1 A / t1 B It is in the range of 0.7 or higher and 1.4 or lower.

[0019] At this time, due to the thickness t1 of the active metal compound layer at the end of the copper component... A The thickness t1 of the active metal compound layer at the center of the copper component B Within the range of 0.05μm to 1.2μm, the ceramic component and the copper component are reliably and firmly bonded by the active metal, and the hardening of the bonding interface is further suppressed.

[0020] Furthermore, due to the thickness being greater than t1 A / t1 B Within the range of 0.7 to 1.4, the hardness of the joint interface at the ends and center of the copper component does not differ significantly, which further suppresses the generation of cracks in the ceramic component during thermal cycling.

[0021] Furthermore, in the copper-ceramic joint according to one aspect of the present invention, preferably, an Ag-Cu alloy layer is formed on the copper component side at the joint interface between the ceramic component and the copper component, and the thickness t2 of the Ag-Cu alloy layer at the end of the copper component is... A and the thickness t2 of the Ag-Cu alloy layer at the center of the copper component. B Within the range of 3μm and above to 30μm, the thickness ratio t2 A / t2 B It is in the range of 0.7 or higher and 1.4 or lower.

[0022] At this time, due to the thickness t2 of the Ag-Cu alloy layer at the end of the copper component... A and the thickness t2 of the Ag-Cu alloy layer at the center of the copper component. B Within the range of 3μm to 30μm, the Ag in the bonding material reacts sufficiently with the copper component, thereby reliably and firmly bonding the ceramic component to the copper component and further suppressing hardening of the bonding interface.

[0023] Furthermore, due to the thickness being greater than t2 A / t2 B Within the range of 0.7 to 1.4, the hardness of the joint interface at the ends and center of the copper component does not differ significantly, which further suppresses the generation of cracks in the ceramic component during thermal cycling.

[0024] The insulating circuit board according to one aspect of the present invention is an insulating circuit board formed by bonding a copper plate made of copper or a copper alloy to the surface of a ceramic substrate. The invention is characterized in that, at the bonding interface between the ceramic substrate and the copper plate, the distance between the ceramic substrate and the copper plate at the end of the copper plate is in the range of 3 μm or more and 30 μm or less, and the porosity of the end region of the copper plate is 10% or less.

[0025] According to one aspect of the present invention, the insulating circuit substrate has a sufficient thickness of the bonding layer at the end face because the distance between the ceramic substrate and the copper plate at the interface between the ceramic substrate and the copper plate is 3 μm or more at the end of the copper plate, and the porosity of the end region of the copper plate is less than 10%. This ensures sufficient end strength. Therefore, cracking or peeling of the ceramic substrate under thermal cycling loads can be suppressed.

[0026] Furthermore, since the distance between the ceramic substrate and the copper plate is less than 30 μm at the end of the copper plate, the overflow of bonding material can be suppressed, and the generation of "solder stains" can be suppressed.

[0027] In this invention, in the insulating circuit substrate, the thickness t1 of the active metal compound layer at the end of the copper plate is preferably specified. A and the thickness t1 of the active metal compound layer at the center of the copper plate. B Within the range of 0.05 μm and 1.2 μm, the thickness ratio t1 A / t1 B It is in the range of 0.7 or higher and 1.4 or lower.

[0028] At this time, due to the thickness t1 of the active metal compound layer at the end of the copper plate... A The thickness t1 of the active metal compound layer at the center of the copper plate B Within the range of 0.05μm to 1.2μm, the ceramic substrate and the copper plate are reliably and firmly bonded by the active metal, and the hardening of the bonding interface is further suppressed.

[0029] Furthermore, due to the thickness being greater than t1 A / t1 BWithin the range of 0.7 to 1.4, the hardness of the bonding interface does not differ significantly between the ends and the center of the copper plate, thus further suppressing the generation of cracks in the ceramic substrate during thermal cycling.

[0030] Furthermore, in the insulating circuit substrate according to one aspect of the present invention, preferably, an Ag-Cu alloy layer is formed on the copper plate side at the interface between the ceramic substrate and the copper plate, and the thickness t2 of the Ag-Cu alloy layer at the end of the copper plate is... A and the thickness t2 of the Ag-Cu alloy layer at the center of the copper plate B Within the range of 3μm and above to 30μm, the thickness ratio t2 A / t2 B It is in the range of 0.7 or higher and 1.4 or lower.

[0031] At this time, due to the thickness t2 of the Ag-Cu alloy layer at the end of the copper plate... A and the thickness t2 of the Ag-Cu alloy layer at the center of the copper plate B Within the range of 3μm to 30μm, the Ag in the bonding material reacts sufficiently with the copper plate, thereby reliably and firmly bonding the ceramic substrate and the copper plate, and further suppressing the hardening of the bonding interface.

[0032] Furthermore, due to the thickness being greater than t2 A / t2 B Within the range of 0.7 to 1.4, the hardness of the bonding interface does not differ significantly between the ends and the center of the copper plate, thus further suppressing the generation of cracks in the ceramic substrate during thermal cycling.

[0033] According to the present invention, a copper-ceramic bond with excellent thermal cycling reliability and sufficient suppression of solder contamination and an insulating circuit board made of the copper-ceramic bond can be provided. Attached Figure Description

[0034] Figure 1 This is a schematic diagram illustrating a power module using an insulating circuit board according to an embodiment of the present invention.

[0035] Figure 2 This is an enlarged illustration of the ends of the circuit layer and metal layer of the insulating circuit board according to an embodiment of the present invention.

[0036] Figure 3A This is an enlarged illustration of the interface between the circuit layer and the metal layer of the insulating circuit board and the ceramic substrate according to the embodiments of the present invention.

[0037] Figure 3BIs Figure 3A An enlarged view of the end of the bonding interface in an insulating circuit board.

[0038] Figure 3C Is Figure 3A An enlarged view of the central portion of the bonding interface in an insulating circuit board.

[0039] Figure 4 This is a flowchart of a method for manufacturing an insulating circuit board according to an embodiment of the present invention.

[0040] Figure 5 This is a schematic diagram illustrating a method for manufacturing an insulating circuit board according to an embodiment of the present invention. Detailed Implementation

[0041] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0042] The copper-ceramic bonding body involved in this embodiment is an insulating circuit board 10 formed by bonding a ceramic substrate 11, which is a ceramic component made of ceramic, and copper plates 42 (circuit layer 12) and 43 (metal layer 13), which are copper components made of copper or copper alloy. Figure 1 A power module 1 equipped with the insulating circuit board 10 of this embodiment is shown.

[0043] The power module 1 includes: an insulating circuit board 10 provided with a circuit layer 12 and a metal layer 13; on one side of the circuit layer 12 (on Figure 1 The semiconductor element 3 (top) is bonded via bonding layer 2; and the semiconductor element 3 is disposed on the other side of metal layer 13 (in... Figure 1 The radiator 5 is located on the lower side (in the middle).

[0044] Semiconductor element 3 is made of semiconductor material such as Si. Semiconductor element 3 is bonded to circuit layer 12 via bonding layer 2.

[0045] The bonding layer 2 is composed of, for example, Sn-Ag, Sn-In, or Sn-Ag-Cu solder materials.

[0046] The heat sink 5 is used to dissipate heat from the aforementioned insulating circuit board 10. The heat sink 5 is made of copper or a copper alloy; in this embodiment, it is made of phosphorus-deoxidized copper. A flow path for cooling fluid is provided in the heat sink 5.

[0047] In this embodiment, the heat sink 5 and the metal layer 13 are bonded by a solder layer 7 made of solder material. The solder layer 7 is made of, for example, Sn-Ag, Sn-In, or Sn-Ag-Cu solder material.

[0048] And, as Figure 1As shown, the insulating circuit board 10 of this embodiment includes: a ceramic substrate 11; and a surface disposed on one side of the ceramic substrate 11 (on...). Figure 1 The circuit layer 12 (top) and the circuit layer disposed on the other side of the ceramic substrate 11 (on the top). Figure 1 The metal layer 13 (with the middle layer below) is located below.

[0049] The ceramic substrate 11 is made of ceramics such as silicon nitride (Si3N4), aluminum nitride (AlN), and alumina (Al2O3), which have excellent insulation and heat dissipation properties. In this embodiment, the ceramic substrate 11 is made of aluminum nitride (AlN), which has particularly excellent heat dissipation properties. Furthermore, the thickness of the ceramic substrate 11 is set, for example, in the range of 0.2 mm or more and 1.5 mm or less; in this embodiment, it is set to 0.635 mm.

[0050] like Figure 5 As shown, the circuit layer 12 is located on one side of the ceramic substrate 11 (on... Figure 5 The middle part (top) is formed by joining a copper plate 42 made of copper or a copper alloy.

[0051] In this embodiment, the circuit layer 12 is formed by bonding an oxygen-free copper rolled plate onto a ceramic substrate 11.

[0052] Furthermore, the thickness of the copper plate 42 that forms the circuit layer 12 is set in the range of 0.1 mm or more and 2.0 mm or less; in this embodiment, it is set to 0.6 mm.

[0053] like Figure 5 As shown, the metal layer 13 passes through the other side of the ceramic substrate 11 (on the other side). Figure 5 (The middle part is below) is formed by joining copper plates 43 made of copper or copper alloys.

[0054] In this embodiment, the metal layer 13 is formed by bonding an oxygen-free copper rolled plate onto a ceramic substrate 11.

[0055] Furthermore, the thickness of the copper plate 43 that forms the metal layer 13 is set in the range of 0.1 mm or more and 2.0 mm or less; in this embodiment, it is set to 0.6 mm.

[0056] And, as Figure 2 As shown, in the insulating circuit board 10 of this embodiment, at the interface between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13, the distance h between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13 is in the range of 3 μm or more and 30 μm or less at the ends of the circuit layer 12 and the metal layer 13.

[0057] In addition, such as Figure 2As shown, in the insulating circuit board 10 of this embodiment, at the interface between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13, the porosity of the end region E of the circuit layer 12 and the metal layer 13 is 10% or less.

[0058] Here, as Figure 2 As shown, the end region in this embodiment refers to the following region: that is, in a cross-sectional view of the interface between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13, the intersection point P of the perpendicular line from the end face position of the circuit layer 12 and the metal layer 13 at a position where the thickness of the circuit layer 12 and the metal layer 13 is 1 / 3 of the thickness, and the point P of the intersection point with the ceramic substrate 11, the region has a height of 30 μm from the surface of the ceramic substrate 11 toward the circuit layer 12 and the metal layer 13 and a width of 400 μm along the surface of the ceramic substrate 11 toward the center of the circuit layer 12 and the metal layer 13.

[0059] Furthermore, when the thickness of the circuit layer 12 and the metal layer 13 is less than 90 μm, the end region refers to the following region: that is, the region is defined as the region with a height of 1 / 3 of the thickness of the circuit layer 12 and the metal layer 13 extending from the surface of the ceramic substrate 11 toward the circuit layer 12 and the metal layer 13 side, taking the intersection point P of the vertical line from the end face position of the circuit layer 12 and the metal layer 13 at a position where the thickness of the circuit layer 12 and the metal layer 13 is 1 / 3 of the height of the circuit layer 12 and the metal layer 13 side, and a width of 400 μm extending from the surface of the ceramic substrate 11 toward the central portion of the circuit layer 12 and the metal layer 13.

[0060] Furthermore, the porosity is calculated as follows: the region in the aforementioned end region where no metal constituting the circuit layer 12 and the metal layer 13 exists is defined as a pore portion, and the proportion of the pore portion in the aforementioned end region is defined as the porosity.

[0061] And, as Figure 3A , Figure 3B , Figure 3C As shown, in this embodiment, preferably at the interface between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13, an active metal compound layer 21 and an Ag-Cu alloy layer 22 are formed sequentially from the ceramic substrate 11 side.

[0062] Alternatively, the active metal compound layer 21 can be considered part of the ceramic substrate (ceramic component) 11. The Ag-Cu alloy layer 22 can also be considered part of the circuit layer (copper component) 12 and the metal layer (copper component) 13. Therefore, the interface between the ceramic substrate 11 and the circuit layer 12 and metal layer 13 (copper plates 42, 43) is the interface between the active metal compound layer 21 and the Ag-Cu alloy layer 22. When the Ag-Cu alloy layer 22 is absent, the interface between the ceramic substrate 11 and the circuit layer 12 and metal layer 13 (copper plates 42, 43) is the interface between the active metal compound layer 21 and the circuit layer 12 and metal layer 13 (copper plates 42, 43).

[0063] Here, as Figure 3A As shown, in the insulating circuit board 10 of this embodiment, the interface structure at the end A and the central portion B of the bonding interface between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13 is defined as follows.

[0064] In addition, in this embodiment, such as Figure 3A As shown, the end A of the interface between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13 is the following region: that is, in the cross section along the stacking direction of the circuit layer 12 and the metal layer 13 and the ceramic substrate 11, the region extends 200 μm inward from the end of the circuit layer 12 and the metal layer 13 in the width direction.

[0065] And, as Figure 3A As shown, the central portion B of the interface between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13 is a region that is 200 μm wide, including the center of the width direction of the circuit layer 12 and the metal layer 13 in the cross section along the stacking direction of the ceramic substrate 11 and the circuit layer 12 and the metal layer 13.

[0066] In this embodiment, the thickness t1 of the active metal compound layer 21A formed at the end A of the interface between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13 is preferably [missing information]. A The thickness t1 of the active metal compound layer 21B formed at the central portion B of the interface between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13. B In the range of 0.05 μm and 1.2 μm, their thickness is greater than t1. A / t1 B It is in the range of 0.7 or higher and 1.4 or lower.

[0067] Here, the active metal compound layers 21A and 21B are layers composed of compounds of active metals (selected from one or more of Ti, Zr, Nb, and Hf) used in the bonding material 45. More specifically, when the ceramic substrate is composed of silicon nitride (Si3N4) or aluminum nitride (AlN), it becomes a layer composed of nitrides of these active metals; when the ceramic substrate is aluminum oxide (Al2O3), it becomes a layer composed of oxides of these active metals. The active metal compound layers 21A and 21B are formed by the aggregation of active metal compound particles. The average particle size is 10 nm or more and 100 nm or less.

[0068] Furthermore, in this embodiment, the bonding material 45 contains Ti as an active metal. Since the ceramic substrate 11 is made of aluminum nitride, the active metal compound layers 21 (21A, 21B) are made of titanium nitride (TiN). That is, they are formed by the aggregation of titanium nitride (TiN) particles with an average particle size of 10 nm or more and 100 nm or less.

[0069] Furthermore, in this embodiment, it is preferable that the thickness t2 of the Ag-Cu alloy layer 22A formed at the end A of the interface between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13 is [not specified]. A The thickness t2 of the Ag-Cu alloy layer 22B formed at the central portion B of the interface between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13. B In the range of 3μm or more and 30μm or less, their thickness is greater than t2. A / t2 B It is in the range of 0.7 or higher and 1.4 or lower.

[0070] The following is for reference. Figure 4 and Figure 5 The manufacturing method of the insulating circuit board 10 according to this embodiment will be described.

[0071] (Joint material installation process S01)

[0072] A copper plate 42 is prepared to become a circuit layer 12 and a copper plate 43 is prepared to become a metal layer 13. Here, in both the copper plate 42 which becomes a circuit layer 12 and the copper plate 43 which becomes a metal layer 13, a chamfer is formed on the periphery of the surface facing the ceramic substrate 11.

[0073] Furthermore, a bonding material 45 is applied to the bonding surface of the copper plate 42, which forms the circuit layer 12, and the copper plate 43, which forms the metal layer 13, and then dried. The coating thickness of the paste-like bonding material 45 is preferably set in the range of 10 μm or more and 50 μm or less after drying.

[0074] In this embodiment, the paste-like bonding material 45 is applied by screen printing.

[0075] The bonding material 45 contains Ag and an active metal (selected from one or more of Ti, Zr, Nb, and Hf). In this embodiment, an Ag-Ti solder (Ag-Cu-Ti solder) is used as the bonding material 45. Furthermore, as the Ag-Ti solder (Ag-Cu-Ti solder), a solder with the following composition is preferably used, for example: the solder contains Cu in the range of 0% to 45% by mass and Ti as an active metal in the range of 0.5% to 20% by mass, with the remainder being Ag and unavoidable impurities.

[0076] Here, for the coated bonding material 45, the equivalent film thickness of Ag and the mass ratio of Ag to active metal (Ag / active metal) are adjusted. Therefore, in the pressurization and heating process S03 described later, the absolute amount and flowability of the generated Ag-Cu liquid phase can be controlled.

[0077] Specifically, it is preferable to set the equivalent film thickness of Ag to 2.5 μm or more, and more preferably to 3.5 μm or more. On the other hand, it is preferable to set the equivalent film thickness of Ag to 20 μm or less, and more preferably to 15 μm or less.

[0078] Furthermore, it is preferable to set the mass ratio of Ag to active metal (Ag / active metal) to 8 or more, more preferably 12 or more. On the other hand, it is preferable to set the mass ratio of Ag to active metal (Ag / active metal) to 60 or less, more preferably 45 or less.

[0079] Furthermore, the specific surface area of ​​the Ag powder contained in the bonding material 45 is preferably 0.15 m². 2 / g or more, preferably 0.25m 2 / g or more, further preferably 0.40m 2 / g or more. On the other hand, the specific surface area of ​​the Ag powder contained in the bonding material 45 is preferably 1.40m². 2 / g or less, more preferably 1.00m 2 / g or less, more preferably 0.75m 2 / g or less.

[0080] Furthermore, regarding the particle size of the Ag powder contained in the paste-like bonding material 45, D10 is preferably in the range of 0.7 μm or more and 3.5 μm or less, and D100 is in the range of 4.5 μm or more and 23 μm or less. In the particle size distribution obtained by laser diffraction scattering particle size distribution measurement method, D10 is the particle size with a cumulative frequency of 10% based on volume, and D100 is the particle size with a cumulative frequency of 100% based on volume.

[0081] (Lamination process S02)

[0082] Next, on one side of the ceramic substrate 11 (on Figure 5 The copper plate 42 (top) is laminated to form the circuit layer 12 via bonding material 45, and on the other side of the ceramic substrate 11 (on the top) Figure 5 The copper plate 43 (bottom) is laminated to form the metal layer 13 via bonding material 45. In addition, since chamfered portions are formed at the periphery of the copper plate 42 (which forms the circuit layer 12) and the copper plate 43 (which forms the metal layer 13), a gap is formed at the end of the ceramic substrate 11.

[0083] (Pressure and heating process S03)

[0084] Next, while the copper plate 42, ceramic substrate 11 and copper plate 43 are under pressure, they are heated in a furnace under vacuum atmosphere to melt the bonding material 45.

[0085] Here, the heating temperature in the pressurization and heating process S03 is preferably in the range of 800°C or higher and 850°C or lower. The total temperature integral value in the heating process from 780°C to the heating temperature and the holding process at the heating temperature is preferably in the range of 7°C·h or higher and 80°C·h or lower.

[0086] Furthermore, the pressurization load in the pressurization and heating process S03 is preferably in the range of 0.029 MPa or more and 2.94 MPa or less.

[0087] Furthermore, the vacuum level in the pressurization and heating process S03 is preferably 1×10⁻⁶. -6 Pa or higher and 5×10 -2 Within the range below Pa.

[0088] (Cooling process S04)

[0089] Furthermore, after the pressurization and heating process S03, cooling is performed to solidify the molten bonding material 45, which will become the copper plate 42 of the circuit layer 12 and the ceramic substrate 11, and the ceramic substrate 11 and the copper plate 43 of the metal layer 13 are bonded together.

[0090] Furthermore, the cooling rate in this cooling process S04 is preferably in the range of 2°C / min or higher and 20°C / min or lower. Here, the cooling rate refers to the cooling rate from the heating temperature to the Ag-Cu eutectic temperature, i.e., 780°C.

[0091] As described above, the insulating circuit board 10 of this embodiment is manufactured by means of a bonding material preparation process S01, a lamination process S02, a pressurization and heating process S03, and a cooling process S04.

[0092] (Radiator joining process S05)

[0093] Next, the heat sink 5 is bonded to the other side of the metal layer 13 of the insulating circuit board 10.

[0094] The insulating circuit board 10 and the heat sink 5 are stacked with solder material and placed in a heating furnace. The insulating circuit board 10 and the heat sink 5 are soldered together through the solder layer 7.

[0095] (Semiconductor device bonding process S06)

[0096] Next, the semiconductor element 3 is bonded to one side of the circuit layer 12 of the insulating circuit board 10 by soldering.

[0097] Through the above processes, a product is manufactured. Figure 1 The power module 1 shown.

[0098] According to the insulating circuit board 10 (copper-ceramic bond) of this embodiment with the structure described above, since the distance h between the ceramic substrate 11 and the circuit layer 12 and metal layer 13 at the bonding interface between the ceramic substrate 11 and the circuit layer 12 and metal layer 13 is 3 μm or more at the ends of the circuit layer 12 and metal layer 13, and the porosity of the end regions of the circuit layer 12 and metal layer 13 is 10% or less, the thickness of the bonding layer at the end face is ensured, and the strength of the ends of the circuit layer 12 and metal layer 13 can be sufficiently ensured. Therefore, cracking or peeling of the ceramic substrate 11 under load thermal cycling can be suppressed.

[0099] Furthermore, since the distance h between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13 is less than 30 μm at the ends of the circuit layer 12 and the metal layer 13, the overflow of the bonding material 45 can be suppressed, and the generation of "solder stains" can be suppressed.

[0100] Furthermore, the distance h between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13 is preferably 5 μm or more at the ends of the circuit layer 12 and the metal layer 13, and more preferably 8 μm or more. On the other hand, the distance h between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13 is preferably 25 μm or less at the ends of the circuit layer 12 and the metal layer 13, and more preferably 20 μm or less.

[0101] Furthermore, at the interface between the ceramic substrate 11 and the circuit layer 12 and the metal layer 13, the porosity of the end region E of the circuit layer 12 and the metal layer 13 is preferably 8% or less, more preferably 5% or less.

[0102] Furthermore, in this embodiment, the thickness t1 of the active metal compound layer 21A formed at the end A of the circuit layer 12 and the metal layer 13 is... A The thickness t1 of the active metal compound layer 21B formed in the central portion B of the circuit layer 12 and the metal layer 13. BWithin the range of 0.05μm and 1.2μm, the ceramic substrate 11 is reliably and firmly bonded to the circuit layer 12 and the metal layer 13 through the active metal, and the hardening of the bonding interface is further suppressed.

[0103] Furthermore, in order to further and more firmly bond the ceramic substrate 11 to the circuit layer 12 and the metal layer 13, it is preferable that the thickness t1 of the active metal compound layer 21A formed at the end A of the circuit layer 12 and the metal layer 13 is [not specified]. A The thickness t1 of the active metal compound layer 21B formed in the central portion B of the circuit layer 12 and the metal layer 13. B It is set to 0.08μm or more, and more preferably 0.15μm or more.

[0104] Furthermore, in order to reliably suppress hardening of the bonding interface, it is preferable to have a thickness t1 of the active metal compound layer 21A formed at the end A of the circuit layer 12 and the metal layer 13. A The thickness t1 of the active metal compound layer 21B formed in the central portion B of the circuit layer 12 and the metal layer 13. B It is set to 1.0 μm or less, and more preferably to 0.6 μm or less.

[0105] Furthermore, in this embodiment, when the thickness t1 of the active metal compound layer 21A formed at the end A of the circuit layer 12 and the metal layer 13 is... A The thickness t1 of the active metal compound layer 21B formed in the central portion B of the circuit layer 12 and the metal layer 13. B The thickness is greater than t1 A / t1 B When the hardness is in the range of 0.7 or higher and 1.4 or lower, the hardness of the bonding interface at the end A and the central part B of the circuit layer 12 and the metal layer 13 will not produce a large hardness difference, which can further suppress the generation of cracks in the ceramic substrate 11 under load thermal cycling.

[0106] Furthermore, in order to further suppress the formation of cracks in the ceramic substrate 11 during thermal cycling, it is more preferable to increase the thickness t1 of the active metal compound layer 21A formed at the end A of the circuit layer 12 and the metal layer 13. A The thickness t1 of the active metal compound layer 21B formed in the central portion B of the circuit layer 12 and the metal layer 13. B The ratio of t1 A / t1 B The value is set within the range of 0.8 or higher and 1.2 or lower, and more preferably within the range of 0.9 or higher and 1.1 or lower.

[0107] Furthermore, in this embodiment, the thickness t2 of the Ag-Cu alloy layer 22A formed at the end A of the circuit layer 12 and the metal layer 13 is... AThe thickness t2 of the Ag-Cu alloy layer 22B formed in the central portion B of the circuit layer 12 and the metal layer 13. B Within the range of 3μm or more and 30μm or less, the Ag of the bonding material 45 described later reacts sufficiently with the circuit layer 12 and the metal layer 13, thereby reliably and firmly bonding the ceramic substrate 11 with the circuit layer 12 and the metal layer 13, and further suppressing the hardening of the bonding interface.

[0108] Furthermore, in order to further and more firmly bond the ceramic substrate 11 to the circuit layer 12 and the metal layer 13, it is preferable that the thickness t2 of the Ag-Cu alloy layer 22A formed at the end A of the circuit layer 12 and the metal layer 13 is [not specified]. A The thickness t2 of the Ag-Cu alloy layer 22B formed in the central portion B of the circuit layer 12 and the metal layer 13. B It should be set to 5μm or larger, and more preferably 7μm or larger.

[0109] Furthermore, in order to further suppress excessive hardening of the bonding interface, it is preferable to limit the thickness t2 of the Ag-Cu alloy layer 22A formed at the end A of the circuit layer 12 and the metal layer 13. A The thickness t2 of the Ag-Cu alloy layer 22B formed in the central portion B of the circuit layer 12 and the metal layer 13. B It is set to 25μm or less, and more preferably to 20μm or less.

[0110] Furthermore, in this embodiment, the thickness t2 of the Ag-Cu alloy layer 22A formed at the end A of the circuit layer 12 and the metal layer 13 is... A The thickness t2 of the Ag-Cu alloy layer 22B formed in the central portion B of the circuit layer 12 and the metal layer 13. B The ratio of t2 A / t2 B When the hardness is in the range of 0.7 or higher and 1.4 or lower, the hardness of the bonding interface at the end A and the central part B of the circuit layer 12 and the metal layer 13 will not produce a large hardness difference, which can further suppress the generation of cracks in the ceramic substrate under load thermal cycling.

[0111] Furthermore, in order to further suppress the formation of cracks in the ceramic substrate 11 during thermal cycling, it is more preferable to increase the thickness t2 of the Ag-Cu alloy layer 22A formed at the end A of the circuit layer 12 and the metal layer 13. A The thickness t2 of the Ag-Cu alloy layer 22B formed in the central portion B of the circuit layer 12 and the metal layer 13. B The ratio of t2 A / t2 B The value is set within the range of 0.8 or higher and 1.2 or lower, and more preferably within the range of 0.9 or higher and 1.1 or lower.

[0112] The embodiments of the present invention have been described above, but the present invention is not limited thereto, and appropriate modifications can be made without departing from the technical concept of the present invention.

[0113] For example, in this embodiment, a power module is constructed by mounting semiconductor elements on an insulating circuit board, but it is not limited to this. For example, an LED module can be constructed by mounting LED elements on the circuit layer of the insulating circuit board, or a thermoelectric module can be constructed by mounting thermoelectric elements on the circuit layer of the insulating circuit board.

[0114] Furthermore, in the insulating circuit board of this embodiment, a ceramic substrate made of aluminum nitride (AlN) is used as an example for description, but it is not limited to this, and other ceramic substrates such as aluminum oxide (Al2O3) and silicon nitride (Si3N4) may also be used.

[0115] Furthermore, in this embodiment, Ti was described as an example of the active metal contained in the bonding material, but it is not limited to this; it is acceptable as long as it contains one or more active metals selected from Ti, Zr, Hf, and Nb. Additionally, these active metals may be contained in the form of hydrides.

[0116] Furthermore, in this embodiment, the circuit layer is formed by bonding a rolled sheet of oxygen-free copper to a ceramic substrate, but this is not a limitation. A circuit layer can also be formed by bonding copper sheets, formed from stamped copper plates, to a ceramic substrate in a circuit pattern configuration. In this case, each copper sheet only needs to have the interface structure with the ceramic substrate as described above.

[0117] Example

[0118] The results of the confirmation experiments conducted to verify the effectiveness of the present invention will be described below.

[0119] First, the ceramic substrates (40mm × 40mm) listed in Table 1 were prepared. Regarding thickness, the thickness was 0.635mm for AlN and Al2O3, and 0.32mm for Si3N4.

[0120] Furthermore, a 37mm × 37mm copper plate, made of oxygen-free copper and with the thickness shown in Table 1, was prepared as the copper plate serving as both the circuit layer and the metal layer. Additionally, a chamfered portion is formed at the periphery of the copper plate serving as both the circuit layer and the metal layer on the ceramic substrate side.

[0121] Furthermore, a bonding material is applied to the copper plate that serves as both the circuit layer and the metal layer. The bonding material is a paste-like material, and the amounts of Ag, Cu, and active metal are shown in Table 1. Here, as shown in Table 1, the equivalent film thickness of Ag and the mass ratio of Ag to active metal (Ag / active metal) were adjusted.

[0122] A copper plate, which will serve as the circuit layer, is stacked on one side of the ceramic substrate. Furthermore, a copper plate, which will serve as the metal layer, is stacked on the other side of the ceramic substrate.

[0123] The laminate was heated under pressure along the lamination direction to produce an Ag-Cu liquid phase. The pressure load was 0.294 MPa, and the temperature integral values ​​are shown in Table 2.

[0124] Furthermore, by cooling the heated laminate, the copper plate that will become the circuit layer, the ceramic substrate, and the copper plate that will become the metal layer are joined together to obtain an insulating circuit substrate (copper-ceramic composite).

[0125] The obtained insulating circuit board (copper-ceramic bond) was evaluated for the porosity at the ends, the distance between the ceramic substrate and the copper plate at the ends, the active metal compound layer, the Ag-Cu alloy layer, thermal cycling reliability, and the presence or absence of solder contamination, as follows.

[0126] (Porosity at the end)

[0127] Using an EPMA (electron probe microanalyzer) apparatus, elemental mappings of Ag, Cu, and active metals were obtained at the end sections of the interface between the circuit layer and the ceramic substrate, and at the interface between the ceramic substrate and the metal layer. Elemental mappings were obtained in five fields of view. Furthermore, the area (pore area) of the region where Ag, Cu, and active metals were not detected in the end region was calculated, and the maximum value of porosity = 100 × pore area / end region area was set as the "porosity at the end" and recorded in Table 2.

[0128] (Distance between the ceramic substrate and the copper plate at the end)

[0129] At the interface between the circuit layer and the ceramic substrate, and at the interface between the ceramic substrate and the metal layer, line analysis of Ag, Cu, and active metal was performed on the aforementioned end sections using an EPMA apparatus. Line analysis of each element was performed in five fields of view, perpendicular to the ceramic substrate and passing through intersection point P towards the circuit layer or metal layer. Furthermore, when Ag + Cu + active metal = 100% by mass, the distance from the surface of the ceramic substrate to the region where the Cu concentration is 90% by mass or higher was measured. The shortest distance within each of the five fields of view (a total of ten fields of view) was defined as the "distance between the ceramic substrate and the copper plate at the end," and this is recorded in Table 2.

[0130] (Active metal compound layer)

[0131] Using a scanning electron microscope (Carl Zeiss NTS ULTRA55, accelerating voltage 1.8kV), the cross-sections of the interface between the circuit layer and the ceramic substrate, and the interface between the ceramic substrate and the metal layer, were measured at 30,000x magnification. Elemental mappings of N, O, and active metal elements were obtained using energy-dispersive X-ray diffraction (EDD). The presence of an active metal compound layer was identified when an active metal element and N or O were present in the same region.

[0132] Observations were made in five fields of view. The average value obtained by dividing the area in which the active metal element and N or O coexist in the same region by the measured width was taken as the “thickness of the active metal compound layer” and recorded in Table 2.

[0133] (Ag-Cu alloy layer)

[0134] Using an EPMA apparatus, elemental mappings of Ag, Cu, and active metals were obtained at cross-sections of the interface between the circuit layer and the ceramic substrate, and at the interface between the ceramic substrate and the metal layer. Elemental mappings were obtained in five fields of view.

[0135] Furthermore, when Ag + Cu + active metal = 100% by mass, the area with an Ag concentration of 15% by mass or higher is designated as the Ag-Cu alloy layer. Its area is calculated, and the value obtained by dividing this area by the width of the measurement area (area / width of the measurement area) is calculated. The average value of this value is taken as the thickness of the Ag-Cu alloy layer and recorded in Table 2.

[0136] (Reliability of hot and cold cycles)

[0137] Depending on the material of the ceramic substrate, the aforementioned insulating circuit board was subjected to the following thermal cycles, and the presence of ceramic cracks was determined by SAT (ultrasonic testing). The evaluation results are shown in Table 2. The number of ceramic crack occurrences in Table 2 refers to the number of thermal cycles required until ceramic cracks occur.

[0138] For AlN and Al2O3: Set the load to -40℃×10 minutes and 150℃×10 minutes as one cycle, and perform SAT check every 50 cycles until 500 cycles are completed.

[0139] For Si3N4: Set the load to -40℃×10 minutes and 150℃×10 minutes as one cycle, and perform SAT check every 200 cycles until 2000 cycles are completed.

[0140] (Are there any solder stains?)

[0141] Using an EPMA device, elemental mappings of Ag, Cu, and active metal were obtained on the surfaces of the circuit layer and the metal layer. Furthermore, when Ag + Cu + active metal = 100% by mass, areas with an Ag concentration of 15% by mass or higher were defined as "solder stains." The area of ​​these stains was calculated and divided by the area of ​​a region 100 μm from the outer perimeter of the circuit layer and the metal layer. A "solder stain" was considered present when this value was 20% or higher.

[0142] [Table 1]

[0143]

[0144] [Table 2]

[0145]

[0146] First, Examples 1 to 3 of the present invention, which use AlN as a ceramic substrate, are compared with Comparative Example 1.

[0147] In Comparative Example 1, the distance between the ceramic substrate and the circuit layer (metal layer) was 23.2 μm at the end of the circuit layer (metal layer), the porosity of the end region of the circuit layer (metal layer) was 16.3%, and the number of crack initiation cycles in the thermal cycling test was 100. Furthermore, solder contamination was observed.

[0148] In contrast, in Example 1 of this invention, the distance between the ceramic substrate and the circuit layer (metal layer) is 24.7 μm at the end of the circuit layer (metal layer), the porosity of the end region of the circuit layer (metal layer) is 9.8%, and the number of crack initiation cycles in the thermal cycling test is 400. Furthermore, no solder contamination was observed.

[0149] In Example 2 of this invention, the distance between the ceramic substrate and the circuit layer (metal layer) is 20.9 μm at the end of the circuit layer (metal layer), the porosity of the end region of the circuit layer (metal layer) is 5.3%, and the number of crack initiation cycles in the thermal cycling test is 450. Furthermore, no solder contamination was detected.

[0150] In Example 3 of this invention, the distance between the ceramic substrate and the circuit layer (metal layer) was 12.1 μm at the end of the circuit layer (metal layer), the porosity of the end region of the circuit layer (metal layer) was set to 0.8%, and the number of crack initiation cycles in the thermal cycling test was 500. Furthermore, no solder contamination was observed.

[0151] Next, Examples 4 to 6 of the present invention, which use Si3N4 as a ceramic substrate, are compared with Comparative Example 2.

[0152] In Comparative Example 2, the distance between the ceramic substrate and the circuit layer (metal layer) was 45.1 μm at the end of the circuit layer (metal layer), the porosity of the end region of the circuit layer (metal layer) was set to 13.2%, and the number of crack initiation cycles in the thermal cycling test was 1200. Furthermore, solder contamination was observed.

[0153] In contrast, in Example 4 of this invention, the distance between the ceramic substrate and the circuit layer (metal layer) is 3.2 μm at the end of the circuit layer (metal layer), the porosity of the end region of the circuit layer (metal layer) is set to 0.3%, and the number of crack initiation cycles in the thermal cycling test is 1600. Furthermore, no solder contamination was observed.

[0154] In Example 5 of this invention, the distance between the ceramic substrate and the circuit layer (metal layer) was 6.4 μm at the end of the circuit layer (metal layer), the porosity of the end region of the circuit layer (metal layer) was set to 7.1%, and the number of crack initiation cycles in the thermal cycling test was 1800. Furthermore, no solder contamination was observed.

[0155] In Example 6 of this invention, the distance between the ceramic substrate and the circuit layer (metal layer) was 8.1 μm at the end of the circuit layer (metal layer), and the porosity of the end region of the circuit layer (metal layer) was set to 0.1%. No cracks were generated even after 2000 cycles in the thermal cycling test. Furthermore, no solder contamination was detected.

[0156] Next, Examples 7 and 8 of the present invention, which use Al2O3 as a ceramic substrate, are compared with Comparative Example 3.

[0157] In Comparative Example 3, the distance between the ceramic substrate and the circuit layer (metal layer) was 1.3 μm at the end of the circuit layer (metal layer), the porosity of the end region of the circuit layer (metal layer) was set to 0.0%, and the number of crack initiation cycles in the thermal cycling test was 50. Furthermore, no solder contamination was observed.

[0158] In contrast, in Example 7 of this invention, the distance between the ceramic substrate and the circuit layer (metal layer) was 29.6 μm at the end of the circuit layer (metal layer), the porosity of the end region of the circuit layer (metal layer) was set to 8.2%, and the number of crack initiation cycles in the thermal cycling test was 350. Furthermore, no solder contamination was observed.

[0159] In Example 8 of this invention, the distance between the ceramic substrate and the circuit layer (metal layer) was 19.6 μm at the end of the circuit layer (metal layer), the porosity of the end region of the circuit layer (metal layer) was set to 4.8%, and the number of crack initiation cycles in the thermal cycling test was 450. Furthermore, no solder contamination was observed.

[0160] The results of the above confirmation experiments confirm that, according to the present invention, an insulating circuit board (copper-ceramic bond) with excellent thermal cycling reliability and sufficient suppression of solder contamination can be provided.

[0161] Industrial availability

[0162] According to the present invention, a copper-ceramic bond with excellent thermal cycling reliability and sufficient suppression of solder contamination and an insulating circuit board made of the copper-ceramic bond can be provided.

[0163] Symbol Explanation

[0164] 10. Insulating circuit board (copper-ceramic bonding)

[0165] 11. Ceramic substrate (ceramic component)

[0166] 12 circuit layers (copper components)

[0167] 13 metal layers (copper components)

[0168] 21 (21A, 21B) Active metal compound layer

[0169] 22 (22A, 22B) Ag-Cu alloy layer

Claims

1. A copper-ceramic joint, formed by joining the surface of a plate-shaped copper component made of copper or a copper alloy to the surface of a plate-shaped ceramic component, characterized in that, In the copper component, a chamfer is formed on the periphery of the ceramic component side. A gap is formed between the ends of the copper component and the ceramic component. At the interface between the ceramic component and the copper component, the distance between the ceramic component and the copper component at the end of the copper component is in the range of 3 μm or more and 30 μm or less. Furthermore, the porosity of the end region of the copper component is less than 10%. The end region is the following region: That is, in a cross-sectional view of the interface between the ceramic component and the copper component, the intersection of the perpendicular line from the end face of the copper component at a position one-third the thickness of the copper component with the ceramic component is taken as the starting point, and the area extends 30 μm from the surface of the ceramic component toward the copper component and 400 μm from the surface of the ceramic component toward the central part of the copper component.

2. The copper-ceramic joint according to claim 1, characterized in that, At the interface between the ceramic component and the copper component, an active metal compound layer is formed on the side of the ceramic component. The thickness t1 of the active metal compound layer at the end of the copper component A The thickness t1 of the active metal compound layer at the center of the copper component B Within the range of 0.05 μm and 1.2 μm, the thickness ratio t1 A / t1 B It is in the range of 0.7 or higher and 1.4 or lower.

3. The copper-ceramic joint according to claim 1 or 2, characterized in that, At the interface between the ceramic component and the copper component, an Ag-Cu alloy layer is formed on the side of the copper component. The thickness t2 of the Ag-Cu alloy layer at the end of the copper component A and the thickness t2 of the Ag-Cu alloy layer at the central portion of the copper component. B Within the range of 3μm and above to 30μm, the thickness ratio t2 A / t2 B It is in the range of 0.7 or higher and 1.4 or lower.

4. An insulating circuit board, formed by bonding a copper plate made of copper or a copper alloy to the surface of a ceramic substrate, characterized in that, In the copper plate, a chamfered portion is formed at the periphery on the ceramic substrate side. A gap is formed between the ends of the copper plate and the ceramic substrate. At the interface between the ceramic substrate and the copper plate, the distance between the ceramic substrate and the copper plate at the end of the copper plate is in the range of 3 μm or more and 30 μm or less. Furthermore, the porosity of the end region of the copper plate is less than 10%. The end region is the following region: That is, in a cross-sectional view of the interface between the ceramic substrate and the copper plate, the intersection of the perpendicular line from the end face of the copper plate at a position one-third of the thickness of the copper plate with the ceramic substrate is taken as the starting point, and the area extends 30 μm from the surface of the ceramic substrate toward the copper plate and 400 μm from the surface of the ceramic substrate toward the center of the copper plate.

5. The insulating circuit board according to claim 4, characterized in that, At the interface between the ceramic substrate and the copper plate, an active metal compound layer is formed on the ceramic substrate side. The thickness t1 of the active metal compound layer at the end of the copper plate A The thickness t1 of the active metal compound layer at the center of the copper plate B Within the range of 0.05 μm and 1.2 μm, the thickness ratio t1 A / t1 B It is in the range of 0.7 or higher and 1.4 or lower.

6. The insulating circuit board according to claim 4 or 5, characterized in that, At the interface between the ceramic substrate and the copper plate, an Ag-Cu alloy layer is formed on the copper plate side. The thickness t2 of the Ag-Cu alloy layer at the end of the copper plate A and the thickness t2 of the Ag-Cu alloy layer at the center of the copper plate B Within the range of 3μm and above to 30μm, the thickness ratio t2 A / t2 B It is in the range of 0.7 or higher and 1.4 or lower.

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