FPGA-based GNSS signal ICAO model implementation method
By using an ICAO model of GNSS signals based on FPGA, diverse simulations of GNSS signals were achieved, solving the problem of digital and analog distortion in complex environments that is difficult to reproduce in existing technologies, and improving the universality and efficiency of satellite signal monitoring and evaluation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUILIN UNIV OF ELECTRONIC TECH
- Filing Date
- 2024-01-18
- Publication Date
- 2026-06-16
Smart Images
Figure CN117890934B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of satellite navigation technology, and in particular to a method for implementing the ICAO model of GNSS signals based on FPGA. Background Technology
[0002] Global Positioning Systems (GNSS) have become a core technology for modern positioning and navigation. Currently, there are four main satellite navigation systems: the US GPS, Russia's GLONASS, Europe's Galileo, and China's BeiDou. Satellites operating in low-Earth orbit, medium-Earth orbit, and high-Earth orbit experience aging and malfunctions in their hardware systems over time, causing digital, analog, and mixed distortions in the corresponding satellite signals. This results in abnormal power spectra and increased positioning errors. A typical example is the malfunction of the US GPS-19 satellite; since then, monitoring and evaluating signal quality has become a major research focus.
[0003] Satellite hardware failures are sporadic occurrences. Therefore, the verification of satellite signal monitoring and evaluation algorithms can only be done using previously acquired anomalous signals. This method suffers from the drawback of uniqueness and lacks universality. Currently, the 2OS model, also known as the ICAO model, is the only model that can describe satellite signal hardware failures. This model categorizes satellite signal failures into digital distortion, analog distortion, and mixed distortion. Summary of the Invention
[0004] The purpose of this invention is to provide an ICAO model implementation method for GNSS signals based on FPGA, which aims to solve the problem that GNSS signal simulators have difficulty reproducing digital distortion, analog distortion, and mixed distortion signals under complex environments.
[0005] To achieve the above objectives, this invention provides a method for implementing an ICAO model of GNSS signals based on FPGA, comprising the following steps:
[0006] The current chip and the next chip are then passed to the chip detection module;
[0007] The chip detection module detects the status of the previous chip and the next chip, and determines whether to activate the time statistics module.
[0008] The time statistics module transmits time data to the digital distortion module and the distortion parameter adjustment module in real time, and then shuts down the time statistics module.
[0009] The distortion parameter adjustment module corrects the distortion error caused by rounding the frequency control word;
[0010] The digital distortion module performs digital distortion processing on the chip based on the time data.
[0011] This includes passing the current chip and the next chip to the chip detection module, including:
[0012] The chip generation module generates the current chip and the next chip;
[0013] The current chip and the next chip are passed to the chip detection module.
[0014] The chip detection module detects the status of the previous chip and the next chip, and determines whether to activate the time statistics module, including:
[0015] The chip detection module performs state detection on the previous chip and the next chip to obtain the detection result.
[0016] Based on the detection results, determine whether to activate the time statistics module.
[0017] The time statistics module transmits time data to the digital distortion module and the distortion parameter adjustment module in real time, including:
[0018] The time statistics module performs statistics based on the code rate, system clock frequency, and chip distortion to obtain time data;
[0019] The time data is transmitted in real time to the digital distortion module and the distortion parameter adjustment module.
[0020] The digital distortion processing includes two cases: leading and lagging.
[0021] The chip generation module generates a chip and quantizes it before it enters an analog distortion filter designed by combining the amplitude-frequency response characteristics of the FPGA and the filter to complete the analog distortion of the chip.
[0022] The simulated distortion output of the completed chip is sent to the modulation module to be modulated with the carrier and navigation information and dequantized according to the quantization index to generate a simulated distortion signal.
[0023] This invention discloses an FPGA-based ICAO model implementation method for GNSS signals, comprising the following steps: transmitting the current chip and the next chip to a chip detection module; the chip detection module detecting the status of the previous chip and the next chip, and determining whether to activate a time statistics module; the time statistics module transmitting time data in real time to a digital distortion module and a distortion parameter adjustment module; the distortion parameter adjustment module correcting distortion errors caused by rounding of the frequency control word; the digital distortion module performing digital distortion processing on the chip based on the time data, and simulating distortion by combining FPGA and amplitude-frequency response characteristics to design a filter. This invention enables the simulation of TMA, TMB, and TMC distortion signals from different satellites of various navigation systems, increases the verification means for monitoring and evaluating satellite signal algorithms, and ensures the diversity of test samples, thereby solving the problem that GNSS signal simulators have difficulty reproducing digital distortion, analog distortion, and mixed distortion signals under complex environments. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a flowchart of digital distortion.
[0026] Figure 2 It simulates the distortion process.
[0027] Figure 3 This is a diagram showing the alignment of the rising edge.
[0028] Figure 4 This is a diagram showing the alignment of the rising edge.
[0029] Figure 5 This is a schematic diagram of rising edge alignment for chip digital distortion in an FPGA.
[0030] Figure 6 This is a schematic diagram of the TMB filter structure.
[0031] Figure 7 This is a diagram illustrating TMB distortion.
[0032] Figure 8 This is a flowchart of an ICAO model implementation method for GNSS signals based on FPGA provided by the present invention. Detailed Implementation
[0033] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.
[0034] Please see Figures 1 to 8 This invention provides a method for implementing an ICAO model of GNSS signals based on FPGA, comprising the following steps:
[0035] S1 transmits the current chip and the next chip to the chip detection module;
[0036] The S11 chip generation module generates the current chip and the next chip;
[0037] Specifically, the chip generation module is used to generate chips with the corresponding code rate. By calling the chip information at the ROM address, it simultaneously generates the current chip C(t) and the next chip C1(t).
[0038] S12 transmits the current chip and the next chip to the chip detection module.
[0039] Specifically, the current chip and the next chip are passed to the chip detection module.
[0040] The chip detection module in S2 detects the status of the previous chip and the next chip, and determines whether to start the time statistics module;
[0041] S21 performs state detection on the previous chip and the next chip through the chip detection module to obtain the detection result;
[0042] Specifically, the chip generation module updates the new chip and detects the chip. Based on the edge alignment of the normal chip and the digitally distorted chip, the corresponding detection method is selected, such as falling edge alignment {C(t), C1(t)}=2'b10, rising edge alignment {C(t), C1(t)}=2'b01. If the above state is detected, the Start signal is activated. No operation is performed on other conditions, such as {C(t), C1(t)}=2'b11, {C(t), C1(t)}=2'b00.
[0043] S22 determines whether to activate the time statistics module based on the detection results.
[0044] Specifically, the chip module detects the status of the preceding and following chips to determine whether to start the time statistics flag start signal.
[0045] The time statistics module described in S3 transmits time data to the digital distortion module and the distortion parameter adjustment module in real time.
[0046] The S31 time statistics module performs statistics based on code rate, system clock frequency and chip distortion to obtain time data;
[0047] Specifically, the number of clock cycles N in a chip duration is calculated using the system clock fs and the chip code rate fc.
[0048]
[0049] Based on the degree of distortion Calculate the lag or advance time m.
[0050]
[0051] statistics time.
[0052]
[0053] Combined with the statistical time It can correct the distortion parameter m.
[0054]
[0055] S32 transmits the time data to the digital distortion module and the distortion parameter adjustment module in real time.
[0056] Specifically, the statistical time is transmitted to the digital distortion module and the distortion parameter adjustment module in real time, and the start flag is turned off when the statistical time reaches the distortion time.
[0057] The distortion parameter adjustment module described in S4 corrects the distortion error caused by rounding the frequency control word;
[0058] Specifically, the digital distortion parameter correction module is used to correct distortion errors caused by rounding the frequency control word.
[0059] The digital distortion module described in S5 performs digital distortion processing on the chip based on the time data.
[0060] The digital distortion processing includes two cases: leading and lagging.
[0061] Specifically, based on real-time time parameters The chip distortion is processed, divided into rising edge alignment and falling edge alignment, each of which includes a lead time. and lag Two scenarios.
[0062] Rising edge alignment
[0063]
[0064]
[0065] Falling edge alignment
[0066]
[0067]
[0068] in For digital distortion lead-ahead chips, Digital distortion lag chip.
[0069] The S101 chip generation module generates a chip and quantizes it. Then, the chip enters an analog distortion filter designed by combining the amplitude-frequency response characteristics of the FPGA and the filter to complete the analog distortion of the chip.
[0070] Specifically, the chip generation module first generates a chip, which, after quantization, enters the TMB distortion filter to complete the simulated distortion of the chip.
[0071] like Figure 6 and Figure 7 As shown, Figure 4 The results show that the simulated distortion damping coefficient of the B1I frequency B6 satellite chip implemented in FPGA according to the present invention is 0.8, and the damping frequency is 4.
[0072] The quantization parameter is used to quantize the chip; generally, the quantization parameter is chosen as a power of 2.
[0073] Determining the parameters of the TMB distortion filter
[0074] The analog system function with TMB distortion is converted into a digital system function using the bilinear method, yielding the zero-point and pole-point expressions of the filter.
[0075]
[0076] Where fd is the damping frequency, df is the damping coefficient, fs is the system's main frequency, b0-2 is the zero, and a0-2 is the pole.
[0077] Quantize the zeros and poles, compare them with the original poles and zeros, perform amplitude-frequency response analysis, and select the optimal quantization parameters.
[0078] S102 outputs the analog distortion of the completed chip to the modulation module, modulates it with the carrier and navigation information, and dequantizes it according to the quantization index to generate an analog distortion signal.
[0079] Specifically, the output is then modulated with the carrier and navigation information by the modulation module, and finally dequantized according to the quantization index to generate a signal with analog distortion. The TMB distortion filter filters the quantized chip to generate a chip with analog distortion, where the filter structure is as follows: Figure 7 As shown. Finally, it is modulated with the carrier and navigation information, dequantized, and the TMB-distorted GNSS signal is obtained.
[0080] Beneficial effects:
[0081] 1. This invention solves the problem of applying the ICAO model in the GNSS satellite signal simulation system, and can use the GNSS signal simulator to reproduce abnormal signals, thus enriching the simulator's functionality.
[0082] 2. It is applicable to other processors with similar FPGA programming methods, as well as satellite signal frequencies with chip components such as GPS L1, BD B1I, GLONASS L1, etc., and has universality.
[0083] 3. It has shortened the development cycle and reduced costs for teams researching monitoring and evaluation algorithms, and has enriched the diversity of anomalous signals used to validate algorithms.
[0084] The above-disclosed embodiments are merely preferred embodiments of the FPGA-based ICAO model implementation method for GNSS signals. They should not be construed as limiting the scope of the invention. Those skilled in the art will understand that all or part of the processes for implementing the above embodiments, and equivalent variations made in accordance with the claims of the invention, are still within the scope of the invention.
Claims
1. A method for implementing an ICAO model of GNSS signals based on FPGA, characterized in that, Includes the following steps: The current chip and the next chip are then passed to the chip detection module; The chip detection module detects the status of the previous chip and the next chip, and determines whether to activate the time statistics module, including: The chip detection module performs state detection on the previous chip and the next chip to obtain the detection result. The number of clock cycles N in a chip duration is calculated using the system clock fs and the chip code rate fc. Based on the degree of distortion Calculate the lag or lead time m; statistics time; Combined with the statistical time The distortion parameter m can be corrected; Start: the start signal of the time statistics flag; Based on the detection results, determine whether to activate the time statistics module; The time statistics module transmits time data to the digital distortion module and the distortion parameter adjustment module in real time, and controls the start and stop signals of digital distortion. The distortion parameter adjustment module corrects the distortion error caused by rounding the frequency control word; The digital distortion module performs digital distortion processing on the chip based on the time and data; Based on real-time time parameters The chip distortion is processed, divided into rising edge alignment and falling edge alignment, each of which includes a lead time. and lag Two scenarios.
2. The method for implementing the ICAO model of GNSS signals based on FPGA as described in claim 1, characterized in that, The current chip and the next chip are passed to the chip detection module, including: The chip generation module generates the current chip and the next chip; The current chip and the next chip are passed to the chip detection module.
3. The method for implementing the ICAO model of GNSS signals based on FPGA as described in claim 2, characterized in that, The time statistics module transmits time data to the digital distortion module and the distortion parameter adjustment module in real time, including: The time statistics module performs statistics based on the code rate, system clock frequency, and chip distortion to obtain time data; The time data is transmitted in real time to the digital distortion module and the distortion parameter adjustment module.
4. The FPGA-based ICAO model implementation method for GNSS signals as described in claim 3, characterized in that, The digital distortion processing includes two cases: leading and lagging.
5. The FPGA-based ICAO model implementation method for GNSS signals as described in claim 2 further includes: The chip generation module generates a chip and quantizes it before it enters an analog distortion filter designed by combining the amplitude-frequency response characteristics of FPGA and filter to complete the analog distortion of the chip. The simulated distortion output of the completed chip is sent to the modulation module to be modulated with the carrier and navigation information and dequantized according to the quantization index to generate a simulated distortion signal.