Data transmission delay adjustable circuit, operation method thereof and memory interface chip

Abstract

The present invention provides a circuit with adjustable data transmission delay, an operation method thereof and a memory interface chip, and relates to the field of memory interface technology. The circuit with adjustable data transmission delay includes a data sampling adjustment module, a clock delay adjustment module and a third D flip-flop. The data sampling adjustment module divides the receiving link clock by two to obtain two input clocks with different phases. The two input clocks sample the same input data respectively to obtain the first sampling data and the second sampling output, and output them to the selector; the clock delay adjustment module adjusts the receiving link clock through the delay chain, and generates a feedback signal to send to the selector; the selector combines the first sampling data and the second sampling data based on the feedback signal, and finally outputs them after sampling by the third D flip-flop.

Description

Technical Field

[0001] The present invention relates to the field of memory interface technology, and more specifically, to a circuit with adjustable data transmission delay, an operation method of the circuit with adjustable data transmission delay, and a register clock driver and a memory interface chip including the circuit with adjustable data transmission delay. Background Art

[0002] Dual Inline Memory Modules (DIMMs) are mainly divided into Registered DIMMs (RDIMMs), Load-Reduced DIMMs (LRDIMMs), Unbuffered DIMMs (UDIMMs), and Small Outline DIMMs (SODIMMs). Among them, both RDIMMs and LRDIMMs are equipped with Register Clock Drivers (RCDs). RDIMMs add Register Clock Drivers to the memory bars for transmission. They are located between the CPU and the memory particles, which not only reduces the distance of parallel transmission but also ensures the effectiveness of parallel transmission. LRDIMMs use simpler buffers, including Register Clock Drivers and data buffers. Buffering reduces the power load on the lower motherboard, but has almost no effect on energy and memory performance.

[0003] DDR5 RCD refers to the register clock driver for DDR5 RDIMM and DDR5 LRDIMM. Its main function is to buffer the command / address bus, chip select, and clock between the host controller and DRAM. DDR refers to double data rate synchronous dynamic random access memory. The process of technology iteration from DDR to DDR5 is accompanied by changes in performance indicators, power supply voltage, data transfer rate, etc. As people's demand for memory bandwidth continues to increase, DDR5 helps meet this demand for speed.

[0004] Figure 1 The signal transmission path of RCD is shown in the figure. As shown in the figure, RCD receives DCA data sent from the CPU side, and outputs data QCA to the memory particle side after sampling and processing. The input clock of RCD is DCK, and the sending clock is QCK. For DDR5, the series of protocols on RCD (JESD82-511, JESD82-512, and JESD82-513) of the Jonit Electon Device Engineering Council (JEDEC) all have specific requirements for the data transmission delay t of RCD. PDMThere are clear regulations that data transmission delay is a very important parameter in DDR5 RCD. Figure 2 As shown, t PDM It refers to the time between the second beat of the input clock corresponding to the second beat of the RCD input data DCA (the falling edge in DDR mode or the rising edge in SDR mode) and the first beat of the output clock corresponding to the first beat of the output data QCA. The protocol stipulates that t PDM The time range is 0.95ns-1.25ns; while the regulations on RCD03 require that the time range is 0.9ns-1.2ns.

[0005] In the prior art, after RCD receives the input clock DCK, the phase-locked loop generates the receive link clock (RXCLK) and the transmit link clock (TXCLK); then the receive link clock is used to sample the DCA data, and the sampled data is analyzed and processed by the digital control logic unit according to the protocol requirements. After the processing is completed, the processed data is sampled by the transmit link clock, and the output data QCA is transmitted to the memory particle side. Here, the DCA data is sampled at the clock edge of the receive link clock at time A, and the data is output at the clock edge of the transmit link clock at time C. The time from time A to time C is called the data transmission delay, such as Figure 3 As shown. This period should meet the requirements of setup time and hold time when register samples data, where time A to time B is setup time, and time B to time C is hold time. At the same time, the data transmission delay should also meet t PDM The challenge to the existing technology is that the data transmission delay is a variable. When the rate is relatively low and the voltage is high, the margin of this time may be small; on the contrary, if the rate is high and the voltage is low, the margin of this time may be large. When in application scenarios with different transmission rate requirements, how to adjust the data transmission delay to meet t PDM The requirement is the problem faced by designers. Summary of the invention

[0006] The purpose of the present invention is to provide a circuit with adjustable data transmission delay, an operation method thereof and a memory interface chip, so as to solve the problem of how to adjust the data transmission delay in application scenarios with different transmission rate requirements, so as to meet the requirements of setup time and hold time and t PDM Requested questions.

[0007] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0008] In a first aspect, an embodiment of the present invention provides a circuit with adjustable data transmission delay, the circuit comprising:

[0009] A data sampling and adjusting module, wherein the data sampling and adjusting module is configured to: divide the receiving link clock into two input clocks with different phases, sample the same input data based on the two input clocks to obtain two data, and then output the data after time-sharing sampling by a selector;

[0010] A clock delay adjustment module, wherein the clock delay adjustment module is configured to: adjust the receiving link clock through the delay chain under different PVT conditions, and then sample the adjusted signal through the sending link clock to generate a feedback signal to provide to the selector;

[0011] and a third D flip-flop, the third D flip-flop being configured to: sample the output signal of the selector based on the transmission link clock and output data;

[0012] The receiving link clock is simultaneously input into the input end of the data sampling adjustment module and the first input end of the clock delay adjustment module; the sending link clock is simultaneously input into the second input end of the clock delay adjustment module and the CK end of the third D flip-flop;

[0013] The D terminal of the third D trigger is connected to the output terminal of the data sampling and adjusting module, and the Q terminal is connected to the second pin.

[0014] Optionally, the data sampling and adjustment module includes:

[0015] An input clock tree, wherein the input clock tree is configured to: generate two clock signals with different phases based on a receive link clock and a receive link clock feedback signal, wherein the first clock signal is connected to a CK terminal of a first D flip-flop, and the second clock signal is connected to a CK terminal of a second D flip-flop;

[0016] A first D flip-flop, wherein the first D flip-flop is configured to: sample the input data DAC based on the first clock signal, and output first sampled data via the Q terminal of the first D flip-flop;

[0017] A second D flip-flop, wherein the second D flip-flop is configured to: sample the input data based on the second clock signal, and output second sampled data via the Q terminal of the second D flip-flop 1003;

[0018] and a selector, wherein the selector is configured to: perform time-sharing sampling on the first sampling data and the second sampling data based on the transmission link clock feedback signal, and output third sampling data.

[0019] Optionally, the clock delay adjustment module includes:

[0020] a fourth D flip-flop, wherein the fourth D flip-flop is configured to: sample a receiving link clock selection signal based on a receiving link clock, and output a receiving link clock feedback signal;

[0021] A delay chain is configured to: perform delay adjustment on a receiving link clock feedback signal.

[0022] and a fifth D flip-flop, wherein the fifth D flip-flop is configured to: sample the delayed signal based on the transmission link clock to output a transmission link clock feedback signal.

[0023] Optionally, the structure of the data sampling adjustment module includes:

[0024] The first input end of the input clock tree inputs the receiving link clock, and the output end is respectively connected to the CK end of the first D flip-flop and the CK end of the second D flip-flop;

[0025] The D end of the first D flip-flop and the D end of the second D flip-flop are connected to a first pin at the same time, and the first pin is connected to input data;

[0026] The Q end of the first D flip-flop is connected to the a end of the selector, and the Q end of the second D flip-flop is connected to the b end of the selector.

[0027] Optionally, the structure of the clock delay adjustment module includes:

[0028] The CK terminal of the fourth D flip-flop inputs the receiving link clock, the D terminal receives the receiving link clock selection signal, the Q terminal is connected to the input terminal of the delay chain, and the Q terminal is also connected to the second input terminal of the input clock tree;

[0029] The output end of the delay chain is connected to the D end of the fifth D flip-flop, the CK end of the fifth D flip-flop inputs the transmission link clock, and the Q end is connected to the C end of the selector.

[0030] Optionally, the data sampling and adjustment module further includes:

[0031] A first control logic module, wherein the first control logic module is configured to: perform logic processing on the first sampled data;

[0032] A second control logic module, wherein the second control logic module is configured to: perform logic processing on the second sampled data;

[0033] A third control logic module is configured to perform logic processing on the third sampling data.

[0034] Optionally, the structure of the data sampling adjustment module includes:

[0035] The first input end of the input clock tree inputs the receiving link clock, and the output end is respectively connected to the CK end of the first D flip-flop and the CK end of the second D flip-flop;

[0036] The D end of the first D flip-flop and the D end of the second D flip-flop are connected to the first pin at the same time, and the first pin is connected to input data;

[0037] The Q end of the first D flip-flop is connected to the input end of the first control logic module, and the Q end of the second D flip-flop is connected to the input end of the second control logic module;

[0038] The output end of the first control logic module is connected to the a end of the selector, and the output end of the second control logic module is connected to the b end of the selector;

[0039] The output end of the selector is connected to the input end of the third control logic module, and the output end of the third control logic module is connected to the D end of the third D flip-flop.

[0040] Optionally, the clock delay adjustment module further includes an output clock tree, and the output clock tree is configured to: generate a clock network based on a transmission link clock and provide it to the output module.

[0041] Optionally, the structure of the clock delay adjustment module includes:

[0042] The CK terminal of the fourth D flip-flop inputs the receiving link clock, the D terminal is connected to the receiving link clock selection signal, the Q terminal is connected to the input terminal of the delay chain, and the Q terminal is also connected to the second input terminal of the input clock tree;

[0043] The output end of the delay chain is connected to the D end of the fifth D flip-flop, the CK end of the fifth D flip-flop inputs the transmission link clock, and the Q end is connected to the C end of the selector;

[0044] The input end of the output clock tree inputs the transmission link clock, and the output end is connected to the CK end of the third D flip-flop.

[0045] Optionally, the data transmission delay adjustable circuit further includes an analog driving module, which is configured to drive the output of data; the input end of the analog driving module is connected to the Q end of the third D flip-flop, and the output end is connected to the second pin.

[0046] Optionally, the delay chain is composed of N identical delay units connected in series, each delay unit is connected to a control signal, and the control signal adjusts the number of enabled delay units.

[0047] In a second aspect, an embodiment of the present invention provides an operating method of a data transmission delay adjustable circuit, wherein the data transmission delay adjustable circuit includes a data sampling adjustment module and a clock delay adjustment module, and the operating method includes:

[0048] Add a delay chain between the receiving link clock and the sending link clock to output clock signals with different delays under different PVT conditions;

[0049] Divide the receiving link clock by two to obtain a first input clock and a second input clock with different phase differences, and use the two clocks to sample the input data to obtain first sampled data and second sampled data;

[0050] The first sampling data and the second sampling data are sampled in time division by the selector, and after completion, the data is output at the rising edge of the next transmission link clock.

[0051] Optionally, the operation method of outputting clock signals with different delays under different PVT conditions includes:

[0052] According to different PVT conditions, training is performed during the chip automation test phase to select appropriate delay parameters to meet delay requirements;

[0053] Configure the control signal of the delay chain based on the delay parameters;

[0054] After the delay chain receives the control signal, it determines the number of delay units that are turned on and outputs a delay signal after a delay.

[0055] Optionally, the method of dividing the receiving link clock by two to obtain a first input clock and a second input clock with different phase differences, and using the two clocks to sample input data respectively includes:

[0056] The receiving link clock is simultaneously input into the fourth D flip-flop and the input clock tree, the fourth D flip-flop sends a receiving clock feedback signal to the input clock tree, and the input clock tree generates a first input clock and a second input clock based on the receiving link clock;

[0057] The first D flip-flop and the second D flip-flop respectively sample the input data and output the first sampled data and the second sampled data;

[0058] After receiving the first sampled data and the second sampled data, the selector performs time-sharing sampling on the data based on the transmission link clock feedback signal, and outputs the combined data.

[0059] In a third aspect, an embodiment of the present invention provides a memory interface chip, which includes a power manager, a serial detection hub, a temperature sensor chip, a data buffer, a register clock driver, and a phase-locked loop, wherein the register clock driver includes the circuit with adjustable data transmission delay.

[0060] Optionally, the memory interface chip is suitable for a double data rate fifth generation (DDR5) memory module.

[0061] Optionally, the memory module comprises a DDR5 RDIMM or a DDR5 LRDIMM.

[0062] Compared with the prior art, the present invention has the following beneficial effects:

[0063] The embodiments of the present disclosure provide a circuit with adjustable data transmission delay, an operation method thereof and a memory interface chip, wherein the circuit with adjustable data transmission delay includes a data sampling adjustment module and a clock delay adjustment module. The data sampling adjustment module is used to obtain a first input clock and a second input clock after dividing the receiving link clock by two, and then sample the input data respectively to obtain first sampled data and second sampled data, thereby increasing the data sampling time in disguise to meet the RCD requirements on setup time and hold time. The clock delay adjustment module is used to adjust the receiving link clock by controlling the delay chain to generate a sending link clock feedback signal. The selector selects the first sampled data and the second sampled data based on the sending link clock feedback signal to ensure that different data are selected at different times to meet the data transmission requirements while meeting t PDM In application scenarios with different transmission rate requirements, the data transmission delay adjustable circuit disclosed in the present invention can meet both the setup time and hold time requirements and the t PDM Requested questions.

[0064] Embodiments of the present invention

[0065] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0067] Figure 1 It is a schematic diagram of the signal transmission path of RCD;

[0068] Figure 2 The existing protocol is about the data transmission delay t PDM Schematic diagram of the definition;

[0069] Figure 3 It is a schematic diagram of the data transmission delay in RCD;

[0070] Figure 4 is a block diagram of a circuit for adjustable data transmission delay in an RCD according to an exemplary embodiment of the present disclosure;

[0071] Figure 5 It is shown in detail Figure 4 Circuit diagram of adjustable data transmission delay in RCD;

[0072] Figure 6 It is shown in detail Figure 4 and Figure 5 The circuit block diagram of the delay chain;

[0073] Figure 7 is a schematic diagram of the operation timing of the data transmission delay adjustable circuit in the RCD of the exemplary embodiment of the present disclosure;

[0074] Figure 8 yes Figure 4 A flow chart of an example of a circuit for adjusting the data transmission delay in an RCD;

[0075] Fig. 9 It is shown in detail Figure 8 Flow chart of operation S110;

[0076] Fig.10 It is shown in detail Figure 8 Flow chart of operation S120.

[0077] Description of reference numerals:

[0078] RXCLK-receive link clock; TXCKL-transmit link clock; RXCLK1-first input clock; RXCLK2-second input clock; RXSEL-receive link clock feedback signal; TXSEL-transmit link clock feedback signal; RXCLK_SEL_DAT-receive link clock selection signal; DAC-input data; RXCLK1_SEL first sampling data; RXCLK2_SEL second sampling data; QCA-output data;

[0079] P1-first pin; P2-second pin. DETAILED DESCRIPTION

[0080] Example embodiments of the present disclosure will be described below in detail and clearly to such an extent that those skilled in the art can easily practice the present disclosure.

[0081] It should be noted that, unless otherwise clearly specified and limited, the terms "connection" and "coupling" should be understood in a broad sense, for example, it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0082] Figure 3 is a schematic diagram of the data transmission delay in RCD. Figure 3 Describe the definition of data transmission delay in RCD. The data transmission delay (hereinafter referred to as Trx2tx ) means that the input data is sampled at the clock edge of the receiving link clock at time A, and the data is output at the clock edge of the sending link clock at time C. The period from time A to time C should meet the requirements of the setup time and hold time when the register samples the data. At the same time, the data transmission delay should also meet the provisions of the relevant protocols of the Electronic Components Solid State Technology Association, that is, the time between the clock edge corresponding to the sampling of the receiving link clock in RCD and the clock edge of the sending link clock corresponding to the data output is t PDM Therefore, according to the requirements of the "Protocol", the data transmission delay in RCD should meet t PDM requirements.

[0083] However, the data transmission delay has nothing to do with the frequency of the input clock DCK of the phase-locked loop, but is affected by the process / voltage / temperature (PVT), and the difference will be very large under different PVT. For example, when the rate is relatively low and the voltage is high, the delay may be small; conversely, if the rate is high and the voltage is low, the delay may be large. Therefore, at different rates, as PVT changes, it is difficult for the existing technology to adjust the data transmission delay in real time to meet t PDM requirements.

[0084] Example 1

[0085] Figure 4 1 is a block diagram of a data transmission delay adjustable circuit 1000 according to an exemplary embodiment of the present disclosure. The data transmission delay adjustable circuit 1000 may include a data sampling adjustment module 1100 , a clock delay adjustment module 1200 and a third D flip-flop 1005 .

[0086] The data sampling and adjusting module 1100 can be configured to divide the receiving link clock into two input clocks with different phases, sample the same input data based on the two input clocks to obtain two data, and then output the data after time-sharing sampling by the selector 1004.

[0087] It should be noted that the phases of the two input clocks can be adjusted by those skilled in the art as required. For example, the phase difference between the two input clocks is 180°.

[0088] The clock delay adjustment module 1200 can be configured to adjust the receiving link clock through the delay chain under different PVT conditions, and then sample the adjusted signal through the transmitting link clock to generate a feedback signal to provide to the selector 1004 as the selection signal TXSEL.

[0089] The third D flip-flop 1005 is coupled to the data sampling adjustment module 1100 and the clock delay adjustment module 1200 at the same time, and can be configured to sample the output signal of the selector based on the transmission link clock and output the data QCA.

[0090] The third D flip-flop 1005 can be configured to sample the output signal of the selector based on the transmission link clock and output data QCA; the D end of the third D flip-flop is connected to the output end of the data sampling adjustment module 1100, the CK end inputs the transmission link clock, and the Q end is connected to the second pin.

[0091] The receiving link clock and the transmitting link clock are both provided by phase locked loops (PLL). The input data DCA is output by the CPU side and input to RCD via the first pin P1, and the output data QCA is output to the memory chip side via the second pin P2.

[0092] Figure 7 It is a schematic diagram of the action timing of the adjustable data transmission delay circuit in the RCD of the example embodiment of the present invention. Referring to the action timing of the circuit, the working principle of the adjustable data transmission delay circuit of the present invention is: a delay chain is set between the receiving link clock and the transmitting link clock, and the receiving link clock is adjusted by controlling the delay chain in the clock delay adjustment module to generate a transmitting link clock feedback signal TXSEL; at the same time, the first input clock and the second input clock after the two-frequency division respectively sample the input data DCA to obtain the first sampling data and the second sampling data, thereby increasing the data sampling time in disguise to meet the requirements of the RCD on the setup time and the hold time. In addition, the selector selects the first sampling data and the second sampling data based on the transmitting link clock feedback signal TXSEL to ensure that different data are selected at different times to meet the data transmission requirements, while satisfying t PDM time requirements.

[0093] The data sampling and adjusting module 1100 may include an input clock tree 1001, a first D flip-flop 1002, a second D flip-flop 1003, and a selector 1004. The input clock tree 1001 may be configured to generate two clock signals with different phases based on the receiving link clock and the receiving link clock feedback signal, wherein the first clock signal is connected to the first D flip-flop 1002, and the second clock signal is connected to the second D flip-flop 1003. The first D flip-flop 1002 may be configured to sample the input data DAC based on the first clock signal, and output the first sampled data through the Q end of the first D flip-flop 1002. The second D flip-flop 1003 may be configured to sample the input data DAC based on the second clock signal, and output the second sampled data through the Q end of the second D flip-flop 1003. The selector 1004 may be configured to perform time-sharing sampling on the first sampled data and the second sampled data based on the sending link clock feedback signal.

[0094] The clock delay adjustment module 1200 may include a fourth D flip-flop 1006, a delay chain 1007, and a fifth D flip-flop 1008. The fourth D flip-flop 1006 may be configured to sample the receiving link clock selection signal based on the receiving link clock and output the receiving link clock feedback signal. The delay chain 1007 may be configured to delay the receiving link clock feedback signal. For example, a delay loop (DLL) known in the art is used to implement this. Figure 6 Shown in detail Figure 4 and Figure 5 The structural block diagram of the delay chain is shown in Figure 2. Figure 4 , Figure 5 and Figure 6 The delay chain of the exemplary embodiment of the present disclosure may be composed of N identical delay units connected in series, each delay unit inputs a control signal, the first delay unit unit1 receives the input signal (i.e., the output signal RXSEL of the fourth D flip-flop), and the Nth delay unit unitN outputs the signal Output Signal to the D terminal of the fifth D flip-flop, where N is a positive integer. The delay unit may adopt a NAND gate or other logic gate circuit known in the art. The delay chain of the present disclosure adjusts the number of delay units turned on by the control signal to ultimately achieve delay adjustment.

[0095] It is well known in the art that there are many ways to adjust the delay, and the present disclosure is not limited to this one delay adjustment method. In practical applications, according to different PVT conditions, training is performed in the chip automatic test equipment (ATE) stage to select appropriate delay parameters to meet the delay requirements.

[0096] The fifth D flip-flop 1008 may be configured to sample the delayed signal based on the transmission link clock and output a transmission link clock feedback signal.

[0097] It should be noted that the receive link clock selection signal is a clock reference signal.

[0098] refer to Figure 4 The structure of the data transmission delay adjustable circuit 1000 disclosed in the present invention is as follows:

[0099] The first input end of the input clock tree 1001 inputs the receiving link clock, and the output end is connected to the CK end of the first D flip-flop 1002 and the CK end of the second D flip-flop 1003 respectively;

[0100] The D end of the first D flip-flop 1002 and the D end of the second D flip-flop 1003 are connected to the first pin at the same time, and the data DCA is input at the same time;

[0101] The Q end of the first D flip-flop 1002 is connected to the a end of the selector, and the Q end of the second D flip-flop 1003 is connected to the b end of the selector;

[0102] The CK terminal of the fourth D flip-flop inputs the receiving link clock, the D terminal receives the receiving link clock selection signal, the Q terminal is connected to the input terminal of the delay chain, and the Q terminal is also connected to the second input terminal of the input clock tree 1001;

[0103] The output end of the delay chain 1007 is connected to the D end of the fifth D flip-flop 1008, the CK end of the fifth D flip-flop 1008 inputs the transmission link clock, and the Q end is connected to the C end of the selector;

[0104] The CK terminal of the third D flip-flop 1005 inputs the transmission link clock, the D terminal is connected to the output terminal of the selector, the Q terminal is connected to the second pin, and the data QCA is output.

[0105] Figure 5 The block diagram of the data transmission delay adjustable circuit 1000 in the RCD of the present disclosure is shown in detail. Figure 4 and Figure 5 The data transmission delay adjustable circuit 1000 may include a data sampling adjustment module 1100 , a clock delay adjustment module 1200 , a third D flip-flop 1005 , an output clock tree 1009 and an analog driving module 1013 .

[0106] The data sampling and adjusting module 1100 may include an input clock tree 1001, a first D flip-flop 1002, a second D flip-flop 1003, a first control logic module 1010, a second control logic module 1011, a selector 1004, and a third control logic module 1012. The first control logic module 1010 may be configured to process the first sampled data; the second control logic module 1011 may be configured to process the second sampled data; and the third control logic module 1012 may be configured to process the data output by the selector.

[0107] The clock delay adjustment module 1200 may include a fourth D flip-flop 1006, a delay chain 1007, a fifth D flip-flop 1008, and an output clock tree 1009. The output clock tree 1009 may be configured to provide a clock signal to each output module of the RCD.

[0108] The third D flip-flop 1005 may be configured to sample data outputted by the third control logic module 1012 based on the transmission link clock signal.

[0109] The output clock tree 1009 can be configured to generate a clock network based on the transmit link clock and provide it to the output module.

[0110] The analog driving module 1013 may be configured to drive the output QCA data.

[0111] Specifically, the structure of the data transmission delay adjustable circuit 1000 is as follows:

[0112] The first input end of the input clock tree 1001 inputs the receiving link clock, and the output end is connected to the CK end of the first D flip-flop 1002 and the CK end of the second D flip-flop 1003 respectively;

[0113] The D end of the first D flip-flop 1002 and the D end of the second D flip-flop 1003 are connected to the first pin at the same time, and the data DCA is input at the same time;

[0114] The Q end of the first D flip-flop 1002 is connected to the input end of the first control logic module 1010, and the Q end of the second D flip-flop 1003 is connected to the input end of the second control logic module 1011;

[0115] The output end of the first control logic module 1010 is connected to the a end of the selector 1004, and the output end of the second control logic module 1011 is connected to the b end of the selector 1004;

[0116] The output end of the selector 1004 is connected to the input end of the third control logic module 1012, and the output end of the third control logic module 1012 is connected to the D end of the third D flip-flop;

[0117] The CK terminal of the fourth D flip-flop 1006 inputs the receiving link clock, the D terminal receives the receiving link clock selection signal, the Q terminal is connected to the input terminal of the delay chain 1007, and the Q terminal is also connected to the second input terminal of the input clock tree 1001;

[0118] The output end of the delay chain 1007 is connected to the D end of the fifth D flip-flop 1008, the CK end of the fifth D flip-flop 1008 inputs the transmission link clock, and the Q end is connected to the C end of the selector;

[0119] The input end of the output clock tree 1009 inputs the transmission link clock, and the output end is connected to the CK end of the third D flip-flop 1005;

[0120] The D end of the third D flip-flop 1005 is connected to the output end of the third control logic module 1012, the Q end of the third D flip-flop 1005 is connected to the input end of the analog driving module 1013, the output end of the analog driving module 1013 is connected to the second pin, and outputs data QCA.

[0121] It should be noted that the first control logic module, the second control logic module, and the third control logic module can be composed of logic gate circuits according to needs by those skilled in the art, which are conventional technical means in the art. The function of the control logic module is to process the data sampled at each stage according to the relevant RCD protocol requirements. The specific structure of the above modules is not disclosed, which does not affect the realization of the invention purpose of the present invention.

[0122] Example 2

[0123] The difference between Example 2 and Example 1 is that this example provides an operation method of the data transmission delay adjustable circuit disclosed in the present invention.

[0124] Figure 8 FIG. 1 is a flow chart of an operation example of the data transmission delay adjustable circuit disclosed in the present invention. Figure 4 and Figure 8 , Figure 4 The disclosed operation method of the data transmission delay adjustable circuit includes:

[0125] In operation S110, a delay chain is added between a receiving link clock and a transmitting link clock to output clock signals with different delays under different PVT conditions;

[0126] In operation S120, the receiving link clock is divided into two frequencies to obtain a first input clock and a second input clock with different phase differences, and the input data DCA is sampled using the two clocks to obtain first sampled data and second sampled data;

[0127] In operation S130, the first sample data and the second sample data are time-division sampled by the selector, and after completion, the data QCA is output at the rising edge of the next transmission link clock.

[0128] Fig. 9 Shown in detail Figure 8 Flow chart of operation S110, refer to Figure 8 , Fig. 9 , S110 includes the following operation methods:

[0129] In operation S111, according to different PVT conditions, training is performed in the chip automation test stage to select appropriate delay parameters to meet the delay requirements;

[0130] In operation S112, a control signal of the delay chain is configured based on the delay parameter;

[0131] In operation S113, after the delay chain receives the control signal of step S122, the number of delay units turned on is determined, and a delay signal is output after delay.

[0132] Fig.10 It is shown in detail Figure 8 Flow chart of operation S120, refer to Figure 4 , Figure 5 , Figure 8 and Fig.10 , S120 includes the following operation methods:

[0133] In operation S121, the receiving link clock is simultaneously input into the fourth D flip-flop and the input clock tree, the fourth D flip-flop sends a receiving clock feedback signal to the input clock tree, and the input clock tree generates a first input clock and a second input clock based on the receiving link clock;

[0134] In operation S122, the first D flip-flop and the second D flip-flop respectively sample the input data DCA and output first sampled data and second sampled data;

[0135] In operation S125 , after receiving the sampled data outputted in step S122 , the selector samples the data in time division based on the transmission link clock feedback signal TXSEL, and outputs the combined data.

[0136] According to design requirements, such as processing RCD internal data to meet the JEDEC Association's requirements for DDR5, operation S122 may also include operations S123 and 124 to process the first sampled data and the second sampled data. In operation S123, the first control logic module performs logic processing on the first sampled signal; in operation S124, the second control logic module performs logic processing on the second sampled signal. It should be noted that the logic processing is actually RCD protocol processing, which may be verification, forwarding, control word processing, etc. These processes are conventional technical means in the field. The use of different logic processing methods does not affect the realization of the purpose of the present invention.

[0137] The operation method disclosed in the present invention can be used to adjust the link delay according to different PVT conditions, so that the data transmission delay (T rx2tx ) meets the requirements of setup time and hold time. First, the phase of the receiving link clock is delayed through the delay adjustment step; then the first input clock and the second input clock are generated based on the receiving link clock. The first input clock and the second input clock sample the input data at the same time, which is equivalent to increasing the sampling time of the receiving link clock in disguise to meet the requirements of RCD setup clock and hold time. Finally, a selector is used to select the first sampled data and the second sampled data to ensure that different data are selected at different times to meet the data transmission requirements and meet t PDM time requirements.

[0138] Example 3

[0139] The difference between this embodiment and embodiment 1 and embodiment 2 is that this embodiment is an exemplary memory interface chip of the present disclosure, and the data transmission delay adjustable circuit of the present disclosure is part of the memory interface chip. The memory interface chip may include a power manager, a serial detection hub, a temperature sensor chip, a data buffer, a register clock driver, and a phase-locked loop.

[0140] The memory interface chip can be applied to a double data rate fifth generation (DDR5) memory module, which may include a DDR5 RDIMM or a DDR5 LRDIMM.

[0141] DDR5 RDIMM is a DDR5 Registered Dual In-line Memory Module (RDIMM) of Synchronous Dynamic Random Access Memory (SDRAM) devices;

[0142] DDR5 LRDIMM is a DDR5 Low Load Registered Dual In-line Memory Module (LRDIMM) of Synchronous Dynamic Random Access Memory (SDRAM) devices.

[0143] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A circuit with adjustable data transmission delay, characterized in that: The circuit with adjustable data transmission delay comprises: A data sampling and adjusting module, wherein the data sampling and adjusting module is configured to: divide the receiving link clock into two input clocks with different phases, sample the same input data based on the two input clocks to obtain two data, and then output the data after time-sharing sampling by a selector; A clock delay adjustment module, wherein the clock delay adjustment module is configured to: adjust the receiving link clock through the delay chain under different PVT conditions, and then sample the adjusted signal through the transmitting link clock to generate a transmitting link clock feedback signal to provide to the selector; and A third D flip-flop, the third D flip-flop is configured to: sample the output signal of the selector based on the transmission link clock and output data; the D end of the third D flip-flop is connected to the output end of the data sampling and adjustment module, the CK end is connected to the transmission link clock, and the Q end is connected to the second pin; The clock delay adjustment module comprises: a fourth D flip-flop, the fourth D flip-flop being configured to: sample a receiving link clock selection signal based on the receiving link clock, and output a receiving link clock feedback signal; A delay chain, wherein the delay chain is configured to: perform delay adjustment on the receiving link clock feedback signal to obtain a delayed signal; and A fifth D flip-flop is configured to: sample the delay signal based on the transmission link clock, and output a transmission link clock feedback signal.

2. The circuit with adjustable data transmission delay according to claim 1, characterized in that: The data sampling and adjustment module comprises: An input clock tree, wherein the input clock tree is configured to: generate a first clock signal and a second clock signal with different phases based on the receiving link clock; A first D flip-flop, wherein the first D flip-flop is configured to: sample input data based on the first clock signal, and output first sampled data via a Q terminal of the first D flip-flop; a second D flip-flop, the second D flip-flop being configured to: sample input data based on the second clock signal, and output second sampled data via a Q terminal of the second D flip-flop; and The selector is configured to perform time-sharing sampling on the first sampling data and the second sampling data based on the transmission link clock feedback signal, and output third sampling data.

3. The circuit with adjustable data transmission delay according to claim 2, characterized in that: The structure of the data sampling and adjustment module includes: The first input end of the input clock tree inputs the receiving link clock, and the output end is respectively connected to the CK end of the first D flip-flop and the CK end of the second D flip-flop; The D end of the first D flip-flop and the D end of the second D flip-flop are connected to a first pin at the same time, and the first pin is connected to input data; The Q end of the first D flip-flop is connected to the a end of the selector, and the Q end of the second D flip-flop is connected to the b end of the selector.

4. The circuit with adjustable data transmission delay according to claim 1, characterized in that: The structure of the clock delay adjustment module includes: The CK terminal of the fourth D flip-flop inputs the receiving link clock, the D terminal receives the receiving link clock selection signal, the Q terminal is connected to the input terminal of the delay chain, and the Q terminal is also connected to the second input terminal of the input clock tree; The output end of the delay chain is connected to the D end of the fifth D flip-flop, the CK end of the fifth D flip-flop inputs the transmission link clock, and the Q end is connected to the C end of the selector.

5. The circuit with adjustable data transmission delay according to claim 2, characterized in that: The data sampling and adjustment module also includes: A first control logic module, wherein the first control logic module is configured to: perform logic processing on the first sampled data; A second control logic module, wherein the second control logic module is configured to: perform logic processing on the second sampled data; A third control logic module is configured to perform logic processing on the third sampling data.

6. The circuit with adjustable data transmission delay according to claim 5, characterized in that: The structure of the data sampling and adjustment module includes: The first input end of the input clock tree inputs the receiving link clock, and the output end is respectively connected to the CK end of the first D flip-flop and the CK end of the second D flip-flop; The D end of the first D flip-flop and the D end of the second D flip-flop are connected to a first pin at the same time, and the first pin is connected to input data; The Q end of the first D flip-flop is connected to the input end of the first control logic module, and the Q end of the second D flip-flop is connected to the input end of the second control logic module; The output end of the first control logic module is connected to the a end of the selector, and the output end of the second control logic module is connected to the b end of the selector; The output end of the selector is connected to the input end of the third control logic module, and the output end of the third control logic module is connected to the D end of the third D flip-flop.

7. The circuit with adjustable data transmission delay according to claim 1, characterized in that: The clock delay adjustment module further includes: an output clock tree, wherein the output clock tree is configured to: generate a clock network based on the transmission link clock and provide it to the CK terminal of the third D flip-flop.

8. The circuit with adjustable data transmission delay according to claim 7, characterized in that: The structure of the clock delay adjustment module includes: The CK terminal of the fourth D flip-flop inputs the receiving link clock, the D terminal receives the receiving link clock selection signal, the Q terminal is connected to the input terminal of the delay chain, and the Q terminal is also connected to the second input terminal of the input clock tree; The output end of the delay chain is connected to the D end of the fifth D flip-flop, the CK end of the fifth D flip-flop inputs the transmission link clock, and the Q end is connected to the C end of the selector; The input end of the output clock tree inputs the transmission link clock, and the output end is connected to the CK end of the third D flip-flop.

9. The circuit with adjustable data transmission delay according to claim 1, characterized in that: The data transmission delay adjustable circuit also includes an analog driving module, which is configured to drive the output of data; the input end of the analog driving module is connected to the Q end of the third D flip-flop, and the output end is connected to the second pin.

10. The circuit with adjustable data transmission delay according to claim 1, characterized in that: The delay chain is composed of N identical delay units connected in series, wherein N is a positive integer, and each delay unit is connected to a control signal, and the control signal adjusts the number of the delay units that are turned on.

11. A method for operating a data transmission delay adjustable circuit, characterized in that: The method adopts the circuit according to any one of claims 1 to 10, and the method comprises: Add a delay chain between the receiving link clock and the sending link clock to output clock signals with different delays under different PVT conditions; Divide the receiving link clock by two to obtain a first input clock and a second input clock with different phase differences, and use the two clocks to sample the input data to obtain first sampled data and second sampled data; The first sampling data and the second sampling data are sampled in time division by the selector, and after completion, the data is output at the rising edge of the next transmission link clock.

12. The method for operating the data transmission delay adjustable circuit according to claim 11, characterized in that: The operation method of outputting clock signals with different delays under different PVT conditions includes: According to different PVT conditions, training is performed during the chip automation test phase to select appropriate delay parameters to meet delay requirements; Configure the control signal of the delay chain based on the delay parameters; After the delay chain receives the control signal, it determines the number of delay units that are turned on and outputs a delay signal after a delay.

13. The operating method of the data transmission delay adjustable circuit according to claim 11, characterized in that: The method of dividing the receiving link clock by two to obtain a first input clock and a second input clock with different phase differences, and using the two clocks to sample input data respectively includes: The receiving link clock is simultaneously input into the fourth D flip-flop and the first input end of the input clock tree, the fourth D flip-flop sends a receiving clock feedback signal to the second input end of the input clock tree, and the input clock tree generates a first input clock and a second input clock based on the receiving link clock; The first D flip-flop and the second D flip-flop respectively sample the input data and output the first sampled data and the second sampled data; After receiving the first sampled data and the second sampled data, the selector performs time-sharing sampling on the data based on the transmission link clock feedback signal, and outputs the combined data.

14. A memory interface chip, comprising a power manager, a serial detection hub, a temperature sensor chip, a data buffer, a register clock driver, and a phase-locked loop, characterized in that: The register clock driver comprises a circuit with adjustable data transmission delay as described in any one of claims 1-10.

15. The memory interface chip according to claim 14, characterized in that: The memory interface chip is suitable for a double data rate fifth generation memory module.

16. The memory interface chip according to claim 15, characterized in that: The memory module includes a DDR5 RDIMM or a DDR5 LRDIMM.

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