A wafer level nanoparticle sintering packaging method for microelectronic device patterned sealing and bump co-bonding

By combining photolithography with the sintering of metal nanoparticles, sealing lines and bumps are fabricated on wafers, solving the welding problem in high-density, small-size, narrow-pitch packaging. This enables efficient and low-cost nanoparticle fabrication and bonding, improving the reliability and sealing of devices.

CN118899225BActive Publication Date: 2026-06-16TSINGHUA UNIVERSITY
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
TSINGHUA UNIVERSITY
Filing Date
2023-05-04
Publication Date
2026-06-16

AI Technical Summary

⚠Technical Problem

Existing technologies struggle to achieve efficient and low-cost nanoparticle fabrication under high-density, small-size, and narrow-pitch packaging conditions. Furthermore, issues such as bridging, tin whisker growth, and intermetallic compound growth during the soldering process can lead to device failure.

⚗Method used

By combining photolithography with metal nanoparticle sintering technology, sealing lines and bumps are prepared on the wafer, patterns are formed by sputtering, and nanoparticles are sintered and bonded at low temperature, simplifying the process flow and improving process redundancy.

🎯Benefits of technology

This technology simplifies the process while efficiently fabricating sealing lines and bumps, reducing production costs, improving device reliability and sealing performance, and meeting the packaging requirements for high density, small size, and narrow pitch.

✦ Generated by Eureka AI based on patent content.

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Abstract

The application provides a wafer-level nanoparticle sintering packaging method for microelectronic device patterning sealing and bump co-bonding. The method comprises the following steps: forming a pattern corresponding to sealing lines and bumps on the surface of a wafer substrate through a photolithography process and a sputtering process; forming a patterned nanoparticle layer; aligning and bonding the wafer with the patterned nanoparticle layer with a wafer with sealing cavities to complete packaging; or making a plurality of chips from the wafer with the patterned nanoparticle layer, and aligning and bonding the chips with the wafer with the sealing cavities respectively to complete packaging; or aligning and bonding the wafer with the patterned nanoparticle layer with a chip with a sealing cavity to complete packaging. The application combines the technology of metal nanoparticle sintering for preparing a bonding layer with a photolithography process, and can simultaneously prepare sealing lines and bumps on a wafer, thereby simplifying the process and further improving the process redundancy.
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