A 3DIC Test Architecture

Abstract

The present invention provides a 3DIC test architecture, including a carrier chip and an upper chip, wherein the carrier chip and the upper chip are embedded with an ijtag network, and the carrier chip and the upper chip are provided with an IJTAG interface, and the ijtag network controlled by the TAP controller on the carrier chip is connected to the ijtag network of the upper chip via the IJTAG interface of the carrier chip, and the signal connected to the IJTAG interface of the upper chip and the control signal of the TAP controller of the upper chip are selected through multiple multiplexers a, and a single test signal is output to the ijtag network of the upper chip. The beneficial effect of this technical solution is that the present invention connects the ijtag network on the carrier chip to the upper chip of the 3D package chip through the multiplexer, and solves the problem of multiplexing the IEEE 1687 network during the 3DIC test process through the TAP controller on the carrier chip.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip testing, and in particular relates to a 3DIC testing architecture. Background Art

[0002] IJTAG (Internal Join Test Action Group) refers to the IEEE 1687 protocol. With the development of integrated circuits, IP is increasingly involved in circuit design. A protocol is needed to access different modules in the chip in a flexible way and solve the delivery of IP test solutions. At the same time, the IEEE 1149.1 and IEEE 1500 protocols have poor scalability, inflexible access, high hardware overhead for a single module, and lack of a suitable description language. These two protocols need to be expanded and developed, so the IEEE1687 protocol came into being.

[0003] The IEEE 1687 protocol defines the Instrument Connectivity Language (ICL) to describe the component connection relationship; it also defines the Procedural Description Language (PDL) to describe the operation of the components, and provides the SIB module. The IEEE 1687 protocol realizes flexible access to different modules based on compatibility with IEEE 1149.1 and IEEE 1500 protocols.

[0004] Modern integrated circuits tend to combine devices from many different sources onto the same chip for packaging. 3D wafer-level packaging is a packaging technology that stacks two or more chips vertically in the same package without changing the size of the package. It originated from the stacked packaging of flash memory and SDRAM. Its advantages include multi-function, high performance, large capacity and high density, multiple functions and applications per unit volume, and low cost.

[0005] In the prior art, the TAP cascade method based on the IEEE 1149 protocol is commonly used for 2DIC testing. In 3DIC testing, if the TAP cascade method based on the IEEE 1149 protocol is used, the configuration time will be too long. The IEEE 1838 protocol for 3DIC testing can flexibly configure each chip. However, there are differences in the way commercial tools support the IEEE 1838 protocol, which has prevented the IEEE 1838 protocol from being promoted. Therefore, in actual project execution, it is hoped that the more mainstream IEEE 1687 protocol will be used to solve the 3DIC testing problem. Summary of the invention

[0006] The present invention provides a 3DIC test architecture, designs a communication method between 3DIC multi-chips based on the IEEE 1687 protocol, and solves the problem of multiplexing the IEEE 1687 network in 3DIC testing.

[0007] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] In order to achieve one or part or all of the above purposes or other purposes, a 3DIC test architecture provided by a technical solution of the present invention includes a carrier chip and an upper chip; an ijtag network is embedded in the carrier chip and the upper chip; an IJTAG interface is provided on the carrier chip and the upper chip, and the ijtag network controlled by the TAP controller on the carrier chip is connected to the ijtag network of the upper chip through the IJTAG interface of the carrier chip, and the signal connected to the IJTAG interface of the upper chip and the control signal of the TAP controller of the upper chip are selected through multiple multiplexers a, and a single test signal is output to the ijtag network of the upper chip. The beneficial effect of this technical solution is that the solution of the present invention connects the ijtag network on the carrier chip to the upper chip of the 3D package chip through the multiplexer a, and controls the entire chip to test the package chip based on the IEEE 1687 protocol through the TAP controller on the carrier chip, thereby solving the problem of multiplexing the IEEE 1687 network during the 3DIC test process.

[0009] An auxiliary SIB module is provided on the carrier chip and the upper chip except the top chip. The auxiliary SIB module is connected to the scan chain formed by the SIB module in the ijtag network. The auxiliary SIB module is connected to the selection signal and the scan input signal in the scan chain, and outputs the selection signal and the scan input signal to the IJTAG interface.

[0010] The IJTAG interface set on the carrier chip and the upper chip includes an interface for transmitting the TCK signal input in the carrier chip test interface; an interface for transmitting the remaining control signals except the host control signal output by the carrier chip TAP controller to the root SIB module; an interface for transmitting the selection signal and the scan input signal output by the auxiliary SIB module; and an interface for returning the scan output signal of the upper chip end SIB module.

[0011] The carrier chip and the upper chip except the top chip are also provided with a virtual position SIB module, and the virtual position SIB module receives the selection signal and the scan input signal output by the auxiliary SIB module; the scan output signal of the virtual position SIB module is transmitted back to the interface end of the auxiliary SIB module.

[0012] When the upper chip is one layer, the upper chip communicates with the carrier chip via the IJTAG interface; when the upper chip has multiple layers, the carrier chip communicates with the upper chip, and between the multiple layers of upper chips via the IJTAG interface.

[0013] The scan output signal of the SIB module at the end of the upper chip returned by the IJTAG interface and the scan output signal of the virtual bit SIB module of the current chip are selected through multiplexer b, and the scan output signal output by the multiplexer b is transmitted to the interface end of the auxiliary SIB module.

[0014] The topmost chip of the packaged chip is not provided with an auxiliary SIB module and a virtual SIB module.

[0015] The upper chip is also embedded with a jtag network, and the jtag network in the upper chip is controlled by a TAP controller of the upper chip; the upper chip is respectively provided with an ijtag network port and a jtag network port.

[0016] The control signals of the multiplexer a and the multiplexer b come from the packaging signal or the TDR signal; when the packaged chip test is performed after stacking, the packaging signal is pulled high so that the upper chip is connected to the ijtag network of the carrier chip through the IJTAG interface; when the wafer test is performed before stacking, the multiplexer a controls the upper chip to access the jtag network or ijtag network of the upper chip through its own TAP controller.

[0017] The scanning test results of the upper chip are read by creating a set of ijtag scanning interfaces for connecting the upper chip in the ICL file of the carrier chip. The scanning test results of the upper chip are returned to the carrier chip through the ICL network, and the ICL file in the carrier chip is extracted through the TAP controller on the carrier chip to read the scanning test results of the upper chip.

[0018] It also includes creating a simulation top-level module in the ICL network, reading in the ICL files of the upper chip and the carrier chip, generating the ICL file of the simulation top-level module, and configuring the ijtag network of the simulation top-level module to simulate the connection between the upper chip of the packaged chip and the carrier chip.

[0019] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. The scheme of the present invention connects the ijtag network on the carrier chip to the upper chip of the 3D package chip through the multiplexer a, and controls the entire chip to test the package chip based on the IEEE 1687 protocol through the TAP controller on the carrier chip, thereby solving the problem of multiplexing the IEEE 1687 network during the 3DIC test process.

[0020] 2. The multiplexer a inserted in the upper chip can be controlled based on the package signal or based on the TDR output signal. During the chip package level test or chip wafer level test, the upper chip selects to access the IEEE 1687 protocol in the carrier chip to test the packaged chip, or performs chip wafer level test based on the ijtag network or jtag network embedded in the upper chip. Testing can be performed according to needs, enriching the test functions.

[0021] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 It is a circuit diagram of the 3DIC test architecture of the present invention.

[0024] Figure 2 This is a circuit diagram of the test architecture when two layers of wafers are sealed in Example 1.

[0025] Figure 3 This is a circuit diagram of the test architecture when three-layer wafers are sealed in Example 1. DETAILED DESCRIPTION

[0026] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0027] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0029] Embodiment 1

[0030] See also Figure 1 The 3DIC test architecture circuit diagram of the present invention includes an ijtag network formed in a carrier chip and an upper chip, and the ijtag network is composed of several SIB modules ( Figure 1 The carrier chip in the figure only gives one SIB module as an example. In the actual ijtag network, several SIB modules may be formed, and corresponding devices may be mounted under the SIB modules to form an access network.

[0031] The TAP controllers of the carrier chip and the upper chip control the ijtag network, where the TAP controller of the carrier chip controls one or more upper chips to perform tests based on the ijtag network, and the TAP controller of the carrier chip sends corresponding control signals (test signals are input to the TAP controller of the carrier chip through the pad of the carrier chip) to the ijtag network of the upper chip. At the same time, the TAP controller of the carrier chip controls the SIB module to send corresponding test signals to the SIB module of the upper chip, and the SIB module of the upper chip transmits the scan results back to the SIB module in the carrier chip to form a loop (see Figure 1 The signal loop is formed by the SIB module of the carrier chip and the SIB module of the upper chip).

[0032] The test signal includes a scan input signal and a selection signal. The scan input signal is used to load the test data into the scan chain to control and observe the internal state of the circuit during the test. The selection signal is used to control the circuit's working mode to switch between the normal working mode and the test mode.

[0033] The signal transmission between the carrier chip and the upper chip is carried out through the Micro Bump (a micro bump used to establish an electrical connection between chips of a packaged wafer or between a chip and a substrate) between the carrier chip and the upper chip. Several Micro Bumps between the carrier chip and the upper chip form a signal transmission interface, through which the control signal of the TAP controller and the test signal of the SIB module are transmitted to the upper chip.

[0034] The following describes the testing of the packaged chip by taking a two-layer packaged chip and a three-layer packaged chip as examples.

[0035] See also Figure 2 The two-layer package chip includes a carrier chip and a second-layer chip, wherein the carrier chip refers to the chip at the bottom of the stacking layer structure. The carrier chip can be selected according to application requirements and technical requirements, and can usually be a logic chip, a dedicated integrated circuit, an interconnect chip, etc. The ijtag network based on the IEEE1687 protocol is embedded in the carrier chip and the upper chip. The ijtag network based on the IEEE 1687 protocol builds an access network (Access Network) through multiple SIB (Segment Insertion Bit) modules, TDR (Test Data Register), controller interface, embedded module interface, etc., wherein the SIB module acts as a switch. When the SIB module is turned on, the signal and data pass through the test equipment (Instrument) mounted on the SIB module. When the SIB module is turned off, the signal and data only flow through the SIB module, not through the test equipment mounted on the SIB module. The TDR (Test Data Register) module is usually controlled and observed through the embedded module interface in the ijtag network. The control, configuration, and operation signals of the TDR are generated by the TAP (Test Access Port) controller. The TDR is divided into three types: write-only, read-only, and writable and readable. The SIB module, mounting device and TDR module in the ijtag network can be designed according to requirements.

[0036] After the test data is received by the TAP controller, a selection signal, a clock signal, TDI data, etc. are sent to the access network where the data conduction direction is controlled by the SIB module for testing. The ijtag access network under the IEEE 1687 protocol is a prior art and will not be described in detail in this application.

[0037] The ijtag network on the carrier chip is controlled by a TAP controller, where the TAP controller is a component of the IEEE 1149.1 protocol test network. The jtag network can be embedded separately in the upper chip. Here, the test of a single wafer is mainly based on the IEEE1149.1 protocol.

[0038] In order to facilitate the testing of packaged chips and the use of mainstream commercial tools, the ijtag network on the carrier chip is connected to the ijtag network of the second-layer chip, and the TAP controller of the carrier chip is used to control the test of the entire packaged chip. Here, the main way to connect the carrier chip to the second-layer chip is to insert a multiplexer a in the second-layer chip through the ECO (Engineering Change Order) method (the ECO method includes: determining requirements, preparing design documents, creating an ECO workspace, designing and inserting multiplexers, verifying, updating test vectors and documents, reviewing and archiving. Inserting multiplexers through the ECO method is a conventional technical solution, which is not described in detail in this application), and at the same time, multiple IJTAG interfaces are set on the carrier chip and the second-layer chip. The IJTAG interface mainly includes transmitting the clock signal TCK in the test signal input on the carrier chip to the interface ijtag_tck of the second-layer chip, and connecting the remaining control signals in the control signal issued by the TAP controller except the host control signal host_1_to_sel to the interface in the ijtag network of the second-layer chip.

[0039] by Figure 2 For example, Figure 2 Among the control signals sent by the TAP controller of the carrier chip, in addition to the host control signal, the signals also include: the control signal capture_dr_en that controls the data register capture operation; the test_logic_reset signal that resets the TAP controller to its initial state; the shift_dr_en signal that enables and controls the data shift process during the shift operation of the data register; the update_dr_en signal that enables and controls the data update process during the update operation of the data register. The interfaces corresponding to the above four signals are interface ijtag_ce, interface ijtag_reset, interface ijtag_se, and interface ijtag_ue.

[0040] The IJTAG interface includes interfaces ijtag_sel and ijtag_si that transmit the selection signal output from the root SIB module on the carrier chip to the SIB module mounted on the root SIB module and the scan input signal to the ijtag network of the layer 2 chip.

[0041] For example, the SIB module connected to the HIP interface of the SIB module mounted on the root SIB module, that is, Figure 2 Auxiliary SIB module sib_aux_die in, Figure 2 The root SIB module in is opened under the control of the selection signal, and the scan input signal ijtag_to_si and the scan selection signal ijtag_to_sel output by the root SIB module enter the auxiliary SIB module. Similarly, the auxiliary SIB module outputs the scan input signal ijtag_to_si and the scan selection signal ijtag_to_sel after being opened.

[0042] The IJTAG interface also includes an interface ijtag_so that transmits the scan output signal of the terminal SIB module in the ijtag network of the upper chip to the carrier chip. Figure 2 Taking the two-layer packaged chip as an example, the end SIB module is the last SIB module in the scan chain.

[0043] In order to facilitate the control of the ijtag network of the second-layer chip, an auxiliary SIB module sib_aux_die and a virtual position SIB module sib_aux_die_dummy are set in the carrier chip, wherein the auxiliary SIB module and the virtual position SIB module do not mount test equipment (their HIP interface does not mount equipment), but the auxiliary SIB module is mounted under the root SIB module, and the virtual position SIB module is mounted under the auxiliary SIB module, and the three form a multi-layer parallel network. The scan output data ijtag_so of the auxiliary SIB module and the virtual position SIB module in the same layer chip are respectively input to the receiving end ijtag_from_so in the root SIB module and the auxiliary SIB module to form a loop. The function of the auxiliary SIB module is to assist the TAP controller in controlling the ijtag network of the upper chip. The auxiliary SIB module transmits the scan input signal ijtag_to_si and the scan selection signal ijtag_to_sel output to the next SIB module to the ijtag network of the second-layer chip through the IJTAG interface (more specifically, the output scan input signal ijtag_to_si and the scan selection signal ijtag_to_sel are used as the scan input signal ijtag_si and the selection signal input ijtag_sel of the root SIB module in the ijtag network of the upper chip) and transmitted to the virtual position SIB module, under which the TDR module is mounted.

[0044] The multiplexer a inserted in the second-layer chip will select the control signal of the TAP controller of the second-layer chip, the test input signal of the second-layer chip, and the clock signal from the IJTAG interface input signal (wherein, the TAP controller in the second-layer chip can be connected to the ijtag network and the jtag network to achieve simultaneous control, or it can be connected only to the ijtag network), and under the control of the control signal, select a unique test signal according to the chip test type to access the upper-layer chip test network. The second-layer chip has an ijtag network based on the IEEE 1686 protocol and a jtag network based on the IEEE 1149.1 protocol controlled by the TAP controller. Correspondingly, there are two network ports (two device interfaces and a module interface) in the hardware architecture of the upper-layer chip. The control signal lines of the multiplexers a are connected to the pads, and the control signals of the multiplexers a come from the package signals and the TDR signals.

[0045] When testing the packaged chip, the control signals of multiplexer a and multiplexer b come from the packaging signal; when testing at the wafer level, the control signals of multiplexer a and multiplexer b come from the TDR output signal. After the chip is packaged, the packaging signal is pulled high and input into the pad, and multiplexer a is controlled to input the clock signal on the carrier chip, the TAP controller control signal, and the scan input signal and selection signal output by the auxiliary SIB module into the ijtag network in the second-layer chip. In this way, when the second-layer chip is tested based on the IEEE 1687 protocol, it can be directly controlled by the TAP controller on the carrier chip, which reduces the time waste of loading the test signal when the TAP controller is cascaded, and improves the test efficiency.

[0046] During wafer-level testing, the control signal of multiplexer a comes from the TDR signal. At this time, multiplexer a selects the TAP controller of the second-layer chip to access the ijtag network or jtag network in the upper-layer chip for wafer-level testing.

[0047] Through the control of multiplexer a, different protocol types can be selected to test the chip according to different test types, thereby expanding the test selectivity and enriching the test functions.

[0048] In order to make the SIB module in the ijtag network form a complete loop, the scan output data of the terminal SIB module in the ijtag network of the second-layer chip is transmitted to the multiplexer b on the carrier chip via the IJTAG interface. The other input data of the multiplexer b is the scan output data of the virtual position SIB module. The control signal of the multiplexer b is the same as the control signal of the multiplexer a mentioned above. When the packaged chip is tested, the package signal is pulled high, and the multiplexer b outputs the scan output data of the terminal SIB module input by the second-layer chip to the receiving end of the auxiliary SIB module. When the wafer-level test is performed, the control signal comes from the TDR signal. At this time, the multiplexer b outputs the scan output data of the virtual position SIB module to the receiving end of the auxiliary SIB module.

[0049] For the testing of multi-layer packaged chips (at least more than 2 layers), Figure 3 Take the 3-layer package chip test in as an example to illustrate. Figure 3 The three-layer packaged chip includes a carrier chip, a second-layer chip and a third-layer chip.

[0050] in Figure 3 Three-layer package chip testing and Figure 2 The difference between the two-layer package chip test in the embodiment is that the carrier chip and the upper chip, and the upper chips communicate with each other through the IJTAG interface. Multiple IJTAG interfaces are set between the carrier chip and the second-layer chip, and multiple IJTAG interfaces are set between the second-layer chip and the third-layer chip. Figure 3 An auxiliary SIB module and a virtual bit SIB module are set on the second-layer chip in the test. At the same time, the auxiliary SIB module of the second-layer chip is set at the very end of the scan chain, and is used to transmit the scan output signal back to the carrier chip through the IJTAG interface. Therefore, when designing the test of multi-layer chips, the position of the auxiliary SIB module is not particularly limited, and it can be in the scan chain formed by the SIB module. However, in order to facilitate the design of the circuit and reduce the interference of the auxiliary SIB module to the circuit, the auxiliary SIB is usually set at the very end of the scan chain or connected to the root SIB module. The connection between the auxiliary SIB module and the virtual bit SIB module in the second-layer chip is similar to Figure 2 The packaging tests of the two layers of chips are the same.

[0051] Other solutions and Figure 2 The two-layer chip packaging test is the same as in the previous section and will not be repeated here.

[0052] Therefore, when there are multiple upper chips for packaging, multiple upper chips (except the topmost upper chip) are all provided with auxiliary SIB modules and virtual SIB modules. The loop formed by the auxiliary SIB module and the virtual SIB module provided on the upper chip is the same as the loop formed by the auxiliary SIB module and the virtual SIB module on the carrier chip. At the same time, an IJTAG interface and a multiplexer a are provided between the upper chips. The IJTAG interface provided between the upper chips is used to receive the control signal from the TAP controller on the carrier chip, the clock signal on the carrier chip, and the scan output data and selection signal from the auxiliary SIB module of the lower chip (the lower chip of the two upper chips for signal transmission). The way in which the signals between the multiple upper chips are connected to the multiplexer a, and the way in which the scan output data of the SIB module at the end of the upper chip are returned to the auxiliary SIB module of the next chip are the same as the two-layer packaged chip test scheme, which will not be repeated here.

[0053] In addition to improving the existing hardware architecture, the 3DIC test architecture in the first embodiment also needs to modify the ICL (Instrument Connection Language, IJTAG network connection language) network accordingly, including inserting multiplexers a and b in the ICL network and modifying the corresponding ICL files so that commercial tools can normally extract and identify ILC networks at different levels. When multiplexer a selects the ICL network connected to the upper chip, the virtual bit SIB module will no longer be accessed.

[0054] At the same time, in order to facilitate the reading of the test content of the upper chip, an additional set of ijtag scanning interfaces for connecting the upper chip is created in the TCL file of the carrier chip. The ICL file of the upper chip can be transferred to the carrier chip through the ijtag interface, and the TAP controller controls the corresponding commercial software to use the standard process to extract the ICL file on the carrier chip to obtain the test results of the upper chip.

[0055] At the same time, in order to simulate the connection between the upper chip and the carrier chip of the packaged wafer, a PseudoTop layer (simulation top module) is created in the ICL network. In the Pseudo Top layer, the ICL files of the upper chip and the carrier chip are read in, and the standard process of commercial software (commercial EDA tools) is used to extract the ICL file of the packaged chip, and the ijtag network is configured in the Pseudo Top layer so that various test points and registers in the upper chip and the carrier chip can be accessed and controlled. The ICL file of the Pseudo Top layer is generated using commercial EDA tools and applied. A unified interface is set on the Pseudo Top layer, the chip is tested according to the generated TCL file, and the results are verified, including the feasibility of the ICL file. Through this method, the test process of the entire packaging system can be managed and controlled at a higher level of abstraction.

[0056] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0057] The above is a detailed introduction to a 3DIC test architecture provided by the present invention. This article uses specific examples to illustrate the architecture and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A 3DIC test architecture, comprising a carrier chip and an upper chip; The carrier chip and the upper chip are embedded with an ijtag network; characterized in that, include: The carrier chip and the upper chip are provided with an IJTAG interface, the ijtag network controlled by the TAP controller on the carrier chip is connected to the ijtag network of the upper chip via the IJTAG interface of the carrier chip, the signal connected to the IJTAG interface of the upper chip and the control signal of the TAP controller of the upper chip are selected by multiple multiplexers a, and a single test signal is output to the ijtag network of the upper chip; The ijtag network is formed by a plurality of SIB modules to form an access network; The TAP controller of the carrier chip will send corresponding control signals to the ijtag network of the upper chip. The TAP controller of the carrier chip will control the SIB module to send corresponding test signals to the SIB module of the upper chip. The SIB module of the upper chip will transmit the scanning results back to the SIB module in the carrier chip to form a loop.

2. A 3DIC test architecture according to claim 1, characterized in that: An auxiliary SIB module is provided on the carrier chip and the upper chip except the top chip. The auxiliary SIB module is connected to the scan chain formed by the SIB module in the ijtag network. The auxiliary SIB module is connected to the selection signal and the scan input signal in the scan chain, and outputs the selection signal and the scan input signal to the IJTAG interface.

3. A 3DIC test architecture according to claim 2, characterized in that: The IJTAG interface set on the carrier chip and the upper chip includes an interface for transmitting the TCK signal input in the carrier chip test interface; an interface for transmitting the remaining control signals except the host control signal output by the carrier chip TAP controller to the root SIB module; an interface for transmitting the selection signal and the scan input signal output by the auxiliary SIB module; and an interface for returning the scan output signal of the upper chip end SIB module.

4. A 3DIC test architecture according to claim 3, characterized in that: The carrier chip and the upper chip except the top chip are also provided with a virtual position SIB module, and the virtual position SIB module receives the selection signal and the scan input signal output by the auxiliary SIB module; the scan output signal of the virtual position SIB module is transmitted back to the interface end of the auxiliary SIB module.

5. A 3DIC test architecture according to any one of claims 1 to 4, characterized in that: When the upper chip is one layer, the upper chip communicates with the carrier chip via the IJTAG interface; when the upper chip has multiple layers, the carrier chip communicates with the upper chip, and between the multiple layers of upper chips via the IJTAG interface.

6. A 3DIC test architecture according to claim 4, characterized in that: The scan output signal of the SIB module at the end of the upper chip returned by the IJTAG interface and the scan output signal of the virtual bit SIB module of the current chip are selected through multiplexer b, and the scan output signal output by the multiplexer b is transmitted to the interface end of the auxiliary SIB module.

7. A 3DIC test architecture according to claim 4, characterized in that: The topmost chip of the packaged chip is not provided with an auxiliary SIB module and a virtual SIB module.

8. The 3DIC test architecture according to claim 1, characterized in that: The upper chip is also embedded with a jtag network, and the jtag network in the upper chip is controlled by a TAP controller of the upper chip; the upper chip is respectively provided with an ijtag network port and a jtag network port.

9. A 3DIC test architecture according to claim 8, characterized in that: The control signals of the multiplexer a and the multiplexer b come from the packaging signal or the TDR signal; when the packaged chip test is performed after stacking, the packaging signal is pulled high so that the upper chip is connected to the ijtag network of the carrier chip through the IJTAG interface; when the wafer test is performed before stacking, the multiplexer a controls the upper chip to access the jtag network or ijtag network of the upper chip through its own TAP controller.

10. The 3DIC test architecture according to claim 1, characterized in that: The scanning test results of the upper chip are read by creating a set of ijtag scanning interfaces for connecting the upper chip in the ICL file of the carrier chip. The scanning test results of the upper chip are returned to the carrier chip through the ICL network, and the ICL file in the carrier chip is extracted through the TAP controller on the carrier chip to read the scanning test results of the upper chip.

11. The 3DIC test architecture according to claim 1, characterized in that: It also includes creating a simulation top-level module in the ICL network, reading in the ICL files of the upper chip and the carrier chip, generating the ICL file of the simulation top-level module, and configuring the ijtag network of the simulation top-level module to simulate the connection between the upper chip of the packaged chip and the carrier chip.

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