Arbitrary waveform generation system and method of multi-bit fault-tolerant superconducting quantum computer

Abstract

The invention relates to the technical field of quantum information, in particular to an arbitrary waveform generation system and method for a multi-bit fault-tolerant superconducting quantum computer, and the system comprises an upper computer which is used for transmitting waveform data and a control signal, reading the state information of an AWG board card, and receiving an AWG return signal; the plurality of AWG board cards are used for waveform output, and the AWG board cards are connected with the upper computer through a high-speed communication link; the AWG board card receives and stores waveform data sent by the upper computer; receiving an instruction sequence, and calling out the stored waveform data according to the instruction sequence; and the waveform data passes through the DAC and then an analog waveform is output. The method has a flexible waveform mode generation mechanism, supports synchronous work of multiple AWG board cards, receives a multi-bit feedback signal, selects a playing waveform according to the feedback signal, can add a new waveform mode when hardware cannot be modified, and does not increase the burden of an upper computer.

Description

Technical Field

[0001] The present invention relates to the field of quantum information technology, and in particular to an arbitrary waveform generation system and method for a multi-bit fault-tolerant superconducting quantum computer. Background Art

[0002] Quantum algorithms usually require precise waveforms to ensure the correct operation of quantum bits. This includes precise control of parameters such as the frequency, amplitude, phase and shape of the waveform. In quantum gate operations, the switch from one waveform to another needs to be completed in a very short time. For example, in an ion trap quantum computer, the control waveform may need to be changed within a few nanoseconds to tens of nanoseconds. Quantum systems often require real-time feedback to correct errors. This requires the waveform generator to dynamically adjust the waveform of subsequent operations based on the results of the previous operation.

[0003] Quantum fault-tolerant computing requires a flexibly configurable AWG (Arbitrary Waveform Generator) to generate manipulated waveforms and to select the next waveform to play based on feedback within nanoseconds. However, existing commercial AWGs are not flexible enough to be configured, and are unable to select and play the next waveform based on external input signals within nanoseconds, which to some extent limits the development of quantum computing. Summary of the invention

[0004] The technical solution provided by the present invention is: an arbitrary waveform generation system for a multi-bit fault-tolerant superconducting quantum computer, comprising: The host computer is used to send waveform data and control signals, read the status information of the AWG board, and receive the AWG return signal; Several AWG boards, used for waveform output, the AWG boards are connected to the host computer via a high-speed communication link; The AWG board can receive synchronization signals sent by other AWG boards to achieve synchronous operation with other AWG boards; The AWG board is capable of receiving feedback information to support error correction codes and sending pre-stored waveforms based on the feedback information; The control signal is composed of a plurality of instruction sequences, and the instruction sequences include a truth table, a macro instruction and a firmware.

[0005] The present invention also provides an arbitrary waveform generation method for a multi-bit fault-tolerant superconducting quantum computer, the method comprising: Receive and store the waveform data sent by the host computer; Receive a command sequence, and call out stored waveform data according to the command sequence; The waveform data is output as an analog waveform after passing through the DAC.

[0006] Preferably, the receiving and storing of waveform data sent by the host computer comprises the following steps: Receive control signals, firmware, and truth tables; The truth table and firmware are stored in the AWG internal memory according to the control signal; The waveform data is stored in the storage area corresponding to the RAM address in the AWG; The RAM address uniquely corresponds to a specific storage area of ​​the AWG; the waveform data stored in the specific area of ​​the AWG can be found through the RAM address.

[0007] Preferably, the step of storing the waveform data in a storage area corresponding to a RAM address in the AWG comprises the following steps: Receive macro instructions and decode them through a decoder; According to the instruction template preset in the firmware, the input macro instruction is divided into multiple atomic instructions for output; Generate RAM address according to the starting address and ending address in the atomic instruction; The waveform data is stored in the storage area corresponding to the RAM address.

[0008] Preferably, the receiving instruction sequence and calling out the stored waveform data according to the instruction sequence comprises the following steps: Analyze atomic instructions through the decoder to identify the intention of atomic instructions; Read the corresponding waveform data through the RAM address and play the waveform data; Get the voltage value in the atomic instruction and output the voltage value.

[0009] Preferably, the method further comprises the steps of: After analyzing the atomic instruction, decide whether to execute the atomic instruction based on the feedback signal; specifically, it includes: Get multiple truth tables; Extract the group number in the atomic instruction; Select the truth table with the corresponding number and output the instruction selection signal to the decoder; The decoder selects the signal according to the input instruction and decides whether to execute the corresponding atomic instruction; After confirming that the synchronization signal is valid, the first atomic instruction is executed to synchronize multiple AWG boards.

[0010] Preferably, the atomic instruction includes a conditional domain and a play domain, the play domain includes a pre-wait time, a pre-wait voltage, RAM address information, a loop, a post-wait time and a post-wait voltage, and the conditional domain includes a conditional validity flag, a truth table selection, a matching value and a group number.

[0011] Preferably, the simulation waveform includes a front-wait voltage, a front-wait time, a waveform, a rear-wait voltage, and a rear-wait time.

[0012] The present invention also provides an electronic device, including a processor and a memory, for executing the arbitrary waveform generation method of the multi-bit fault-tolerant superconducting quantum computer.

[0013] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement the arbitrary waveform generation method of the multi-bit fault-tolerant superconducting quantum computer.

[0014] Beneficial effects of the present invention: The present invention has a flexible waveform mode generation mechanism. The so-called waveform mode is a scheduling instruction such as which segment to play first, which segment to play next, how many times each segment is cycled, how much idle time in between, etc. Through the synchronization signal, it can support the synchronous operation of multiple AWG boards and select the playback waveform according to the feedback signal. When the hardware cannot be modified, a new waveform mode can also be added without increasing the burden on the host computer too much. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a composition structure diagram of the system of the present invention; Figure 2 is a flow chart of the method of the present invention; Figure 3 The atomic instruction format diagram of the present invention; Figure 4 This is a schematic diagram of the structure of the playback domain of the present invention; Figure 5 It is a schematic diagram of the structure of the conditional domain of the present invention. DETAILED DESCRIPTION

[0016] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the present invention defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the present invention.

[0017] It is to be understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the element may be multiple, and the term "one" should not be understood as a limitation on the quantity.

[0018] Please combine Figure 1,The present invention provides an arbitrary waveform generation system for a multi-bit fault-tolerant superconducting quantum computer, comprising: a host computer and a plurality of AWG boards; The host computer and the AWG board are connected via a high-speed communication link, and the host computer sends waveform data and control signals through the high-speed communication link, and reads the status information of the AWG board. In addition to receiving the control signal of the host computer, the AWG board also receives the synchronization signal of other AWG boards for the synchronous operation of multiple AWG boards. In order to support error correction codes, the AWG board can also receive feedback signals from external devices, and when necessary, select to send pre-stored waveforms according to the feedback signals. The control signal is composed of multiple instruction sequences, and the instruction sequence includes a truth table, a macro instruction and a firmware.

[0019] The AWG board consists of a high-speed communication link interface, an instruction processing unit, a waveform RAM, a selector, and a DAC.

[0020] The high-speed communication link interface sends the information sent by the host computer to different modules according to the category. The waveform data is written into the waveform RAM; the truth table is written into the instruction processing unit; the macro instruction is written into the instruction processing unit; and the firmware is written into the instruction processing unit. The instruction processing unit generates a RAM address based on the macro instruction, truth table, synchronization signal and feedback signal, which is used to read out the RAM data at a specific address in the waveform RAM.

[0021] Please combine Figure 2 The present invention also provides an arbitrary waveform generation method for a multi-bit fault-tolerant superconducting quantum computer, comprising the following steps: S1, receiving and storing the waveform data sent by the host computer; specifically comprising the following steps: S11, receiving control signals, firmware, and truth tables; S12, storing the truth table and firmware in the AWG internal memory according to the control signal; S13, storing the waveform data in the storage area corresponding to the RAM address in the AWG, specifically: S131, receiving a macro instruction and decoding it through a decoder; S132, dividing the input macro instruction into multiple atomic instructions for output according to the instruction template preset in the firmware; S133, generating an incremented RAM address according to the start address and end address in the atomic instruction; S134, storing the waveform data in a storage area corresponding to the RAM address in the AWG board; The RAM address uniquely corresponds to a specific storage area of ​​the AWG board; the waveform data stored in the specific area of ​​the AWG board can be found through the RAM address.

[0022] The firmware has built-in preset instruction templates. It inputs a macro instruction and outputs several atomic instructions to form an atomic instruction queue. It should be pointed out that atomic instructions can also be mixed in the macro instruction sequence. After the hardware determines that it is an atomic instruction rather than a macro instruction, it is directly pushed into the atomic instruction queue instead of being handed over to the MCU and firmware memory for decoding and disassembly. The number of atomic instructions corresponding to the macro instruction is completely determined by the firmware, so it can easily support very complex address jump styles. The firmware can also be changed after the hardware is finalized, so that new macro instructions can be supported.

[0023] S2, receiving the instruction sequence, and calling out the stored waveform data according to the instruction sequence, specifically: S21, analyzing the atomic instruction through a decoder to identify the intention of the atomic instruction; S22, read the corresponding waveform data through the RAM address, and broadcast the waveform; S23. Obtain the voltage value in the atomic instruction and output the voltage value.

[0024] Among them, analyzing the atomic instruction through the decoder and identifying the intention of the atomic instruction means: if the atomic instruction requires sending a certain waveform in the waveform RAM, then the decoder generates an incremented RAM address according to the starting address and the ending address in the atomic instruction; if the atomic instruction requires sending the firmware voltage, then the decoder sends out the voltage value in the atomic instruction, which is a constant value in this embodiment, and at the same time, the data source selection instruction issued by the instruction processing unit switches the selector to the receiving voltage.

[0025] S3: The waveform data is output as an analog waveform after passing through the DAC.

[0026] In some cases, it is necessary to decide whether to execute the instruction based on the feedback signal, so the following steps are also included: S210, after analyzing the atomic instruction, determining whether to execute the atomic instruction according to the feedback signal; specifically including: S2101, obtaining multiple truth tables; S2101, extract the group number in the atomic instruction; S2101, select the truth table with the corresponding number, and output the instruction selection signal to the decoder; S2101, the decoder determines whether to execute the corresponding atomic instruction according to the input instruction selection signal; S2101. After confirming that the synchronization signal is valid, start executing the first atomic instruction so that multiple AWG boards are synchronized.

[0027] Please combine Figure 3-4The atomic instruction includes a condition field and a play field, the play field includes a pre-wait time, a pre-wait voltage, RAM address information, a loop, a post-wait time and a post-wait voltage, the condition field includes a conditional validity flag, a truth table selection, a matching value and a group number. The simulation waveform includes a pre-wait voltage, a pre-wait time, a waveform, a post-wait voltage and a post-wait time.

[0028] The conditional valid flag is used to indicate whether the instruction selection is to be considered to determine whether to play. If it is not necessary to consider, the contents of the truth table selection, matching value, and group number are ignored by the decoder.

[0029] If it needs to be considered, the truth table will send out the selected value to select a certain truth table. By comparing the instruction selection with the matching value, you can know whether it needs to be played. It should be noted that the matching value can be more than just a value, it can also contain simple rules, such as comparing only a few bits, playing if equal, or playing if unequal. Since the truth table memory first makes a configurable transformation on the feedback signal, and the matching value can configure the rules, this conditional execution function has greater flexibility.

[0030] The group number is used to indicate which instructions need to be compared at the same time and judged whether to play. When the first instruction in the atomic instruction queue exit needs to be compared (indicated by conditional validity), and several subsequent consecutive instructions also need to be compared, and the group number is the same as the group number of the first instruction, then these instructions must receive instruction selection at the same time (the value selected by the truth table can be determined by the first instruction), and compare with their own matching value to decide whether to play. Instructions that are not played are deleted from the queue.

[0031] The present invention also provides an electronic device, including a processor and a memory, for executing the arbitrary waveform generation method of the multi-bit fault-tolerant superconducting quantum computer.

[0032] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement the arbitrary waveform generation method of the multi-bit fault-tolerant superconducting quantum computer.

[0033] The embodiments disclosed in the present invention, the process described above with reference to the flowchart can be implemented as a computer software program. The embodiments disclosed in the present invention include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part, and / or installed from a removable medium. When the computer program is executed by the central processing unit (CPU), the above-mentioned functions defined in the method of the present application are executed. It should be noted that the above-mentioned computer-readable medium of the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be, for example, but not limited to, a system, device or device of an electrical, magnetic, optical, electromagnetic, infrared segment, or semiconductor, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection with one or more wire segments, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, electrical wire, optical cable, RF, etc., or any suitable combination of the foregoing.

[0034] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0035] Those skilled in the art should understand that the embodiments of the present invention described above and shown in the accompanying drawings are only examples and do not limit the present invention. The objectives of the present invention have been fully and effectively achieved. The functional and structural principles of the present invention have been demonstrated and explained in the embodiments. Without departing from the principles, the implementation methods of the present invention may be deformed or modified in any way.

Claims

1. Arbitrary waveform generation system for multi-bit fault-tolerant superconducting quantum computers, It is characterized in that include: The host computer is used to send waveform data and control signals, read the status information of the AWG board, and receive the AWG return signal; Several AWG boards, used for waveform output, the AWG boards are connected to the host computer via a high-speed communication link; The AWG board can receive synchronization signals sent by other AWG boards to achieve synchronous operation with other AWG boards; The AWG board is capable of receiving feedback signals to support the operation of error correction codes and sending pre-stored waveforms according to the feedback signals; The control signal is composed of a plurality of instruction sequences, and the instruction sequences include a truth table, a macro instruction and a firmware.

2. Arbitrary waveform generation method for multi-bit fault-tolerant superconducting quantum computers, It is characterized in that The method comprises: Receive and store waveform data sent by the host computer; Receive a command sequence, and call out stored waveform data according to the command sequence; The waveform data is output as an analog waveform after passing through the DAC.

3. The method for generating an arbitrary waveform of a multi-bit fault-tolerant superconducting quantum computer according to claim 2, It is characterized in that The receiving and storing of the waveform data sent by the host computer comprises the following steps: Receive control signals, firmware, and truth tables; The truth table and firmware are stored in the AWG internal memory according to the control signal; The waveform data is stored in the storage area corresponding to the RAM address in the AWG; The RAM address uniquely corresponds to a specific storage area of ​​the AWG; the waveform data stored in the specific area of ​​the AWG can be found through the RAM address.

4. The method for generating an arbitrary waveform of a multi-bit fault-tolerant superconducting quantum computer according to claim 2, It is characterized in that The step of storing the waveform data in a storage area corresponding to a RAM address in the AWG comprises the following steps: Receive macro instructions and decode them through a decoder; According to the instruction template preset in the firmware, the input macro instruction is divided into multiple atomic instructions for output; Generate RAM address according to the starting address and ending address in the atomic instruction; The waveform data is stored in the storage area corresponding to the RAM address.

5. The method for generating an arbitrary waveform of a multi-bit fault-tolerant superconducting quantum computer according to claim 4, It is characterized in that The receiving instruction sequence and calling out the stored waveform data according to the instruction sequence comprises the following steps: Analyze atomic instructions through the decoder to identify the intention of atomic instructions; Read the corresponding waveform data through the RAM address and play the waveform data; Get the voltage value in the atomic instruction and output the voltage value.

6. The method for generating an arbitrary waveform of a multi-bit fault-tolerant superconducting quantum computer according to claim 5, It is characterized in that Also includes the steps: After analyzing the atomic instruction, decide whether to execute the atomic instruction based on the feedback signal; specifically, it includes: Get multiple truth tables; Extract the group number in the atomic instruction; Select the truth table with the corresponding number and output the instruction selection signal to the decoder; The decoder selects the signal according to the input instruction and decides whether to execute the corresponding atomic instruction; After confirming that the synchronization signal is valid, the first atomic instruction is executed to synchronize multiple AWG boards.

7. The method for generating an arbitrary waveform for a multi-bit fault-tolerant superconducting quantum computer according to claim 4, It is characterized in that The atomic instruction includes but is not limited to a conditional domain and a play domain, wherein the play domain includes a pre-wait time, a pre-wait voltage, RAM address information, a loop, a post-wait time and a post-wait voltage, and the conditional domain includes a conditional validity flag, a truth table selection, a matching value and a group number.

8. The method for generating an arbitrary waveform of a multi-bit fault-tolerant superconducting quantum computer according to claim 2, It is characterized in that The simulation waveform includes a front waiting voltage, a front waiting time, a waveform, a rear waiting voltage, and a rear waiting time.

9. An electronic device comprising a processor and a memory, It is characterized in that An arbitrary waveform generation method for executing a multi-bit fault-tolerant superconducting quantum computer as described in any one of claims 1-8.

10. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement the arbitrary waveform generation method of a multi-bit fault-tolerant superconducting quantum computer as described in any one of claims 1 to 8.

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