A visual system control method, device, FPGA chip and storage medium based on FPGA

Abstract

The present invention relates to the field of visual detection technology, and provides a visual system control method, device, FPGA chip and storage medium based on FPGA, the method comprising: receiving a first trigger signal input from the outside; wherein the first trigger signal is a high level signal or a low level signal; generating a second trigger signal according to the first trigger signal; inputting the first trigger signal to the light source, and inputting the second trigger signal to the camera, so that the camera performs synchronous shooting when the light source is turned on. The present application generates a second trigger signal according to the first trigger signal, and the camera shooting time can be controlled by the second trigger signal to ensure that the camera performs synchronous shooting when the light source is turned on.

Description

Technical Field

[0001] The present invention relates to the field of visual detection technology, and in particular to a visual system control method and device based on FPGA, an FPGA chip and a storage medium. Background Art

[0002] In the visual system, the camera and the controller can be driven to work by both hard triggering and soft triggering. However, when the trigger signals are not synchronized, the controller will light up the light source first and the camera will take pictures later, or the camera will take pictures first and the controller will light up the light source later.

[0003] This will cause the image obtained after the camera completes the image acquisition to become darker, and the software will not be able to use the algorithm to compare and output the correct result according to the set parameters, and the entire device will not be able to operate normally. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present application provides a FPGA-based visual system control method, device, FPGA chip and storage medium, which are conducive to enabling the camera to accurately perform synchronous shooting when the light source is turned on.

[0005] To solve the above problems, the present invention provides the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a visual system control method based on FPGA, which is applied to an FPGA chip. The method includes:

[0007] Receiving a first trigger signal input from outside; wherein the first trigger signal is a high level signal or a low level signal;

[0008] generating a second trigger signal according to the first trigger signal;

[0009] The first trigger signal is input to the light source, and the second trigger signal is input to the camera, so that the camera performs synchronous shooting when the light source is turned on.

[0010] In some implementations, generating a second trigger signal according to the first trigger signal includes:

[0011] The first trigger signal is copied to generate an identical second trigger signal.

[0012] In some implementations, the step of receiving a first trigger signal input from an external source includes:

[0013] Receiving a first trigger signal input from outside at a first time;

[0014] The step of inputting the first trigger signal to the light source and the second trigger signal to the camera so that the camera performs synchronous shooting when the light source is turned on comprises:

[0015] At a second time, the first trigger signal is input to the light source, and the second trigger signal is input to the camera, so that the camera performs synchronous shooting when the light source is turned on.

[0016] In some embodiments, the time interval between the first time and the second time is greater than or equal to a preset time, the visual system includes a plurality of cameras and a plurality of light sources, and the method further includes:

[0017] Obtaining a first trigger waveform by fitting the first trigger signal received within the preset time;

[0018] When there are two rising edges within the preset time of the first trigger waveform, determining a first duty cycle of the signal in the first preset time and a second duty cycle of the signal in the second preset time of the first trigger waveform; wherein the sum of the first preset time and the second preset time is equal to the preset time;

[0019] determining at least one target light source to be controlled according to the first duty cycle and the second duty cycle;

[0020] Determining a phase difference between a signal in the first preset time and a signal in the second preset time;

[0021] At least one target camera is determined according to the phase difference.

[0022] In some implementations, generating a second trigger signal according to the first trigger signal includes:

[0023] generating a second trigger signal according to the first trigger signal received after a second time;

[0024] The step of inputting the first trigger signal to the light source and the step of inputting the second trigger signal to the camera comprises:

[0025] The first trigger signal received after the second time is sent to the at least one target light source, and the second trigger signal generated according to the first trigger signal received after the second time is input to the at least one target camera.

[0026] In some embodiments, the target light source includes a first target light source and a second target light source, and the method further includes:

[0027] Determine a lighting time difference between the first target light source and the second target light source; wherein the lighting time difference is the difference between the time required for the first target light source to reach maximum brightness and the time required for the second target light source to reach maximum brightness;

[0028] When the second target light source is lit later than the first target light source, generating a third trigger signal delayed by the lighting time difference relative to the first trigger signal according to the lighting time difference;

[0029] The step of inputting the first trigger signal to the light source comprises:

[0030] The third trigger signal is input to the first target light source, and the first trigger signal is input to the second target light source.

[0031] In some implementations, the step of receiving a first trigger signal input from an external source includes:

[0032] receiving the first trigger signal through a first input port;

[0033] The method further comprises:

[0034] When there are two rising edges within a preset time of the first trigger waveform, a correspondence between the first input port and the at least one target light source and the at least one target camera is established; wherein, after the corresponding relationship is established, it is stopped to determine whether there are two rising edges within the preset time.

[0035] In a second aspect, an embodiment of the present application provides a visual system control device based on FPGA, which is applied to an FPGA chip, and the device includes:

[0036] A receiving unit, configured to receive a first trigger signal input from outside; wherein the first trigger signal is a high level signal or a low level signal;

[0037] A generating unit, configured to generate a second trigger signal according to the first trigger signal;

[0038] The input unit is used to input the first trigger signal to the light source and input the second trigger signal to the camera, so that the camera can perform synchronous shooting when the light source is turned on.

[0039] In a third aspect, an embodiment of the present application provides an FPGA chip, wherein the FPGA chip comprises:

[0040] at least one processor; and,

[0041] a memory communicatively connected to the at least one processor; wherein,

[0042] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the FPGA-based vision system control method according to the first aspect.

[0043] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores an executable program, and the executable program is executed by a processor to implement the FPGA-based visual system control method as in the first aspect.

[0044] The present application provides a visual system control method, device, FPGA chip and storage medium based on FPGA, the method comprising: receiving a first trigger signal input from the outside; wherein the first trigger signal is a high level signal or a low level signal; generating a second trigger signal according to the first trigger signal; inputting the first trigger signal to the light source, and inputting the second trigger signal to the camera, so that the camera performs synchronous shooting when the light source is turned on. The present application generates a second trigger signal according to the first trigger signal, and the camera shooting time can be controlled by the second trigger signal to ensure that the camera performs synchronous shooting when the light source is turned on. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a schematic diagram of the FPGA-based vision system provided in this application.

[0046] Figure 2 It is a first flow chart of the FPGA-based visual system control method provided in an embodiment of the present application.

[0047] Figure 3 It is a schematic diagram of a square wave signal waveform provided in an embodiment of the present application.

[0048] Figure 4 This is a second flow chart of the FPGA-based visual system control method provided in an embodiment of the present application.

[0049] Figure 5 It is a structural schematic diagram of an FPGA chip provided in an embodiment of the present application.

[0050] Figure 6 It is a structural block diagram of a computer-readable storage medium provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0052] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0053] See also Figure 1 , Figure 1 Schematic diagram of the FPGA-based visual system provided by this application. Figure 1 As shown, Figure 1 The visual system 1 includes: an FPGA chip 10, a light source 20, a camera driving chip 30 and a camera 40.

[0054] Specifically, a Field-Programmable Gate Array (FPGA) is an integrated circuit (IC) that can be reprogrammed on-site (i.e., after production) to perform specific tasks. FPGA is a highly flexible hardware platform that can implement complex digital logic and algorithms at the hardware level, and therefore has a wide range of applications in many fields.

[0055] like Figure 1 As shown, when the FPGA chip 10 receives the first trigger signal, it sends the first trigger signal to the light source 20 and sends the second trigger signal to the camera driver chip 30. The camera driver chip 30 controls the camera 40 to start capturing images according to the second trigger signal.

[0056] In some embodiments, the FPGA chip 10 instantly copies the first trigger signal, that is, when the FPGA chip 10 receives the first trigger signal, it immediately copies and generates a second trigger signal that is identical to the first trigger signal, thereby achieving synchronous control of the light source and the camera through the high computing power of the FPGA chip 10.

[0057] It is understandable that in order to ensure the immediacy of the generation of the second trigger signal, certain requirements are placed on chip performance. Therefore, this application adopts an FPGA chip, thereby utilizing the high computing power of the FPGA chip to achieve the immediacy of the generation of the second trigger signal.

[0058] However, in some cases, if the FPGA chip needs to control too many devices or modules, interference will occur between the same type of control methods, causing some devices to lose control and affecting the overall function of the device. For example, if multiple trigger signals need to use the same interface, then these signals may compete with each other for these interfaces, resulting in signal loss or erroneous triggering.

[0059] Therefore, in other embodiments, the present application will not immediately copy the first trigger signal, but will wait for a certain period of time to establish a corresponding relationship between the input port for receiving the trigger signal and the camera and optical machine to prevent competition between signals. The specific scheme will be described in the method embodiment.

[0060] And when the FPGA chip has multiple light sources and multiple cameras, it is not necessary to send the first trigger signal to all light sources, nor is it necessary to send the second trigger signal to all cameras. Therefore, it is also necessary to determine the target device corresponding to the trigger signal. The specific solution will be described in the method embodiment.

[0061] In addition, this application is aimed at the scene where the light source is lit and the camera is taken simultaneously. The light source will not be lit for a long time, specifically for the following reasons:

[0062] In some cases, over-illumination can result in overexposed images, i.e., loss of detail in the image, especially for scenes with high reflectivity or large brightness variations. In other cases, even if the light source is always on, the camera's exposure time and readout time still need to be precisely controlled to obtain consistent image quality, and long exposure times will not solve synchronization problems if the synchronization between the camera and the light source is not well managed.

[0063] See also Figure 2 , Figure 2 1 is a schematic diagram of a first flow chart of a visual system control method based on FPGA provided in an embodiment of the present application. Figure 2 As shown, Figure 2 The FPGA-based visual system control method 100 includes: steps 110 to 130.

[0064] Step 110: Receive a first trigger signal input from the outside; wherein the first trigger signal is a high level signal or a low level signal.

[0065] It can be understood that in the present application, the first trigger signal is received in real time, and the first trigger signal received at all times can form a square wave signal waveform.

[0066] See also Figure 3 , Figure 3 Schematic diagram of the square wave signal waveform provided by the embodiment of the present application. Figure 3As shown, at time t1, the first trigger signal received by the FPGA chip is a high level signal, and at time t2, the first trigger signal received by the FPGA chip is a low level state.

[0067] Step 120: Generate a second trigger signal according to the first trigger signal.

[0068] In some implementations, step 120 includes the step of: replicating the first trigger signal to generate an identical second trigger signal.

[0069] Among them, when the control relationship between the camera and the light source controlled by the FPGA chip is relatively simple, the first trigger signal can be directly copied instantly, and the first trigger signal and the second trigger signal are sent simultaneously after the copying, so that the camera can capture images while the light source is turned on.

[0070] Step 130: Input the first trigger signal to the light source, and input the second trigger signal to the camera, so that the camera performs synchronous shooting when the light source is turned on.

[0071] See also Figure 4 , Figure 4 is a second flow chart of the FPGA-based visual system control method provided in the embodiment of the present application. Figure 4 As shown, the FPGA-based visual system control method 200 includes: steps 210 to 230.

[0072] Step 210: Receive a first trigger signal input from outside at a first time.

[0073] Step 220: Generate a second trigger signal according to the first trigger signal.

[0074] Step 230: Input the first trigger signal to the light source at a second time, and input the second trigger signal to the camera, so that the camera performs synchronous shooting when the light source is turned on.

[0075] In the above implementation, the first trigger signal is not input to the light source immediately, but is retained for a certain period of time, during which the first trigger signal is identified to determine how to perform subsequent processing based on the first trigger signal.

[0076] In some embodiments, the above-mentioned determination of how to perform subsequent processing based on the first trigger signal is specifically to determine whether the first trigger signal is a target device determination signal. In this embodiment, it is necessary to first determine at least one target light source and at least one target camera based on the first trigger signal. When the target light source and the target camera are not determined, if a first trigger signal that is not a target device determination signal is received, the first trigger signal is classified as an invalid signal.

[0077] Specifically, the time interval between the first time and the second time is greater than or equal to a preset time, the visual system includes multiple cameras and multiple light sources, and the method of the present application also includes the following steps.

[0078] (1) A first trigger waveform is obtained by fitting a first trigger signal received within the preset time.

[0079] The start time of the first trigger waveform is the first time, the end time is the second time, and the second time is greater than or equal to the first time+the preset time.

[0080] (2) When there are two rising edges within the preset time of the first trigger waveform, determine a first duty cycle of the signal in the first preset time and a second duty cycle of the signal in the second preset time of the first trigger waveform; wherein the sum of the first preset time and the second preset time is equal to the preset time.

[0081] The control method of this embodiment is divided into two stages. The first stage is the stage where the target device is not determined, and the second stage is the control stage after the target device is determined. The same signal will cause the FPGA chip to perform different functions in different stages.

[0082] Optionally, a termination signal function is also provided in the control stage. When the termination signal is received, the first input port receiving the first trigger waveform is untied from the target light source and the target camera, thereby ending the control stage. Therefore, it is necessary to distinguish between normal high-level trigger signals and termination signals in the control stage. In this embodiment, the preset time is set shorter. In the visual system, for example, in scenes such as assembly line detection and foreign object detection, the light source lighting interval is usually in seconds, which is generally higher than 1S / time, that is, a normal high-level trigger signal is usually received only once within 1S. Therefore, the preset time can be in milliseconds, and the setting time is shorter. In 1S, for example, it is set within the range of 300ms to 700ms, such as 300ms, 500ms, 700ms, etc. When there are two rising edges within the preset time of the first trigger waveform, it switches from the first stage to the second stage, and switches from the second stage to the first stage when the termination signal is received. The preset time is set shorter than the actual lighting requirement, so that the normal high-level trigger signal and the termination signal can be distinguished. It can be understood that the number of rising edges in the target device determination signal can be greater than two, but cannot be 1, otherwise the target device determination signal and the ordinary high-level trigger signal cannot be distinguished.

[0083] One possible implementation is that when a waveform identical to the first trigger waveform appears, it is considered that a termination signal is received.

[0084] Another possible implementation is that the termination signal is a specific signal sent by an external device, but the present application does not limit the specific composition of the termination signal.

[0085] (3) Determining at least one target light source to be controlled according to the first duty cycle and the second duty cycle.

[0086] In a possible implementation, the first duty cycle and the second duty cycle have the same meaning, and at least one target light source to be controlled is determined according to the magnitudes of the first duty cycle and the second duty cycle, and each duty cycle corresponds to at least one target light source.

[0087] It can be understood that when the first duty cycle and the second duty cycle are the same, at least one target light source to be controlled can be determined according to the size of the first duty cycle and / or the second duty cycle.

[0088] Exemplarily, a duty cycle of 5% corresponds to the first light source, a duty cycle of 10% corresponds to the second light source, and a duty cycle of 15% corresponds to the first light source and the second light source.

[0089] In another possible implementation manner, the first duty cycle and the second duty cycle represent different meanings.

[0090] For example, the first duty cycle is used to determine the group number of the light source, and the second duty cycle is used to determine the target light source in the group with the group number corresponding to the first duty cycle.

[0091] Exemplarily, the first duty cycle is 5% corresponding to the first group, and the second duty cycle is 5% corresponding to the first light source in the first group; the first duty cycle is 5% corresponding to the first group, and the second duty cycle is 10% corresponding to the second light source in the first group; the first duty cycle is 10% corresponding to the second group, and the second duty cycle is 5% corresponding to the first light source in the second group.

[0092] For another example, the first duty cycle is used to determine the row number of the light source, and the second duty cycle is used to determine the column number of the light source.

[0093] Optionally, when corresponding to different parameters, the change amplitude of the first duty cycle and the second duty cycle is greater than or equal to 5%. For example, when the duty cycle of the first duty cycle corresponding to the first group is 5%, the duty cycle corresponding to the second group is greater than or equal to 5%+5%, thereby preventing external interference from causing duty cycle fluctuations and resulting in incorrect judgments. It can also reduce the requirements for chip processing capabilities, thereby using lower-cost FPGA chips and saving costs.

[0094] (4) Determining a phase difference between the signal in the first preset time and the signal in the second preset time.

[0095] Among them, because the first trigger waveform in the present application is not a traditional square wave signal with a fixed period, the square wave waveform within the first preset time can be regarded as the first square wave, and the square wave waveform within the second preset time can be regarded as the second square wave, and the phase difference between the first square wave and the second square wave is calculated.

[0096] (5) Determine at least one target camera according to the phase difference.

[0097] Exemplarily, a phase difference of 30° corresponds to the first camera, a phase difference of 60° corresponds to the second camera, and a phase difference of 90° corresponds to the first camera and the second camera.

[0098] Optionally, when corresponding to different parameters, the phase difference variation amplitude is greater than or equal to 30°. For example, when the phase difference corresponds to the first camera, it is 30°, and when the phase difference corresponds to the second camera, it is greater than or equal to 30°+30°, thereby preventing external interference from causing phase difference fluctuations and causing judgment errors. It can also reduce the requirements for chip processing capabilities, thereby using lower-cost FPGA chips and saving costs.

[0099] Optionally, an input port can establish multiple corresponding relationships. In this case, the trigger signal received by the input port is processed according to the working cycle, and the number of cycles of the basic working cycle of the input port is set according to the number of corresponding relationships established by the input port, thereby forming a working cycle of each input port, and each basic working cycle corresponds to a corresponding relationship.

[0100] Optionally, the number of cycles of the basic working cycle is equal to the number of corresponding relationships.

[0101] It is understandable that the working cycle of the present application will be continuously cycled. For example, if the working cycle time is 1S, there will be 60 working cycles within 1 minute.

[0102] Exemplarily, the time length of the basic control cycle is 1S, and the number of corresponding relationships of a certain input port is two, then the first 1S in every 2S is used to control the first corresponding relationship, and the last 1S in every 2S is used to control the second corresponding relationship.

[0103] Therefore, when the number of input ports is insufficient, the number of cameras and light sources that can be controlled simultaneously can be increased to save costs. In addition, the working cycle can be set in units of basic working cycles, so that there is a collaborative basis between the corresponding relationships that need to work together. For example, a certain corresponding relationship only corresponds to the light source, and a certain corresponding relationship only corresponds to the camera. The working cycles must be aligned to enable the two to achieve synchronous shooting.

[0104] In some embodiments, step 120 includes the step of generating a second trigger signal based on the first trigger signal received after the second time, and step 140 includes the step of sending the first trigger signal received after the second time to the at least one target light source, and inputting the second trigger signal generated based on the first trigger signal received after the second time to the at least one target camera.

[0105] In the above implementation, the first trigger signal received before the second time is used to determine the target device, not to control the target device. Therefore, the target device should be controlled according to the first trigger signal received after the second time, thereby improving the control logic.

[0106] In some embodiments, the target light source includes a first target light source and a second target light source. In this embodiment, the method of the present application further includes the steps of:

[0107] (1) determining a lighting time difference between the first target light source and the second target light source; wherein the lighting time difference is a difference between a time required for the first target light source to reach a maximum brightness and a time required for the second target light source to reach a maximum brightness;

[0108] (2) when the second target light source is lit later than the first target light source, generating a third trigger signal delayed by the lighting time difference relative to the first trigger signal according to the lighting time difference;

[0109] Based on step (1) and step (2) in this embodiment, the step of inputting the first trigger signal to the light source in step 130 includes the following steps:

[0110] (3) Inputting the third trigger signal to the first target light source, and inputting the first trigger signal to the second target light source.

[0111] Among them, when there are multiple light sources, if there is an inappropriate brightness difference between the multiple light sources, images that the algorithm cannot recognize may be captured, especially when the types of light sources are different. For example, LED lights usually respond very quickly, while incandescent lamps require a period of time to heat the filament to reach maximum brightness. Even if the two receive the first trigger signal to trigger light emission at the same time, the time to reach maximum brightness is different. Therefore, in this embodiment, the lighting time difference between different light sources can be calibrated to solve the above problem.

[0112] Optionally, in this embodiment, a mapping relationship between the total number of switching times of each light source and the lighting time to reach maximum brightness is preset. Each time the light source is switched on and off, the total number of switching times is accumulated and recorded, so that the lighting time difference can be calculated when each light source is lit to reach maximum brightness.

[0113] In some embodiments, step 110 includes the steps of:

[0114] (1) Receive the first trigger signal through the first input port.

[0115] Based on step (1) in this embodiment, the method further includes:

[0116] (2) When there are two rising edges within a preset time of the first trigger waveform, a corresponding relationship between the first input port and the at least one target light source and the at least one target camera is established; wherein, after the corresponding relationship is established, the determination of whether there are two rising edges within the preset time is stopped.

[0117] Among them, the FPGA chip in this application has multiple input ports, and the FPGA chip is connected to multiple light sources and multiple cameras. In order to achieve orderly control, it is necessary to establish a corresponding relationship between the input ports and the light sources and cameras.

[0118] In a possible implementation, multiple input ports may include the same light source and / or camera.

[0119] Among them, in order to prevent the control disorder of the light sources and / or cameras shared by multiple input ports, when a working device (camera or light source) is controlled by multiple input ports at the same time, the FPGA will follow the high-level priority principle and give priority to processing the high-level signals transmitted by the input port to control the working device. For example, if the first input port inputs a low-level signal and the second input port inputs a high-level signal, the high-level signal will be processed first to allow the light source and / or camera corresponding to the second input port to work. That is, at this time, if the first input port and the second input port have a common light source and / or camera, the common light source and / or camera will work.

[0120] Furthermore, for the input ports of the shared light source and / or camera, in order to ensure the orderliness of the operation, each input port operates in the form of a working cycle, and the start time and end time of all working cycles of all input ports are the same. At the end of each working cycle, if a high-level signal is received during the working cycle, the light source and / or camera corresponding to the input port is controlled to operate only at the end of the working cycle.

[0121] Exemplarily, the first input port controls light source 1 , light source 2 and camera 1 , the second input port controls light source 1 , light source 3 and camera 2 , and the two input ports share light source 1 .

[0122] If in a certain working cycle, the first input port and the second input port both receive high level signals, then at the end of the working cycle, light source 1, light source 2, camera 1, light source 3 and camera 2 are controlled to work simultaneously.

[0123] If in a certain working cycle, the first input port receives a high level signal and the second input port does not receive a high level signal, then at the end of the working cycle, light source 1, light source 2 and camera 1 are controlled to work.

[0124] By setting the working cycle, the disorder of control logic can be prevented. For example, when a certain light source is working, a trigger signal for controlling the light source is received. Then, for the camera corresponding to the latter trigger signal, the shooting timing will be later than the timing of the light source lighting up, resulting in blurred image.

[0125] Optionally, the working cycle is less than or equal to 1 second to meet the high-speed shooting requirements.

[0126] In another possible implementation, after a camera and a light source establish a corresponding relationship with one input port, they cannot establish a corresponding relationship with other input ports.

[0127] The working mode of the above working cycle is applicable to most working scenarios. For example, on an assembly line, assuming that the position of each light source and camera is fixed, each assembly line sets a corresponding relationship through an input port. However, in some cases, the position of each camera and light source is not fixed. For example, the shapes, structures, and roughness of different parts to be inspected are different, and the positions of the cameras and light sources need to be adjusted for shooting. Therefore, if only the synchronous exposure time of the camera and light source is controlled without adjusting their positions, a better exposure effect cannot be achieved.

[0128] Optionally, the FPGA chip is also connected to a processing chip, which is connected to at least one position sensor, and the at least one position sensor is used to determine the position of each movable light source and camera. The processing chip is responsible for: 1. Storing and updating the position of each movable light source and camera in real time according to the sensing information of the position sensor; 2. Storing the combination information of the working combination of the light source and the camera, the combination information includes the indicators (such as numbers, letters, etc.) of all light sources and cameras corresponding to the combination, and the reference position of each movable light source and camera under the working combination. 3. Storing the reference position of each movable light source and camera under the non-working combination. 4. The correspondence between each light source and camera and the indicator.

[0129] In the above optional embodiment, the method executed by the FPGA further includes:

[0130] (1) Before establishing a correspondence between an input port and at least one target light source and at least one target camera, an indicator of at least one target light source and at least one target camera is sent to a processing chip, and the processing chip is queried whether the target light source and the target camera constitute a working combination. If so, the FPGA chip obtains the combination information of the working combination to adjust each movable light source and camera to a reference position under the working combination.

[0131] (2) If a working combination is not formed, the processing chip queries whether there is a movable light source or camera in at least one target light source and at least one target camera. If so, the FPGA chip obtains the reference position of the movable light source or camera in the non-working combination to adjust each movable light source and camera to the reference position in the non-working combination.

[0132] Optionally, the position chip can be any chip including a processor, such as a single-chip microcomputer, etc., which is not limited in this application. Optionally, the position sensor can be a camera or a gyroscope, etc., which is not limited in this application.

[0133] The above method can ensure that the light source and the camera are in the correct position during shooting, further ensuring the exposure effect.

[0134] Furthermore, in the present application, the operation of the light source and the camera is controlled in units of working cycles. Therefore, each time the first trigger signal is received, the position chip is used to detect once whether the movable light source and the camera within the current working cycle of the input port are in the correct reference position. If the movable light source and the camera are not in the correct reference position, the movable light source and the camera are controlled to move to the correct reference position.

[0135] However, the movement of the camera and the light source requires time. If the cycle time of the working cycle is less than the cycle time threshold, it can be considered that the movement time of the light source and the camera is insufficient. At this time, the current working cycle and the next working cycle are merged into an adjustment working cycle, and exposure is performed at the end of the adjustment working cycle, thereby giving the camera and the light source enough time to move.

[0136] Optionally, in an actual production process, the cycle time threshold is usually at most 1.5S.

[0137] Exemplarily, if the cycle time of the working cycle is 1S, the working cycle of 0-1S is combined with the working cycle of 1-2S, the trigger signal is received at the 0S, and the exposure is performed at the end of the 2S.

[0138] Furthermore, if multiple corresponding relationships are established for the input port, if the cycle time of the reference working cycle is less than the cycle time threshold, the current reference working cycle and the next reference working cycle are combined into an adjustment working cycle.

[0139] Optionally, sometimes the camera is divided into a main camera and a sub-camera. The main camera usually undertakes the main shooting or monitoring tasks and has a high resolution, stable performance and reliable data transmission capabilities. The sub-camera is used for auxiliary shooting, monitoring specific areas or providing additional viewing angle information to detect specific inspection content. Because the sub-camera is used to inspect special inspection parts, it is not used frequently. Therefore, the FPGA chip may be connected to the main camera, and the main camera is connected to at least one sub-camera. The sub-camera is controlled by the main camera. At this time, in order to prevent the shooting lag of the sub-camera, the method executed by the FPGA chip also includes:

[0140] (1) When receiving the first trigger signal from the external input, determine whether there is a main camera in the corresponding relationship of the input port. If there is a main camera, immediately send the end time of the current working cycle and the working instruction to the main camera in the corresponding relationship, so that the main camera controls itself and the connected sub-camera to capture images at the same time at the end time of the current working cycle.

[0141] (2) At the end of the current working cycle, the light source in the corresponding relationship is controlled to emit light and the camera other than the main camera is controlled to take pictures.

[0142] The embodiment of the present application also provides a visual system control device based on FPGA, which is applied to an FPGA chip, and the device includes:

[0143] A receiving unit, configured to receive a first trigger signal input from outside; wherein the first trigger signal is a high level signal or a low level signal;

[0144] A generating unit, configured to generate a second trigger signal according to the first trigger signal;

[0145] The input unit is used to input the first trigger signal to the light source and input the second trigger signal to the camera, so that the camera can perform synchronous shooting when the light source is turned on.

[0146] In some embodiments, the FPGA-based visual system control device also includes a unit for executing the remaining steps corresponding to any of the above-mentioned method implementations, which will not be described in detail in this application.

[0147] See also Figure 5 , Figure 5 Schematic diagram of the structure of an FPGA chip provided in the embodiment of the present application. Figure 5 As shown, the FPGA chip 300 includes: one or more processors 310 and a memory 320, Figure 5 A processor 310 is taken as an example.

[0148] In some implementations, the processor 310 and the memory 320 may be connected via a bus or other means. Figure 5 The example of connecting through bus is taken in the following.

[0149] In some embodiments, the processor 310 is used to receive a first trigger signal input from the outside; wherein the first trigger signal is a high-level signal or a low-level signal; generate a second trigger signal according to the first trigger signal; input the first trigger signal to the light source, and input the second trigger signal to the camera, so that the camera performs synchronous shooting when the light source is turned on.

[0150] In some embodiments, the memory 320, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as the program instructions / modules of the FPGA-based visual system control method in the embodiment of the present application. The processor 310 executes various functional applications and data processing of the FPGA chip by running the non-volatile software programs, instructions and modules stored in the memory 320, that is, the FPGA-based visual system control method of the above method embodiment is implemented.

[0151] In some embodiments, the memory 320 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required by at least one function; the data storage area may store data created according to the use of the FPGA chip, etc. In addition, the memory 320 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 320 may optionally include a memory remotely arranged relative to the processor 310, and these remote memories may be connected to the controller via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0152] In some embodiments, one or more modules are stored in the memory 320, and when executed by one or more processors 310, the FPGA-based visual system control method in any of the above method embodiments is executed, for example, the above described Figure 2 Method steps 110 to 130 in.

[0153] Please refer to Figure 6 , Figure 6 The computer-readable storage medium 400 stores program code 410, which can be called by a processor to execute the FPGA-based visual system control method described in the above method embodiment.

[0154] The computer-readable storage medium 400 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer-readable storage medium includes a non-transitory computer-readable storage medium. The computer-readable storage medium 400 has a storage space for program codes for executing any method steps in the above control method. These program codes may be read from or written to one or more computer program products. The program code may be compressed, for example, in an appropriate form.

[0155] In summary, the present application provides a visual system control method, device, FPGA chip and storage medium based on FPGA, the method comprising: receiving a first trigger signal input from the outside; wherein the first trigger signal is a high level signal or a low level signal; generating a second trigger signal according to the first trigger signal; inputting the first trigger signal to the light source, and inputting the second trigger signal to the camera, so that the camera performs synchronous shooting when the light source is turned on. The present application generates a second trigger signal according to the first trigger signal, and the camera shooting time can be controlled by the second trigger signal to ensure that the camera performs synchronous shooting when the light source is turned on.

[0156] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A visual system control method based on FPGA, characterized in that: Applied to FPGA chip, the method comprises: Receiving a first trigger signal input from outside; wherein the first trigger signal is a high level signal or a low level signal; The step of receiving a first trigger signal input from an external source comprises: Receiving a first trigger signal input from outside at a first time; generating a second trigger signal according to the first trigger signal; Inputting the first trigger signal to the light source, and inputting the second trigger signal to the camera, so that the camera takes pictures synchronously when the light source is turned on; The step of inputting the first trigger signal to the light source and the second trigger signal to the camera so that the camera performs synchronous shooting when the light source is turned on comprises: Inputting the first trigger signal to the light source at a second time, and inputting the second trigger signal to the camera, so that the camera performs synchronous shooting when the light source is turned on; Wherein, the time interval between the first time and the second time is greater than or equal to a preset time, and the visual system includes a plurality of cameras and a plurality of light sources; Obtaining a first trigger waveform by fitting the first trigger signal received within the preset time; When there are two rising edges within the preset time of the first trigger waveform, determining a first duty cycle of the signal in the first preset time and a second duty cycle of the signal in the second preset time of the first trigger waveform; wherein the sum of the first preset time and the second preset time is equal to the preset time; determining at least one target light source to be controlled according to the first duty cycle and the second duty cycle; Determining a phase difference between a signal in the first preset time and a signal in the second preset time; At least one target camera is determined according to the phase difference.

2. The method according to claim 1, characterized in that The generating a second trigger signal according to the first trigger signal comprises: The first trigger signal is copied to generate an identical second trigger signal.

3. The method according to claim 1, characterized in that The generating a second trigger signal according to the first trigger signal comprises: generating a second trigger signal according to the first trigger signal received after a second time; The step of inputting the first trigger signal to the light source and the step of inputting the second trigger signal to the camera comprises: The first trigger signal received after the second time is sent to the at least one target light source, and the second trigger signal generated according to the first trigger signal received after the second time is input to the at least one target camera.

4. The method according to claim 1, characterized in that: The target light source includes a first target light source and a second target light source, and the method further includes: Determine a lighting time difference between the first target light source and the second target light source; wherein the lighting time difference is the difference between the time required for the first target light source to reach maximum brightness and the time required for the second target light source to reach maximum brightness; When the second target light source is lit later than the first target light source, generating a third trigger signal delayed by the lighting time difference relative to the first trigger signal according to the lighting time difference; The step of inputting the first trigger signal to the light source comprises: The third trigger signal is input to the first target light source, and the first trigger signal is input to the second target light source.

5. The method according to claim 1, characterized in that The step of receiving a first trigger signal input from an external source comprises: receiving the first trigger signal through a first input port; The method further comprises: When there are two rising edges within a preset time of the first trigger waveform, a correspondence between the first input port and the at least one target light source and the at least one target camera is established; wherein, after the corresponding relationship is established, it is stopped to determine whether there are two rising edges within the preset time.

6. A visual system control device based on FPGA, characterized in that: Applied to FPGA chip, the device comprises: A receiving unit, configured to receive a first trigger signal input from outside; wherein the first trigger signal is a high level signal or a low level signal; The receiving unit is specifically configured to receive a first trigger signal input from outside at a first time; A generating unit, configured to generate a second trigger signal according to the first trigger signal; An input unit, used to input the first trigger signal to the light source, and input the second trigger signal to the camera, so that the camera performs synchronous shooting when the light source is turned on; The input unit is specifically used to input the first trigger signal to the light source at a second time, and input the second trigger signal to the camera, so that the camera performs synchronous shooting when the light source is turned on; wherein the time interval between the first time and the second time is greater than or equal to a preset time, and the visual system includes multiple cameras and multiple light sources; The device is also used to obtain a first trigger waveform by fitting a first trigger signal received within the preset time; when there are two rising edges within the preset time of the first trigger waveform, determine a first duty cycle of the signal in the first preset time and a second duty cycle of the signal in the second preset time of the first trigger waveform; wherein the sum of the first preset time and the second preset time is equal to the preset time; determine at least one target light source to be controlled according to the first duty cycle and the second duty cycle; judge the phase difference between the signal in the first preset time and the signal in the second preset time; and determine at least one target camera according to the phase difference.

7. An FPGA chip, characterized in that: The FPGA chip comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the FPGA-based visual system control method as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores an executable program, and the executable program is executed by a processor to implement the FPGA-based visual system control method according to any one of claims 1 to 5.

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