GOOSE message access method and system of energy storage coordination control device based on FPGA

Abstract

The invention discloses a GOOSE (Generic Object Oriented Substation Event) message access method and a GOOSE message access system for an energy storage coordination control device based on an FPGA (Field Programmable Gate Array), a used CPU board card is a CPU + FPGA dual-core architecture, and at a receiving side, the FPGA is responsible for receiving, analyzing and filtering a GOOSE message of a PCS (Personal Computer System), and only uploading an APPID (Advanced Proportion Integration Differentiation) descriptor of a management field and application layer data to the CPU. On the sending side, the CPU only needs to issue the APPID, goID, gocbRef, dataSet and application layer data of the GOOSE message to be sent to the FPGA, and the FPGA carries out GOOSE message packing and sending. According to the method, the GOOSE message access capability of the energy storage power station coordination control device is improved, and the operation efficiency and the processing capability of the energy storage coordination control device are effectively improved, so that the real-time performance of state monitoring and remote control and remote regulation of the PCS is greatly improved.

Description

Technical Field

[0001] The invention relates to a GOOSE message access method and system for an energy storage coordination control device based on FPGA, belonging to the technical field of energy storage power station control. Background Art

[0002] Energy storage has become an important part of the new power system. There is more and more energy storage on the power supply side and the grid side, and the scale of energy storage is getting larger and larger. Energy storage power stations of tens of megawatts or even larger have emerged. The number of energy storage converters (PCS) in these energy storage power stations usually reaches dozens or even hundreds. When so many battery packs and PCS are arranged in the same power station at the same time, the problem of coordinated control arises. Traditional energy management system (EMS) devices are difficult to adapt to the requirements of these large-scale energy storage. Therefore, a control device is needed to centralize and coordinate the control of all PCSs, so that the overall performance of the energy storage power station, especially the transient performance, can be improved and enhanced. The energy storage coordination control device based on the embedded CPU chip has the characteristics of fast sampling, strong computing power, rich communication interfaces, and fast control of GOOSE (generic object-oriented substation event) message communication, and can be applied in large-scale energy storage power station scenarios.

[0003] The coordination control device and PCS communicate through GOOSE messages on optical fiber Ethernet. PCS sends status information to the coordination control device through GOOSE messages, and the coordination control device sends remote control and remote adjustment instructions to PCS through GOOSE messages. The current coordination control device of energy storage power stations is limited by the hardware processing capabilities, such as the processing capabilities of embedded CPU chips. The maximum number of GOOSE control blocks that can be connected to a single device, that is, the number of PCS, generally does not exceed 32. If 256 or even 512 GOOSE control blocks need to be connected, there are two solutions. One is to add a CPU board in the coordination control device, but this will increase costs and the problem of data interaction between multiple CPU boards in the device; the other is to increase the number of coordination control devices, which will lead to a significant increase in overall costs. Summary of the invention

[0004] Purpose of the invention: In order to solve the problem of large-volume GOOSE messages or network storm messages occupying CPU running time and the problem of CPU overload and low operating efficiency, the present invention provides a GOOSE message access method for an energy storage coordination control device based on FPGA.

[0005] Technical solution: To achieve the above purpose, the technical solution adopted by the present invention is:

[0006] A GOOSE message access method for an energy storage coordination control device based on FPGA, comprising the following steps:

[0007] Step S1, using FPGA chip to realize the communication network port of GOOSE network of coordinated control device, connecting industrial switch with optical fiber, and accessing the process layer GOOSE network of energy storage converter PCS.

[0008] Step S2, the CPU chip parses the information of the GOOSE control blocks of all energy storage converters PCS communicating with the coordination control device according to the SCD configuration file of the energy storage power station, and writes it into the configuration buffer of the FPGA chip. Each GOOSE control block configuration information includes the destination MAC address, APPID, goID, gocbRef, dataSet and confRev, the MAC address represents the physical layer address of the Ethernet packet, the APPID represents the GOOSE message application identifier, the goID represents the GOOSE control block identifier, the gocbRef represents the GOOSE control block reference name, the dataSet represents the data set reference name, and the confRev represents the configuration version. The CRC value generated by goID, gocbRef and dataSet after CRC polynomial calculation is written into the FPGA chip.

[0009] Step S3, the FPGA chip filters the key fields of the message received by the communication network port according to the information of the configuration buffer.

[0010] Step S4, establish a stNum buffer inside the FPGA chip, which corresponds one-to-one to the entries in the configuration buffer, use a register to latch the stNum of the current message, and compare it with the stNum of the same entry in the stNum buffer. If they are different, enter the next message parsing logic and update the stNum value of the entry in the stNum buffer. Otherwise, discard the message. stNum represents the GOOSE message status number.

[0011] Step S5, the FPGA chip continues to unpack the current message, parses the application layer data of the GOOSE message, and caches it in the application layer data FIFO. After the message parsing is completed, the APPID of the message and the application layer data in the FIFO are sent to the CPU chip, and the CPU chip processes the application layer data.

[0012] Step S6, the CPU chip sends the APPID, goID, gocbRef, dataSet and application layer data of the GOOSE message to be sent to the FPGA chip, and the FPGA chip packages and sends the GOOSE message according to the descriptors corresponding to the APPID during initialization.

[0013] Preferably: In step S3, the FPGA chip filters the key fields of the message received by the communication network port according to the information of the configuration buffer:

[0014] Step S31, use the register to latch the 1st to 6th bytes of the current message, which is the destination MAC address. The FPGA chip traverses the destination MAC addresses of all GOOSE control blocks. If the same destination MAC address is found, the entry number corresponding to the destination MAC address is recorded and the APPID filtering logic is entered, otherwise the message is discarded.

[0015] Step S32, use the register to latch the APPID of the current message, and compare it with the APPID in the record entry. If they are the same, enter the keyword CRC value judgment logic, otherwise discard the message.

[0016] Step S33, use the register to latch the goID, gocbRef and dataSet of the current message, and use the FPGA chip logic to calculate the CRC value in real time and compare it with the CRC configuration value in the record entry. If they are the same, enter the keyword confRev judgment logic, otherwise the message is discarded.

[0017] Step S34, use the register to latch the confRev of the current message, and compare it with the confRev in the record entry. If they are the same, enter the state sequence number stNum judgment logic, otherwise discard the message.

[0018] Preferably, in step S6, the method for the FPGA chip to package and send the GOOSE message according to the descriptors corresponding to the APPID during initialization is as follows:

[0019] Step S61, the CPU chip sends a data buffer to the FPGA chip and writes the APPID, goID, gocbRef, dataSet and application layer data of the GOOSE message to be sent.

[0020] Step S62, the FPGA chip traverses the configuration buffer according to the APPID, finds the corresponding destination MAC address and confRev, and temporarily stores them using a register.

[0021] Step S63, the FPGA chip reads the time information of the time management module, obtains the current time information, and temporarily stores it in a register.

[0022] Step S64, the FPGA chip reads the application layer data and calculates the CRC value in real time, and then determines whether the CRC value of the application layer data of the previous frame of the MAC address is the same. If the same, stNum remains unchanged and sqNum increases by 1. Otherwise, stNum increases by 1, sqNum is set to 0, and the application layer data CRC value is updated. stNum represents the GOOSE message status number, and sqNum represents the GOOSE message sequence number.

[0023] Step S65, the FPGA chip assembles the packet according to the obtained destination MAC address, confRev, current time information, sqNum, and stNum in accordance with the GOOSE specification and sends the GOOSE message to the switch from the optical fiber network port.

[0024] Preferred: CRC polynomial is: CRC = x 16 +x 13 +x 12 +x 11 +x 10 +x 8 +x 6 +x 5 +x 2 +1, where CRC represents the CRC value of goID, gocbRef or dataSet, and x represents goID, gocbRef or dataSet.

[0025] Preferably: the CPU chip processes the PCS voltage, current, active power and reactive power data of the application layer data.

[0026] Another object of the present invention is to provide a GOOSE message access system for an energy storage coordination control device based on FPGA, which is used to implement the GOOSE message access method for an energy storage coordination control device based on FPGA, and comprises a processing unit, wherein the processing unit is a dual-core architecture of a CPU chip + FPGA chip,

[0027] The FPGA chip is used to implement the communication network port of the GOOSE network of the coordinated control device, connect the industrial switch with optical fiber, and access the process layer GOOSE network of the energy storage converter PCS. The FPGA chip filters the key fields of the message received by the communication network port according to the information of the configuration buffer. An stNum buffer is established inside the FPGA chip, corresponding to the entries of the configuration buffer one by one. The stNum of the current message is latched by a register and compared with the stNum of the same entry in the stNum buffer. If they are different, the next message parsing logic is entered, and the stNum value of the entry in the stNum buffer is updated at the same time, otherwise the message is discarded. The FPGA chip continues to unpack the current message, parses the application layer data of the GOOSE message, and caches it in the application layer data FIFO. After the message parsing is completed, the APPID of the message and the application layer data in the FIFO are sent to the CPU chip together. The FPGA chip packages and sends the GOOSE message according to the descriptors corresponding to the APPID during initialization.

[0028] According to the SCD configuration file of the energy storage power station, the CPU chip parses the information of the GOOSE control blocks of all energy storage converter PCSs that communicate with the coordinated control device and writes them into the configuration buffer of the FPGA chip. The configuration information of each GOOSE control block includes the destination MAC address, APPID, goID, gocbRef, dataSet and confRev. The MAC address represents the physical layer address of the Ethernet packet, the APPID represents the GOOSE message application identifier, the goID represents the GOOSE control block identifier, the gocbRef represents the GOOSE control block reference name, the dataSet represents the data set reference name, and the confRev represents the configuration version. The CRC value generated by the goID, gocbRef and dataSet after the CRC polynomial calculation is written into the FPGA chip. The CPU chip processes the application layer data. The CPU chip sends the APPID, goID, gocbRef, dataSet and application layer data of the GOOSE message to be sent to the FPGA chip.

[0029] Preferably: the FPGA chip uses a register to latch the 1st to 6th bytes of the current message, which is the destination MAC address. The FPGA chip traverses the destination MAC addresses of all GOOSE control blocks. If the same destination MAC address is found, the entry number corresponding to the destination MAC address is recorded and the APPID filtering logic is entered, otherwise the message is discarded. The APPID of the current message is latched using a register and compared with the APPID in the record entry. If they are the same, the keyword CRC value judgment logic is entered, otherwise the message is discarded. The goID, gocbRef and dataSet of the current message are latched using a register, and the CRC value is calculated in real time by the FPGA chip logic and compared with the CRC configuration value in the record entry. If they are the same, the keyword confRev judgment logic is entered, otherwise the message is discarded. The confRev of the current message is latched using a register and compared with the confRev in the record entry. If they are the same, the state sequence number stNum judgment logic is entered, otherwise the message is discarded. stNum represents the GOOSE message state number.

[0030] Preferably: the CPU chip sends a data buffer to the FPGA chip to write the APPID, goID, gocbRef, dataSet and application layer data of the GOOSE message to be sent.

[0031] The FPGA chip traverses the configuration buffer according to the APPID, finds the corresponding destination MAC address and confRev, and uses the register to temporarily store it. The FPGA chip reads the time information of the time management module, obtains the current time information, and uses the register to temporarily store it. The FPGA chip reads the application layer data and calculates the CRC value in real time, and then determines whether the CRC value of the previous frame of application layer data of the MAC address is the same. If the same, stNum remains unchanged and sqNum increases by 1. Otherwise, stNum increases by 1, sqNum is set to 0, and the application layer data CRC value is updated. The FPGA chip assembles the packet according to the GOOSE specification based on the obtained destination MAC address, confRev, current time information, sqNum, and stNum, and sends the GOOSE message from the optical network port to the switch. stNum represents the GOOSE message status number, and sqNum represents the GOOSE message sequence number.

[0032] Another object of the present invention is to provide a computer system, comprising a memory and a processor, wherein the memory is used to store computer programs / instructions. The processor is used to execute the computer programs / instructions to implement the GOOSE message access method of the FPGA-based energy storage coordination control device.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] The present invention breaks through the bottleneck of CPU chip computing power, improves the access capability of GOOSE messages of the energy storage power station coordination control device, and improves the operating efficiency and processing capability of the energy storage coordination control device, thereby greatly improving the real-time performance of PCS status monitoring and remote control and adjustment. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a flowchart of message filtering.

[0036] Figure 2 This is the flow chart of GOOSE message packet sending.

[0037] Figure 3 It is the GOOSE communication test environment for co-control and PCS. DETAILED DESCRIPTION

[0038] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. It should be understood that these examples are only used to illustrate the present invention and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the present invention by those skilled in the art all fall within the scope defined by the claims attached to this application.

[0039] The communication network port of the energy storage coordination control device and multiple PCSs are connected to the switch with optical fiber, and the coordination control device will receive the communication messages sent by all PCSs. The current mainstream device uses the CPU network port to access the GOOSE network of the energy storage power station. Non-subscribed GOOSE messages and network storm messages generated by the network switch will occupy a large amount of CPU running time. In addition, a large number of GOOSE message unpacking and packaging work will cause great consumption of CPU computing power and memory, resulting in excessive CPU load, unable to obtain the status of PCS in real time and accurately, and difficult to send the dispatched remote control and remote adjustment instructions to PCS in time, resulting in a sharp increase in the response time of the entire control system. The number of energy storage converters (PCS) in energy storage power stations of tens of megawatts or even larger scales usually reaches dozens or even hundreds. The energy storage coordination control device based on the embedded CPU chip has the characteristics of fast sampling, strong computing power, rich communication interfaces, and fast control of GOOSE message communication, and can be applied in large-scale energy storage power station scenarios. However, the current mainstream GOOSE message access solution based on the CPU network port significantly reduces the operating efficiency of the device when the number of PCSs reaches more than 128, and even the response time of remote control and remote adjustment instructions cannot meet the requirements of the specification. To this end, we provide a GOOSE message access method for energy storage coordinated control devices based on FPGA, such as Figure 1-3 As shown, the following steps are included:

[0040] Step S1, using FPGA chip to realize the communication network port of GOOSE network of coordinated control device, connecting industrial switch with optical fiber, and accessing the process layer GOOSE network of energy storage converter PCS.

[0041] In step S2, the CPU chip parses the information of the GOOSE control blocks of all energy storage converters PCS that communicate with the coordination control device according to the configuration file SCD of the energy storage power station, and writes it into the configuration buffer of the FPGA chip. The configuration information of each GOOSE control block includes the destination MAC address, APPID, goID, gocbRef, dataSet and confRev. The MAC address represents the physical layer address of the Ethernet packet, the APPID represents the GOOSE message application identifier, the goID represents the GOOSE control block identifier, the gocbRef represents the GOOSE control block reference name, the dataSet represents the data set reference name, and the confRev represents the configuration version. Since the lengths of goID, gocbRef and dataSet are not fixed, the CRC value generated by goID, gocbRef and dataSet is calculated by the CRC polynomial and written into the FPGA chip, which can also reduce the consumption of FPGA resources by the configuration buffer. The CRC polynomial is: CRC=x 16 +x 13 +x 12 +x 11+x 10 +x 8 +x 6 +x 5 +x 2 +1, where CRC represents the CRC value of goID, gocbRef or dataSet, and x represents goID, gocbRef or dataSet.

[0042] Step S3, the FPGA chip filters the key fields of the message received by the communication network port according to the information of the configuration buffer.

[0043] like Figure 1 As shown, the FPGA chip filters the key fields of the message received by the communication network port according to the information of the configuration buffer:

[0044] Step S31, use the register to latch the 1st to 6th bytes of the current message, which is the destination MAC address. The FPGA chip traverses the destination MAC addresses of all GOOSE control blocks. If the same destination MAC address is found, the entry number corresponding to the destination MAC address is recorded and the APPID filtering logic is entered, otherwise the message is discarded.

[0045] Step S32, use the register to latch the APPID of the current message, and compare it with the APPID in the record entry. If they are the same, enter the keyword CRC value judgment logic, otherwise discard the message.

[0046] Step S33, use the register to latch the goID, gocbRef and dataSet of the current message, and use the FPGA chip logic to calculate the CRC value in real time and compare it with the CRC configuration value in the record entry. If they are the same, enter the keyword confRev judgment logic, otherwise the message is discarded.

[0047] Step S34, use the register to latch the confRev of the current message, and compare it with the confRev in the record entry. If they are the same, enter the state sequence number stNum judgment logic, otherwise discard the message.

[0048] Step S4, stNum will change only when the application layer data changes. Therefore, redundant messages with unchanged application layer data can be discarded according to whether stNum changes, reducing invalid data sent to the CPU. An stNum buffer is established inside the FPGA chip, corresponding to the entries in the configuration buffer. The stNum of the current message is latched using a register, and compared with the stNum of the same entry in the stNum buffer. If they are different, the next message parsing logic is entered, and the stNum value of the entry in the stNum buffer is updated at the same time, otherwise the message is discarded. stNum represents the GOOSE message status number.

[0049] Step S5, the FPGA chip continues to unpack the current message, parses the application layer data of the GOOSE message, and caches it in the application layer data FIFO. After the message parsing is completed, the APPID of the message and the application layer data in the FIFO are sent to the CPU chip, and the CPU chip processes the application layer data. The CPU chip processes the PCS voltage, current, active power, reactive power and other data of the application layer data.

[0050] Step S6, in order to enable the coordinated control device to have the ability to quickly send remote control and adjustment instructions to the PCS, the present invention simplifies the data interface between the CPU and the FPGA. The CPU only needs to send the APPID, goID, gocbRef, dataSet and application layer data of the GOOSE message to be sent to the FPGA, and the FPGA packages and sends the GOOSE message according to the descriptors corresponding to the APPID during initialization.

[0051] like Figure 2 As shown, the method for the FPGA chip to package and send the GOOSE message according to the descriptors corresponding to the APPID during initialization is as follows:

[0052] Step S61, the CPU chip sends a data buffer to the FPGA chip and writes the APPID, goID, gocbRef, dataSet and application layer data of the GOOSE message to be sent.

[0053] Step S62, the FPGA chip traverses the configuration buffer according to the APPID, finds the corresponding destination MAC address and confRev, and temporarily stores them using a register.

[0054] Step S63, the FPGA chip reads the time information of the time management module, obtains the current time information, and temporarily stores it in a register.

[0055] Step S64, the FPGA chip reads the application layer data and calculates the CRC value in real time, and then determines whether the CRC value of the application layer data of the previous frame of the MAC address is the same. If the same, stNum remains unchanged and sqNum increases by 1. Otherwise, stNum increases by 1, sqNum is set to 0, and the application layer data CRC value is updated. stNum represents the GOOSE message status number, and sqNum represents the GOOSE message sequence number.

[0056] Step S65, the FPGA chip assembles the packet according to the obtained destination MAC address, confRev, current time information, sqNum, and stNum in accordance with the GOOSE specification and sends the GOOSE message to the switch from the optical fiber network port.

[0057] By utilizing the GOOSE access technology of the coordinated control device based on a field-programmable logic device (FPGA), the messages subscribed by the device can be quickly filtered out from a large number of messages in real time, and hardware unpacking can be performed to parse the application layer data and send it to the CPU, which greatly reduces the GOOSE data that the CPU needs to process. At the same time, the GOOSE messages to be sent by the CPU are packaged by hardware, which solves the bottleneck problem of the CPU processing power and effectively improves the processing power, operating efficiency and real-time remote control of the coordinated control device; it effectively improves the operation level of the energy storage power station and greatly enhances the power supply reliability of the energy storage power station.

[0058] In another embodiment, a GOOSE message access system for an energy storage coordination control device based on FPGA is provided, which is used to implement the GOOSE message access method for an energy storage coordination control device based on FPGA, and includes a processing unit, wherein the processing unit is a dual-core architecture of a CPU chip + an FPGA chip,

[0059] The FPGA chip is used to implement the communication network port of the GOOSE network of the coordinated control device, connect the industrial switch with optical fiber, and access the process layer GOOSE network of the energy storage converter PCS. The FPGA chip filters the key fields of the message received by the communication network port according to the information of the configuration buffer. An stNum buffer is established inside the FPGA chip, corresponding to the entries of the configuration buffer one by one. The stNum of the current message is latched by a register and compared with the stNum of the same entry in the stNum buffer. If they are different, the next message parsing logic is entered, and the stNum value of the entry in the stNum buffer is updated at the same time, otherwise the message is discarded. The FPGA chip continues to unpack the current message, parses the application layer data of the GOOSE message, and caches it in the application layer data FIFO. After the message parsing is completed, the APPID of the message and the application layer data in the FIFO are sent to the CPU chip together. The FPGA chip packages and sends the GOOSE message according to the descriptors corresponding to the APPID during initialization.

[0060] The CPU chip parses the information of the GOOSE control blocks of all energy storage converters PCS that communicate with the coordination control device according to the configuration file SCD of the energy storage power station, and writes it into the configuration buffer of the FPGA chip. The configuration information of each GOOSE control block includes the destination MAC address, APPID, goID, gocbRef, dataSet and confRev. The MAC address represents the physical layer address of the Ethernet packet, the APPID represents the GOOSE message application identifier, the goID represents the GOOSE control block identifier, the gocbRef represents the GOOSE control block reference name, the dataSet represents the data set reference name, and the confRev represents the configuration version. The CRC value generated by the goID, gocbRef and dataSet after the CRC polynomial calculation is written into the FPGA chip. The CPU chip processes the application layer data. The CPU chip sends the APPID, goID, gocbRef, dataSet and application layer data of the GOOSE message to be sent to the FPGA chip.

[0061] The FPGA chip uses a register to latch the 1st to 6th bytes of the current message, which is the destination MAC address. The FPGA chip traverses the destination MAC addresses of all GOOSE control blocks. If the same destination MAC address is found, the entry number corresponding to the destination MAC address is recorded and the APPID filtering logic is entered, otherwise the message is discarded. The APPID of the current message is latched using a register and compared with the APPID in the record entry. If they are the same, the keyword CRC value judgment logic is entered, otherwise the message is discarded. The goID, gocbRef and dataSet of the current message are latched using a register, and the CRC value is calculated in real time by the FPGA chip logic and compared with the CRC configuration value in the record entry. If they are the same, the keyword confRev judgment logic is entered, otherwise the message is discarded. The confRev of the current message is latched using a register and compared with the confRev in the record entry. If they are the same, the state sequence number stNum judgment logic is entered, otherwise the message is discarded. stNum represents the GOOSE message state number.

[0062] The CPU chip sends a data buffer to the FPGA chip and writes the APPID, goID, gocbRef, dataSet and application layer data of the GOOSE message to be sent.

[0063] The FPGA chip traverses the configuration buffer according to the APPID, finds the corresponding destination MAC address and confRev, and uses the register to temporarily store it. The FPGA chip reads the time information of the time management module, obtains the current time information, and uses the register to temporarily store it. The FPGA chip reads the application layer data and calculates the CRC value in real time, and then determines whether the CRC value of the previous frame of application layer data of the MAC address is the same. If the same, stNum remains unchanged and sqNum increases by 1. Otherwise, stNum increases by 1, sqNum is set to 0, and the application layer data CRC value is updated. The FPGA chip assembles the packet according to the GOOSE specification based on the obtained destination MAC address, confRev, current time information, sqNum, and stNum, and sends the GOOSE message from the optical network port to the switch.

[0064] In another embodiment, a computer system is provided, including a memory and a processor, wherein the memory is used to store a computer program / instruction. The processor is used to execute the computer program / instruction to implement the GOOSE message access method of the FPGA-based energy storage coordination control device.

[0065] The CPU board used in the present invention is a dual-core architecture of CPU+FPGA. First, the FPGA only receives subscribed GOOSE messages through MAC address and descriptor filtering logic, thereby greatly reducing the number of messages entering the device.

[0066] Secondly, in order to reduce the CPU's memory and computing power consumption, the receiving side unpacking and sending side assembly of the GOOSE message are completed by the FPGA. On the receiving side, the FPGA is responsible for receiving the GOOSE message from the PCS. After filtering the message as mentioned above, it parses the subscribed GOOSE message according to the specification, processes the state sequence number and sequence sequence number logic, and only sends the APPID descriptor of the management field and the application layer data to the CPU, which greatly reduces the message content and traffic that the CPU needs to process; on the sending side, similarly, the CPU only needs to send the APPID, goID, gocbRef, dataSet and application layer data of the GOOSE message to be sent to the FPGA, and the FPGA assembles and sends the GOOSE message according to the descriptors corresponding to the APPID during initialization.

[0067] FPGA chips have the characteristics of hardware parallel processing, multiple hard-core resources, and logic customizability. They can complete more processing tasks in each clock cycle and have obvious advantages over CPUs in realizing specific logic, data calculation, customized storage, etc. Therefore, the present invention breaks through the computing power bottleneck of CPU chips, improves the access capability of GOOSE messages of the energy storage power station coordination control device, effectively improves the operating efficiency and processing capability of the energy storage coordination control device, and greatly improves the real-time performance of PCS status monitoring, remote control and remote adjustment.

[0068] In another embodiment, a solution for accessing the CPU network port and the PCS through GOOSE messages is provided for comparative testing with the GOOSE message access technology based on FPGA of the present invention. The test environment is as follows: Figure 3 As shown, multiple PCSs form a GOOSE network through switches and two coordination control devices. The main coordination control A is connected to the GOOSE network through the CPU network port, and the main coordination control B is connected to the GOOSE network through the FPGA network port.

[0069] (1) PCS will periodically send status information to the GOOSE network, and the two coordinated control devices will receive GOOSE messages from the same PCS at the same time;

[0070] (2) The two coordinated control devices record the APPID of the parsed GOOSE message and the absolute time when the parsing is completed through file storage, where the receiving time of the main cooperative control A is recorded as t1, and the receiving time of the main cooperative control B is recorded as t2;

[0071] (3) Download the record file from the file system of the coordination control device, count the time difference (t1-t2) between the two coordination control devices when parsing the GOOSE message of the same APPID, and then calculate the average value of the reception time difference of all GOOSE control blocks. The statistical results are shown in Table 1.

[0072] Table 1 Statistics of absolute time difference of GOOSE reception

[0073] Number of PCS accesses Average value of receiving time difference (t1-t2) 32 0.35ms 64 0.47ms 128 3.22ms 256 12.68ms 512 34.27ms

[0074] (4) The workstation sends a frequency modulation command to each of the two coordination control devices, and records the response time from the workstation sending the command to the PCS completing the frequency modulation command. The statistical results are shown in Table 2.

[0075] Table 2 Response time of a frequency modulation instruction

[0076]

[0077] (5) In the GOOSE network, the number of connected PCSs was 32, 64, 128, 256 and 512 respectively, simulating the test environment with different loads and traffic.

[0078] Table 1 is the statistical data of the absolute time difference of the same APPID message parsed by two coordination control devices, and Table 2 is the statistical data of the response time of the workstation sending a frequency modulation instruction to the same PCS through two coordination control devices. It can be seen from Tables 1 and 2 that when the number of PCSs in the GOOSE network is small, the average receiving delay of the two schemes is not much different compared with the CPU network port GOOSE message access scheme, using the FPGA-based coordination control device GOOSE message access technology of the present invention. When the number of PCSs in the GOOSE network increases, the receiving delay of the former is significantly less than that of the latter. This also reflects that when the number of PCSs in the GOOSE network is large, the processing capacity of the coordination control device based on the CPU network port is obviously weak, resulting in a significant increase in the processing time of the remote control and remote adjustment instructions of the workstation.

[0079] According to the "T / CNESA 1005-2021 Technical Specifications for Coordinated Controllers of Electrochemical Energy Storage Power Stations" and the "Architecture and Functional Requirements for Coordinated Control Systems of Energy Storage Power Stations" issued by the Electric Power Research Institute of State Grid Jiangsu Electric Power Co., Ltd. in May 2019, the frequency regulation response time must be less than 90ms. When the number of PCSs in the GOOSE network exceeds 256, the coordinated control device based on the CPU network port is obviously difficult to meet the requirements of the specifications, while the coordinated control device based on FPGA GOOSE message access technology meets the requirements of the specifications and still has a large margin.

[0080] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A GOOSE message access method for an energy storage coordination control device based on FPGA, characterized in that: The following steps are involved: Step S1, using an FPGA chip to realize the communication network port of the GOOSE network of the coordinated control device, connecting the industrial switch with an optical fiber, and accessing the process layer GOOSE network of the energy storage converter PCS; Step S2, the CPU chip parses the information of the GOOSE control blocks of all the energy storage converters PCS communicating with the coordination control device according to the SCD configuration file of the energy storage power station, and writes it into the configuration buffer of the FPGA chip; each GOOSE control block configuration information includes the destination MAC address, APPID, goID, gocbRef, dataSet and confRev, the MAC address represents the physical layer address of the Ethernet packet, the APPID represents the GOOSE message application identifier, the goID represents the GOOSE control block identifier, the gocbRef represents the GOOSE control block reference name, the dataSet represents the data set reference name, and the confRev represents the configuration version. The CRC value generated by the goID, gocbRef and dataSet after the CRC polynomial calculation is written into the FPGA chip; Step S3, the FPGA chip filters the key fields of the message received by the communication network port according to the information of the configuration buffer; Step S4, establish a stNum buffer inside the FPGA chip, which corresponds one-to-one to the entries in the configuration buffer, use a register to latch the stNum of the current message, and compare it with the stNum of the same entry in the stNum buffer. If they are different, enter the next message parsing logic and update the stNum value of the entry in the stNum buffer. Otherwise, discard the message; stNum represents the GOOSE message status number. Step S5, the FPGA chip continues to unpack the current message, parses the application layer data of the GOOSE message, and caches it in the application layer data FIFO; after the message parsing is completed, the APPID of the message and the application layer data in the FIFO are sent to the CPU chip, and the CPU chip processes the application layer data; Step S6, the CPU chip sends the APPID, goID, gocbRef, dataSet and application layer data of the GOOSE message to be sent to the FPGA chip, and the FPGA chip packages and sends the GOOSE message according to the descriptors corresponding to the APPID during initialization.

2. According to the FPGA-based energy storage coordination control device GOOSE message access method of claim 1, it is characterized by: In step S3, the FPGA chip filters the key fields of the message received by the communication network port according to the information of the configuration buffer: Step S31, use the register to latch the 1st to 6th bytes of the current message, which is the destination MAC address. The FPGA chip traverses the destination MAC addresses of all GOOSE control blocks. If the same destination MAC address is found, the entry number corresponding to the destination MAC address is recorded and the APPID filtering logic is entered. Otherwise, the message is discarded. Step S32, use the register to latch the APPID of the current message, and compare it with the APPID in the record entry. If they are the same, enter the keyword CRC value judgment logic, otherwise discard the message; Step S33, use the register to latch the goID, gocbRef and dataSet of the current message, and use the FPGA chip logic to calculate the CRC value in real time, and compare it with the CRC configuration value in the record entry. If they are the same, enter the keyword confRev judgment logic, otherwise discard the message; Step S34, use the register to latch the confRev of the current message, and compare it with the confRev in the record entry. If they are the same, enter the state sequence number stNum judgment logic, otherwise discard the message.

3. According to the FPGA-based energy storage coordination control device GOOSE message access method of claim 2, it is characterized in that: In step S6, the method for the FPGA chip to package and send the GOOSE message according to the descriptors corresponding to the APPID during initialization is as follows; Step S61, the CPU chip sends a data buffer to the FPGA chip and writes APPID, goID, gocbRef, dataSet and application layer data of the GOOSE message to be sent; Step S62, the FPGA chip traverses the configuration buffer according to the APPID, finds the corresponding destination MAC address and confRev, and temporarily stores them in a register; Step S63, the FPGA chip reads the time information of the time management module, obtains the current time information, and temporarily stores it in a register; Step S64, the FPGA chip reads the application layer data and calculates the CRC value in real time, and then determines whether the CRC value of the previous frame of application layer data of the MAC address is the same. If the CRC value is the same, stNum remains unchanged and sqNum increases by 1; otherwise, stNum increases by 1, sqNum is set to 0, and the CRC value of the application layer data is updated; Step S65, the FPGA chip assembles the packet according to the obtained destination MAC address, confRev, current time information, sqNum, and stNum in accordance with the GOOSE specification and sends the GOOSE message to the switch from the optical fiber network port.

4. According to claim 3, the GOOSE message access method of the FPGA-based energy storage coordination control device is characterized in that: The CRC polynomial is: CRC = x 16 +x 13 +x 12 +x 11 +x 10 +x 8 +x 6 +x 5 +x 2 +1, where CRC represents the CRC value of goID, gocbRef or dataSet, and x represents goID, gocbRef or dataSet.

5. The GOOSE message access method of the FPGA-based energy storage coordination control device according to claim 4 is characterized in that: The CPU chip processes the PCS voltage, current, active power, and reactive power data of the application layer data.

6. A GOOSE message access system for energy storage coordination control device based on FPGA, characterized in that: The GOOSE message access method for an FPGA-based energy storage coordination control device according to any one of claims 1 to 4 comprises a processing unit, wherein the processing unit is a dual-core architecture of a CPU chip + an FPGA chip, The FPGA chip is used to realize the communication network port of the GOOSE network of the coordinated control device, connect the industrial switch with optical fiber, and access the process layer GOOSE network of the energy storage converter PCS; the FPGA chip filters the key fields of the message received by the communication network port according to the information of the configuration buffer; establishes a stNum buffer inside the FPGA chip, which corresponds to the entries of the configuration buffer one by one, uses a register to latch the stNum of the current message, and compares it with the stNum of the same entry in the stNum buffer. If they are different, enter the next message parsing logic and update the stNum value of the entry in the stNum buffer at the same time, otherwise the message is discarded; the FPGA chip continues to unpack the current message, parses the application layer data of the GOOSE message, and caches it in the application layer data FIFO; after the message parsing is completed, the APPID of the message and the application layer data in the FIFO are sent to the CPU chip together; the FPGA chip packages the GOOSE message according to the descriptors corresponding to the APPID during initialization and sends it; The CPU chip parses the information of the GOOSE control blocks of all the energy storage converters PCS communicating with the coordination control device according to the configuration file SCD of the energy storage power station, and writes it into the configuration buffer of the FPGA chip; the configuration information of each GOOSE control block includes the destination MAC address, APPID, goID, gocbRef, dataSet and confRev, the MAC address represents the physical layer address of the Ethernet packet, the APPID represents the GOOSE message application identifier, the goID represents the GOOSE control block identifier, the gocbRef represents the GOOSE control block reference name, the dataSet represents the data set reference name, and the confRev represents the configuration version. The CRC value generated by the goID, gocbRef and dataSet after the CRC polynomial calculation is written into the FPGA chip; the CPU chip processes the application layer data; the CPU chip sends the APPID, goID, gocbRef, dataSet and application layer data of the GOOSE message to be sent to the FPGA chip.

7. The GOOSE message access system for energy storage coordination control device based on FPGA according to claim 6 is characterized in that: The FPGA chip uses a register to latch the 1st to 6th bytes of the current message, which is the destination MAC address. The FPGA chip traverses the destination MAC addresses of all GOOSE control blocks. If the same destination MAC address is found, the entry number corresponding to the destination MAC address is recorded and the APPID filtering logic is entered. Otherwise, the message is discarded. Use the register to latch the APPID of the current message and compare it with the APPID in the record entry. If they are the same, enter the keyword CRC value judgment logic, otherwise the message is discarded; use the register to latch the goID, gocbRef and dataSet of the current message, and the CRC value is calculated by the FPGA chip logic in real time, and compared with the CRC configuration value in the record entry. If they are the same, enter the keyword confRev judgment logic, otherwise the message is discarded; use the register to latch the confRev of the current message and compare it with the confRev in the record entry. If they are the same, enter the state number stNum judgment logic, otherwise the message is discarded. stNum represents the GOOSE message status number.

8. The GOOSE message access system for energy storage coordination control device based on FPGA according to claim 7 is characterized in that: The CPU chip sends a data buffer to the FPGA chip and writes the APPID, goID, gocbRef, dataSet and application layer data of the GOOSE message to be sent; The FPGA chip traverses the configuration buffer according to the APPID, finds the corresponding destination MAC address and confRev, and uses the register to temporarily store it; the FPGA chip reads the time information of the time management module, obtains the current time information, and uses the register to temporarily store it; the FPGA chip reads the application layer data and calculates the CRC value in real time, and then determines whether the CRC value of the previous frame of application layer data of the MAC address is the same. If the same, stNum remains unchanged and sqNum increases by 1; otherwise, stNum increases by 1, sqNum is set to 0, and the application layer data CRC value is updated; the FPGA chip assembles the packet according to the GOOSE specification based on the obtained destination MAC address, confRev, current time information, sqNum, and stNum, and sends the GOOSE message from the optical network port to the switch. stNum represents the GOOSE message status number, and sqNum represents the GOOSE message sequence number.

9. A computer system, characterized in that: It includes a memory and a processor, the memory is used to store computer programs / instructions; the processor is used to execute the computer programs / instructions to implement the GOOSE message access method of the FPGA-based energy storage coordination control device as described in any one of claims 1-8.

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