Power Devices

By setting spaced conductive layers on the lining of the power device and connecting the chip with interconnecting members, the problem of poor chip junction temperature consistency is solved, and better heat dissipation effect and lower thermal resistance are achieved.

CN119181691BActive Publication Date: 2025-03-25BEIJING HONGWEI HUAISHI SEMICONDUCTOR CO LTD
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Patent Information

Application Number
CN202411696419.5
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-11-25
Publication Date
2025-03-25
Estimated Expiration
2044-11-25

AI Technical Summary

Technical Problem

The chip layout inside the power device is complex and the chip distribution is relatively concentrated, resulting in poor chip junction temperature consistency.

Method used

A power device is designed, and the liner is provided with spaced first, second and third conductive layers, and the drains of the plurality of chips are electrically connected to the conductive layer, and the electrical connection between the chip and the conductive layer is realized through the interconnecting member, and the heat dissipation area of ​​the chip is increased through the conductive layer.

Benefits of technology

Through this design, the junction temperature consistency of multiple chips is achieved, and the thermal resistance of the power devices is reduced, and the heat dissipation capability is improved.

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Abstract

The present invention provides a power device, the power device comprises: a liner, the upper surface of the liner has a first conductive layer, a second conductive layer and a third conductive layer arranged at intervals, the second conductive layer is located between the first conductive layer and the third conductive layer; a chip assembly, comprising a plurality of first chips and a plurality of second chips, the drain of each first chip is conductively connected to the second conductive layer, and the drain of each second chip is conductively connected to the third conductive layer; a first interconnection member, having a conductive connection part and a plurality of interconnections, the conductive connection part is electrically connected to the first conductive layer, and the plurality of interconnections are conductively connected to the source electrodes of the plurality of first chips in a one-to-one correspondence; a second interconnection member, the second conductive layer is conductively connected to the source electrodes of the plurality of second chips through the second interconnection member. The technical solution provided by the present application can solve the problem of poor chip junction temperature consistency of power devices in the related art.
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