Method for avoiding bad pixels in frame buffer circuit in micro display chip

Abstract

The present invention relates to the field of micro-display technology, and discloses a method for avoiding bad pixels in a frame buffer circuit in a micro-display chip, wherein each address of the frame buffer circuit is written and read to determine the bad pixel address in the frame buffer circuit that cannot correctly implement the write and read operations; the row and column positions of the pixel points of the LED array corresponding to the bad pixel address are determined; pixel data compensation calculation is performed for each bad pixel address; and the LED array pixel points corresponding to each bad pixel address are driven based on the result of the pixel data compensation calculation performed on each bad pixel address. The present invention enables the frame buffer circuit to display the picture correctly even if a large number of circuit defects occur, thereby avoiding display errors caused by abnormalities of the frame buffer circuit.

Description

Technical Field

[0001] The present invention relates to the field of micro-display technology, and in particular to a method for avoiding bad pixels in a frame buffer circuit in a micro-display chip. Background Art

[0002] Micro-display chips in the prior art generally refer to Micro-LED or Micro-OLED micro-display chips. Micro-LED or Micro-OLED micro-display chips refer to display technologies that use self-luminous micron-scale LEDs or OLEDs as light-emitting pixel units and assemble them on a drive panel to form a high-density LED array. Due to the small size, high integration, and self-luminescence of micro-display chips, they have greater advantages in terms of display brightness, resolution, contrast, energy consumption, service life, response speed, and thermal stability. Based on the above advantages, display devices based on micro-display chips can be manufactured into miniature and portable products.

[0003] Since the microdisplay chip adopts a highly integrated design, and the current display driving mode of the microdisplay chip is generally a digital scan drive, it is generally necessary to integrate a frame buffer circuit in the microdisplay chip, that is, under different video interfaces, such as SPI or MIPI interfaces to send video signals, the microdisplay chip receives the video signal and stores the video signal in the frame buffer. The digital scan drive method takes out the video data from the frame buffer according to its specific scanning order and writes it into the pixel array to realize display. This results in a large number of frame buffer circuits in the chip, which often occupy a large area of ​​the chip. The yield of the chip is positively correlated with the chip area, that is, the larger the chip area, the lower the yield. Therefore, when there is a frame buffer inside the chip, the frame buffer circuit is damaged, such as the cache circuit in some positions is abnormal, resulting in abnormal pixel data displayed.

[0004] It can be seen that the prior art requires a bad pixel avoidance method that can keep the micro display chip displaying normally when a storage error occurs in the frame buffer circuit of the micro display chip. Summary of the invention

[0005] The technical purpose to be achieved by the present invention is to provide a method for avoiding bad pixels in a frame buffer circuit in a micro display chip. According to the method for avoiding bad pixels in a frame buffer circuit in a micro display chip, it is possible to maintain normal display of the micro display chip when a storage error occurs in the frame buffer circuit of the micro display chip.

[0006] To achieve the above technical objectives, the present invention provides a method for avoiding bad pixels in a frame buffer circuit in a micro display chip, the method comprising:

[0007] Performing write and read operations on each address of the frame buffer circuit to determine a bad pixel address in the frame buffer circuit where the write and read operations cannot be correctly performed;

[0008] Determine the row and column positions of the pixel points of the LED array corresponding to the bad pixel address;

[0009] A pixel data compensation operation is performed for each bad pixel address, wherein the compensation operation process includes: reading pixel data corresponding to a plurality of pixel points surrounding the pixel point corresponding to the bad pixel address, and calculating pixel data of the pixel point corresponding to the bad pixel address according to the pixel data corresponding to the plurality of pixel points surrounding the pixel point;

[0010] The LED array pixel point corresponding to each bad pixel address is driven based on the result of the pixel data compensation operation performed on each bad pixel address.

[0011] In one embodiment, reading pixel data corresponding to several pixel points surrounding the pixel point corresponding to the bad pixel address includes: reading pixel data D1 of adjacent left pixel points and pixel data D2 of adjacent right pixel points in the same row of pixels of the pixel point corresponding to the bad pixel address; and calculating the average value of the pixel data D1 and the pixel data D2.

[0012] In one embodiment, reading pixel data corresponding to several pixel points surrounding the pixel point corresponding to the bad pixel address includes: reading pixel data D1 of adjacent upper pixel points and pixel data D2 of adjacent lower pixel points in the same column of pixels of the pixel point corresponding to the bad pixel address; and calculating the average value of the pixel data D1 and the pixel data D2.

[0013] In one embodiment, reading pixel data corresponding to a plurality of pixel points around the pixel point corresponding to the bad pixel address includes: reading pixel data D of n pixel points adjacent to the left of the pixel point corresponding to the bad pixel address in the same row of pixels. 11 , D 12 ,……,D 1n and the pixel data D of the adjacent right pixel 21 , D 22 ,……,D 2n ; and pixel data D 11 , D 12 ,……,D 1n and pixel data D 21 , D 22 ,……,D 2n Perform weighted average operation.

[0014] In one embodiment, reading pixel data corresponding to a plurality of pixel points around the pixel point corresponding to the bad pixel address includes: reading pixel data D of n adjacent upper pixel points in the same column of pixels of the pixel point corresponding to the bad pixel address. 11 , D12 ,……,D 1n and the pixel data D of the adjacent lower pixel point 21 , D 22 ,……,D 2n ; and pixel data D 11 , D 12 ,……,D 1n and pixel data D 21 , D 22 ,……,D 2n Perform weighted average operation.

[0015] In one embodiment, reading pixel data corresponding to several pixel points around the pixel point corresponding to the bad pixel address includes: reading pixel data D1 of adjacent left pixel points and pixel data D2 of adjacent right pixel points in the same row of pixels of the pixel point corresponding to the bad pixel address, and simultaneously reading pixel data D3 of adjacent upper pixel points and pixel data D4 of adjacent lower pixel points in the same column of pixels of the pixel point corresponding to the bad pixel address; and calculating the average value of the pixel data D1, pixel data D2, pixel data D3 and pixel data D4.

[0016] In one embodiment, reading pixel data corresponding to a plurality of pixel points around the pixel point corresponding to the bad pixel address includes: reading pixel data D of n pixel points adjacent to the left of the pixel point corresponding to the bad pixel address in the same row of pixels. 11 , D 12 ,……,D 1n , pixel data D of the adjacent right pixel 21 , D 22 ,……,D 2n and the pixel data D of the n adjacent upper pixels in the same column of pixels 31 , D 32 ,……,D 3n and the pixel data D of the adjacent lower pixel point 41 , D 42 ,……,D 4n ; and pixel data D 11 , D 12 ,……,D 1n ; Pixel data D 21 , D 22 ,……,D 2n ; Pixel data D 31 , D 32 ,……,D 3n ; Pixel data D 41 , D 42 ,……,D 4n Perform weighted average operation.

[0017] In one embodiment, the determining of the bad pixel address in the frame buffer circuit where the write and read operations cannot be correctly performed further includes: and recording the error bit in the error data fed back by the bad pixel address.

[0018] In one embodiment, when the number of bad pixel addresses exceeds a predetermined threshold, a pixel data compensation operation is performed for each bad pixel address.

[0019] Compared with the prior art, one or more embodiments of the present invention may have the following advantages:

[0020] In the present invention, by compensating the pixel data of the specific bad points of the frame buffer circuit having problems, even if a large number of circuit defects occur in the frame buffer circuit, the picture can still be displayed correctly, thereby avoiding display errors caused by abnormalities of the frame buffer circuit.

[0021] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0023] Figure 1 is a schematic diagram of the micro display chip structure of the present invention;

[0024] Figure 2 is a flow chart of a bad pixel avoidance method for a frame buffer circuit according to a first embodiment of the present invention;

[0025] Figure 3 is a flow chart of a bad pixel avoidance method for a frame buffer circuit according to a second embodiment of the present invention;

[0026] Figure 4 is a flow chart of a method for avoiding bad pixels in a frame buffer circuit according to a third embodiment of the present invention;

[0027] Figure 5 is a flow chart of a method for avoiding bad pixels in a frame buffer circuit according to a fourth embodiment of the present invention;

[0028] Figure 6 is a flow chart of a bad pixel avoidance method for a frame buffer circuit according to a fifth embodiment of the present invention;

[0029] Figure 7is a flow chart of a method for avoiding bad pixels in a frame buffer circuit according to a sixth embodiment of the present invention;

[0030] Figure 8 4 is a flow chart of a method for avoiding bad pixels in a frame buffer circuit according to a seventh embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings.

[0032] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present invention necessarily has the first element, component, region, layer or part.

[0033] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0034] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] Example 1

[0036] like Figure 1 , as shown in FIG. 2 , the micro display chip of the present invention includes an LED array and a driving circuit, wherein the driving circuit includes a frame buffer circuit, wherein the frame buffer circuit includes an address bit and a corresponding data bit, and each storage address in the frame buffer circuit corresponds to a display pixel in the LED array. For example, when the frame buffer circuit input data bit width is 8 bits, and the resolution of the LED array is 640x480 (i.e., there are 640 columns and 480 rows), the bit width of the frame buffer circuit SRAM is also 8 bits, and one address stores one pixel, then address 0 represents the first row and the first column, address 10 represents the first row and the eleventh column, address 639 represents the first row and the 640th column, address 640 represents the second row and the first column, address 1280 represents the third row and the first column, and so on. When the SRAM bit width is 16 bits, one address stores two pixels, i.e., address 0 represents the first row and the second column pixels, and its high 8 bits are used to express that the first column or the second column pixel can be preset, and similarly. Address 319 represents row 1, column 639-630. As for the bit width of other different SRAMs, one address can store multiple pixels and can be preset.

[0037] like Figure 2 As shown, the bad pixel avoidance method of the frame buffer circuit of this embodiment includes:

[0038] S100, performing write and read operations on each address of the frame buffer circuit to determine a bad pixel address in the frame buffer circuit where the write and read operations cannot be correctly performed.

[0039] In this embodiment, the frame buffer circuit is first accessed by setting registers through the I2C or SPI interface, that is, the address bits and data bits of the frame buffer circuit are directly read and written through the interface that controls the frame buffer circuit. Assuming that the data of the frame buffer is 8 bits wide and the address bit width is 16 bits, when register 0x00[0] is set to 1, debug mode is entered and the frame buffer is controlled by the register. When 0x00[0] is 0, it is a normal working mode and the frame buffer is controlled by the normal video read and write function. When the frame buffer circuit enters debug mode, register 0x00[1] is 1 for writing, 0x00[1] is 0 for reading, register 0x00[2] is 1 for enabling the frame buffer operation, and 0x00[2] is 0 for not operating the frame buffer.

[0040] To write data to the frame buffer circuit, first set the frame buffer address, for example, {0x02, 0x01} two registers control the address, {0x02, 0x01} = 0, read and write address 0, {0x02, 0x01} = 1, read and write address 1. The value of register 0x03 is the value to be written to the address of the frame buffer. For example, to write data 0x5a to address 5, set {0x02, 0x01} = 5, 0x03 = 0x5a, 0x00[0] = 1, 0x00[1] = 1, 0x00[2] = 1 to complete the write operation. Read the value of address 5 and save it in register 0x04. For example, set {0x02, 0x01} = 5, 0x00[0] = 1, 0x00[1] = 0, 0x00[2] = 1 to complete the read operation and store the data of the frame buffer read interface in register 0x04. Read the value of register 0x04 through the i2c or spi interface to get the value of the frame buffer.

[0041] Traverse each address, write 0x00 value first and then read it out, write 0xff value and then read it out, write 0x55 value and then read it out, write 0xaa value and then read it out. That is, the test values ​​are 0x00, 0xff, 0x55, 0xaa. When the read value is different from the written value, it is considered that there is a problem with the frame buffer of this address, that is, this address is saved as an error address in the micro display screen.

[0042] S200, determining the row and column positions of the pixel points of the LED array corresponding to the bad pixel address.

[0043] S300, performing pixel data compensation operation for each bad pixel address, the compensation operation process comprising:

[0044] The pixel data D1 of the adjacent left pixel and the pixel data D2 of the adjacent right pixel in the same row of pixels corresponding to the bad pixel address are read. The pixel data is the grayscale data or brightness data of the LED pixel array when displaying.

[0045] The average value of the pixel data D1 and the pixel data D2 is calculated, that is, (D1+D2) / 2. The average value is the pixel data of the pixel point corresponding to the bad pixel address when it is displayed.

[0046] S400, driving the LED array pixel corresponding to each bad pixel address based on the result of the pixel data compensation operation performed on each bad pixel address.

[0047] Example 2

[0048] like Figure 1 , as shown in FIG3 , the micro display chip of the present invention includes an LED array and a driving circuit, wherein the driving circuit includes a frame buffer circuit, wherein the frame buffer circuit includes an address bit and a corresponding data bit, and each storage address in the frame buffer circuit corresponds to a display pixel in the LED array. For example, when the frame buffer circuit input data bit width is 8 bits, and the resolution of the LED array is 640x480 (i.e., there are 640 columns and 480 rows), the bit width of the frame buffer circuit SRAM is also 8 bits, and one address stores one pixel, then address 0 represents the first row and the first column, address 10 represents the first row and the eleventh column, address 639 represents the first row and the 640th column, address 640 represents the second row and the first column, address 1280 represents the third row and the first column, and so on. When the SRAM bit width is 16 bits, one address stores two pixels, i.e., address 0 represents the first row and the second column pixels, and its high 8 bits are used to express that the first column or the second column pixel can be preset, and similarly. Address 319 represents row 1, column 639-630. As for the bit width of other different SRAMs, one address can store multiple pixels and can be preset.

[0049] like Figure 3 As shown, the bad pixel avoidance method of the frame buffer circuit of this embodiment includes:

[0050] S100, performing write and read operations on each address of the frame buffer circuit to determine a bad pixel address in the frame buffer circuit where the write and read operations cannot be correctly performed.

[0051] In this embodiment, the frame buffer circuit is first accessed by setting registers through the I2C or SPI interface, that is, the address bits and data bits of the frame buffer circuit are directly read and written through the interface that controls the frame buffer circuit. Assuming that the data of the frame buffer is 8 bits wide and the address bit width is 16 bits, when register 0x00[0] is set to 1, debug mode is entered and the frame buffer is controlled by the register. When 0x00[0] is 0, it is a normal working mode and the frame buffer is controlled by the normal video read and write function. When the frame buffer circuit enters debug mode, register 0x00[1] is 1 for writing, 0x00[1] is 0 for reading, register 0x00[2] is 1 for enabling the frame buffer operation, and 0x00[2] is 0 for not operating the frame buffer.

[0052] To write data to the frame buffer circuit, first set the frame buffer address, for example, {0x02, 0x01} two registers control the address, {0x02, 0x01} = 0, read and write address 0, {0x02, 0x01} = 1, read and write address 1. The value of register 0x03 is the value to be written to the address of the frame buffer. For example, to write data 0x5a to address 5, set {0x02, 0x01} = 5, 0x03 = 0x5a, 0x00[0] = 1, 0x00[1] = 1, 0x00[2] = 1 to complete the write operation. Read the value of address 5 and save it in register 0x04. For example, set {0x02, 0x01} = 5, 0x00[0] = 1, 0x00[1] = 0, 0x00[2] = 1 to complete the read operation and store the data of the frame buffer read interface in register 0x04. Read the value of register 0x04 through the i2c or spi interface to get the value of the frame buffer.

[0053] Traverse each address, write 0x00 value first and then read it out, write 0xff value and then read it out, write 0x55 value and then read it out, write 0xaa value and then read it out. That is, the test values ​​are 0x00, 0xff, 0x55, 0xaa. When the read value is different from the written value, it is considered that there is a problem with the frame buffer of this address, that is, this address is saved as an error address in the micro display screen.

[0054] S200, determining the row and column positions of the pixel points of the LED array corresponding to the bad pixel address.

[0055] S300, performing pixel data compensation operation for each bad pixel address, the compensation operation process comprising:

[0056] The pixel data D1 of the adjacent upper pixel and the pixel data D2 of the adjacent lower pixel in the same column of pixels corresponding to the bad pixel address are read. The pixel data is the grayscale data or brightness data of the LED pixel array when displaying.

[0057] The average value of the pixel data D1 and the pixel data D2 is calculated, that is, (D1+D2) / 2. The average value is the pixel data of the pixel point corresponding to the bad pixel address when it is displayed.

[0058] S400, driving the LED array pixel corresponding to each bad pixel address based on the result of the pixel data compensation operation performed on each bad pixel address.

[0059] Example 3

[0060] like Figure 1 , as shown in 4, the micro display chip of the present invention includes an LED array and a driving circuit, wherein the driving circuit includes a frame buffer circuit, wherein the frame buffer circuit includes an address bit and a corresponding data bit, and each storage address in the frame buffer circuit corresponds to a display pixel in the LED array. For example, when the frame buffer circuit input data bit width is 8 bits, and the resolution of the LED array is 640x480 (i.e., there are 640 columns and 480 rows), the bit width of the frame buffer circuit SRAM is also 8 bits, and one address stores one pixel, then address 0 represents the first row and the first column, address 10 represents the first row and the eleventh column, address 639 represents the first row and the 640th column, address 640 represents the second row and the first column, address 1280 represents the third row and the first column, ..., and so on. When the SRAM bit width is 16 bits, one address stores two pixels, i.e., address 0 represents the first row and the second column pixels, and its high 8 bits are used to express that the first column or the second column pixel can be preset, and similarly. Address 319 represents row 1, column 639-630. As for the bit width of other different SRAMs, one address can store multiple pixels and can be preset.

[0061] like Figure 4 As shown, the bad pixel avoidance method of the frame buffer circuit of this embodiment includes:

[0062] S100, performing write and read operations on each address of the frame buffer circuit to determine a bad pixel address in the frame buffer circuit where the write and read operations cannot be correctly performed.

[0063] In this embodiment, the frame buffer circuit is first accessed by setting registers through the I2C or SPI interface, that is, the address bits and data bits of the frame buffer circuit are directly read and written through the interface that controls the frame buffer circuit. Assuming that the data of the frame buffer is 8 bits wide and the address bit width is 16 bits, when register 0x00[0] is set to 1, debug mode is entered and the frame buffer is controlled by the register. When 0x00[0] is 0, it is a normal working mode and the frame buffer is controlled by the normal video read and write function. When the frame buffer circuit enters debug mode, register 0x00[1] is 1 for writing, 0x00[1] is 0 for reading, register 0x00[2] is 1 for enabling the frame buffer operation, and 0x00[2] is 0 for not operating the frame buffer.

[0064] To write data to the frame buffer circuit, first set the frame buffer address, for example, {0x02, 0x01} two registers control the address, {0x02, 0x01} = 0, read and write address 0, {0x02, 0x01} = 1, read and write address 1. The value of register 0x03 is the value to be written to the address of the frame buffer. For example, to write data 0x5a to address 5, set {0x02, 0x01} = 5, 0x03 = 0x5a, 0x00[0] = 1, 0x00[1] = 1, 0x00[2] = 1 to complete the write operation. Read the value of address 5 and save it in register 0x04. For example, set {0x02, 0x01} = 5, 0x00[0] = 1, 0x00[1] = 0, 0x00[2] = 1 to complete the read operation and store the data of the frame buffer read interface in register 0x04. Read the value of register 0x04 through the i2c or spi interface to get the value of the frame buffer.

[0065] Traverse each address, write 0x00 value first and then read it out, write 0xff value and then read it out, write 0x55 value and then read it out, write 0xaa value and then read it out. That is, the test values ​​are 0x00, 0xff, 0x55, 0xaa. When the read value is different from the written value, it is considered that there is a problem with the frame buffer of this address, that is, this address is saved as an error address in the micro display screen.

[0066] S200, determining the row and column positions of the pixel points of the LED array corresponding to the bad pixel address.

[0067] S300, performing pixel data compensation operation for each bad pixel address, the compensation operation process comprising:

[0068] Read the pixel data D of n adjacent left pixels in the same row of pixels corresponding to the bad pixel address 11 , D 12 ,……,D 1nand the pixel data D of the adjacent right pixel 21 , D 22 ,……,D 2n . Where D 11 is the pixel data of the pixel point on the left side closest to the pixel point corresponding to the bad pixel address, D 12 is the pixel data of the pixel point on the left side that is next to the pixel point corresponding to the bad pixel address, and so on; similarly, D 21 D is the pixel data of the pixel point on the right side closest to the pixel point corresponding to the bad pixel address; 22 It is the pixel data of the pixel point on the right side that is next to the pixel point corresponding to the bad pixel address, and so on.

[0069] The pixel data is grayscale data or brightness data of the LED pixel array when displaying.

[0070] And the pixel data D 11 , D 12 ,……,D 1n and pixel data D 21 , D 22 ,……,D 2n A weighted average operation is performed to obtain a pixel data compensation operation value, where the pixel data compensation operation value is the pixel data of the pixel point corresponding to the bad pixel address when being displayed.

[0071] The weighted average operation is:

[0072] [(D 11 +D 21 )*m1+(D 12 +D 22 )*m2+……+(D 1n +D 2n )*m n ] / n

[0073] Among them, the m1, ..., m n is the weight coefficient, and m1, ..., m n It can be set that the weight of the pixel data of the selected pixel points close to the pixel points corresponding to the bad pixel address is greater, while the weight of the pixel data of the selected pixel points far from the pixel points corresponding to the bad pixel address is smaller.

[0074] S400, driving the LED array pixel corresponding to each bad pixel address based on the result of the pixel data compensation operation performed on each bad pixel address.

[0075] Example 4

[0076] like Figure 1, as shown in Figure 5, the micro display chip of the present invention includes an LED array and a driving circuit, wherein the driving circuit includes a frame buffer circuit, wherein the frame buffer circuit includes an address bit and a corresponding data bit, and each storage address in the frame buffer circuit corresponds to a display pixel in the LED array. For example, when the frame buffer circuit input data bit width is 8 bits, and the resolution of the LED array is 640x480 (i.e., there are 640 columns and 480 rows), the bit width of the frame buffer circuit SRAM is also 8 bits, and one address stores one pixel, then address 0 represents the first row and the first column, address 10 represents the first row and the eleventh column, address 639 represents the first row and the 640th column, address 640 represents the second row and the first column, address 1280 represents the third row and the first column, and so on. When the SRAM bit width is 16 bits, one address stores two pixels, i.e., address 0 represents the first row and the second column pixels, and its high 8 bits are used to express that the first column or the second column pixel can be preset, and similarly. Address 319 represents row 1, column 639-630. As for the bit width of other different SRAMs, one address can store multiple pixels and can be preset.

[0077] like Figure 5 As shown, the bad pixel avoidance method of the frame buffer circuit of this embodiment includes:

[0078] S100, performing write and read operations on each address of the frame buffer circuit to determine a bad pixel address in the frame buffer circuit where the write and read operations cannot be correctly performed.

[0079] In this embodiment, the frame buffer circuit is first accessed by setting registers through the I2C or SPI interface, that is, the address bits and data bits of the frame buffer circuit are directly read and written through the interface that controls the frame buffer circuit. Assuming that the data of the frame buffer is 8 bits wide and the address bit width is 16 bits, when register 0x00[0] is set to 1, debug mode is entered and the frame buffer is controlled by the register. When 0x00[0] is 0, it is a normal working mode and the frame buffer is controlled by the normal video read and write function. When the frame buffer circuit enters debug mode, register 0x00[1] is 1 for writing, 0x00[1] is 0 for reading, register 0x00[2] is 1 for enabling the frame buffer operation, and 0x00[2] is 0 for not operating the frame buffer.

[0080] To write data to the frame buffer circuit, first set the frame buffer address, for example, {0x02, 0x01} two registers control the address, {0x02, 0x01} = 0, read and write address 0, {0x02, 0x01} = 1, read and write address 1. The value of register 0x03 is the value to be written to the address of the frame buffer. For example, to write data 0x5a to address 5, set {0x02, 0x01} = 5, 0x03 = 0x5a, 0x00[0] = 1, 0x00[1] = 1, 0x00[2] = 1 to complete the write operation. Read the value of address 5 and save it in register 0x04. For example, set {0x02, 0x01} = 5, 0x00[0] = 1, 0x00[1] = 0, 0x00[2] = 1 to complete the read operation and store the data of the frame buffer read interface in register 0x04. Read the value of register 0x04 through the i2c or spi interface to get the value of the frame buffer.

[0081] Traverse each address, write 0x00 value first and then read it out, write 0xff value and then read it out, write 0x55 value and then read it out, write 0xaa value and then read it out. That is, the test values ​​are 0x00, 0xff, 0x55, 0xaa. When the read value is different from the written value, it is considered that there is a problem with the frame buffer of this address, that is, this address is saved as an error address in the micro display screen.

[0082] S200, determining the row and column positions of the pixel points of the LED array corresponding to the bad pixel address.

[0083] S300, performing pixel data compensation operation for each bad pixel address, the compensation operation process comprising:

[0084] Read the pixel data D of the n adjacent upper pixels in the same column of pixels corresponding to the bad pixel address. 11 , D 12 ,……,D 1n and the pixel data D of the adjacent lower pixel point 21 , D 22 ,……,D 2n . Where D 11 is the pixel data of the pixel point closest to the pixel point corresponding to the bad pixel address on the upper side, D 12 is the pixel data of the pixel point that is next to the pixel point corresponding to the bad pixel address on the upper side, and so on; similarly, D 21 D is the pixel data of the pixel point closest to the pixel point corresponding to the bad pixel address at the lower side; 22 It is the pixel data of the pixel point next to the pixel point corresponding to the bad pixel address at the lower side, and so on.

[0085] The pixel data is grayscale data or brightness data of the LED pixel array when displaying.

[0086] And the pixel data D 11 , D 12 ,……,D 1n and pixel data D 21 , D 22 ,……,D 2n A weighted average operation is performed to obtain a pixel data compensation operation value, where the pixel data compensation operation value is the pixel data of the pixel point corresponding to the bad pixel address when being displayed.

[0087] The weighted average operation is:

[0088] [(D 11 +D 21 )*m1+(D 12 +D 22 )*m2+……+(D 1n +D 2n )*m n ] / n

[0089] Among them, the m1, ..., m n is the weight coefficient, and m1, ..., m n It can be set that the weight of the pixel data of the selected pixel points close to the pixel points corresponding to the bad pixel address is greater, while the weight of the pixel data of the selected pixel points far from the pixel points corresponding to the bad pixel address is smaller.

[0090] S400, driving the LED array pixel corresponding to each bad pixel address based on the result of the pixel data compensation operation performed on each bad pixel address.

[0091] Example 5

[0092] like Figure 1, as shown in FIG6 , the micro display chip of the present invention includes an LED array and a driving circuit, wherein the driving circuit includes a frame buffer circuit, wherein the frame buffer circuit includes an address bit and a corresponding data bit, and each storage address in the frame buffer circuit corresponds to a display pixel in the LED array. For example, when the frame buffer circuit input data bit width is 8 bits, and the resolution of the LED array is 640x480 (i.e., there are 640 columns and 480 rows), the bit width of the frame buffer circuit SRAM is also 8 bits, and one address stores one pixel, then address 0 represents the first row and the first column, address 10 represents the first row and the eleventh column, address 639 represents the first row and the 640th column, address 640 represents the second row and the first column, address 1280 represents the third row and the first column, and so on. When the SRAM bit width is 16 bits, one address stores two pixels, i.e., address 0 represents the first row and the second column pixels, and its high 8 bits are used to express that the first column or the second column pixel can be preset, and similarly. Address 319 represents row 1, column 639-630. As for the bit width of other different SRAMs, one address can store multiple pixels and can be preset.

[0093] like Figure 6 As shown, the bad pixel avoidance method of the frame buffer circuit of this embodiment includes:

[0094] S100, performing write and read operations on each address of the frame buffer circuit to determine a bad pixel address in the frame buffer circuit where the write and read operations cannot be correctly performed.

[0095] In this embodiment, the frame buffer circuit is first accessed by setting registers through the I2C or SPI interface, that is, the address bits and data bits of the frame buffer circuit are directly read and written through the interface that controls the frame buffer circuit. Assuming that the data of the frame buffer is 8 bits wide and the address bit width is 16 bits, when register 0x00[0] is set to 1, debug mode is entered and the frame buffer is controlled by the register. When 0x00[0] is 0, it is a normal working mode and the frame buffer is controlled by the normal video read and write function. When the frame buffer circuit enters debug mode, register 0x00[1] is 1 for writing, 0x00[1] is 0 for reading, register 0x00[2] is 1 for enabling the frame buffer operation, and 0x00[2] is 0 for not operating the frame buffer.

[0096] To write data to the frame buffer circuit, first set the frame buffer address, for example, {0x02, 0x01} two registers control the address, {0x02, 0x01} = 0, read and write address 0, {0x02, 0x01} = 1, read and write address 1. The value of register 0x03 is the value to be written to the address of the frame buffer. For example, to write data 0x5a to address 5, set {0x02, 0x01} = 5, 0x03 = 0x5a, 0x00[0] = 1, 0x00[1] = 1, 0x00[2] = 1 to complete the write operation. Read the value of address 5 and save it in register 0x04. For example, set {0x02, 0x01} = 5, 0x00[0] = 1, 0x00[1] = 0, 0x00[2] = 1 to complete the read operation and store the data of the frame buffer read interface in register 0x04. Read the value of register 0x04 through the i2c or spi interface to get the value of the frame buffer.

[0097] Traverse each address, write 0x00 value first and then read it out, write 0xff value and then read it out, write 0x55 value and then read it out, write 0xaa value and then read it out. That is, the test values ​​are 0x00, 0xff, 0x55, 0xaa. When the read value is different from the written value, it is considered that there is a problem with the frame buffer of this address, that is, this address is saved as an error address in the micro display screen.

[0098] S200, determining the row and column positions of the pixel points of the LED array corresponding to the bad pixel address.

[0099] S300, performing pixel data compensation operation for each bad pixel address, the compensation operation process comprising:

[0100] The pixel data D1 of the adjacent left pixel and the pixel data D2 of the adjacent right pixel in the same row of pixels corresponding to the bad pixel address are read, and the pixel data D3 of the adjacent upper pixel and the pixel data D4 of the adjacent lower pixel in the same column of pixels corresponding to the bad pixel address are read. The pixel data is the grayscale data or brightness data of the LED pixel array when displaying.

[0101] And the average value of the pixel data D1, pixel data D2, pixel data D3 and pixel data D4 is calculated, that is, (D1+D2+D3+D4) / 4, and the average value is the pixel data of the pixel point corresponding to the bad pixel address when it is displayed.

[0102] S400, driving the LED array pixel corresponding to each bad pixel address based on the result of the pixel data compensation operation performed on each bad pixel address.

[0103] Example 6

[0104] like Figure 1 , as shown in 7, the micro display chip of the present invention includes an LED array and a driving circuit, wherein the driving circuit includes a frame buffer circuit, wherein the frame buffer circuit includes an address bit and a corresponding data bit, and each storage address in the frame buffer circuit corresponds to a display pixel in the LED array. For example, when the frame buffer circuit input data bit width is 8 bits, and the resolution of the LED array is 640x480 (i.e., there are 640 columns and 480 rows), the bit width of the frame buffer circuit SRAM is also 8 bits, and one address stores one pixel, then address 0 represents the first row and the first column, address 10 represents the first row and the eleventh column, address 639 represents the first row and the 640th column, address 640 represents the second row and the first column, address 1280 represents the third row and the first column, ..., and so on. When the SRAM bit width is 16 bits, one address stores two pixels, i.e., address 0 represents the first row and the second column pixels, and its high 8 bits are used to express that the first column or the second column pixel can be preset, and similarly. Address 319 represents row 1, column 639-630. As for the bit width of other different SRAMs, one address can store multiple pixels and can be preset.

[0105] like Figure 7 As shown, the bad pixel avoidance method of the frame buffer circuit of this embodiment includes:

[0106] S100, performing write and read operations on each address of the frame buffer circuit to determine a bad pixel address in the frame buffer circuit where the write and read operations cannot be correctly performed.

[0107] In this embodiment, the frame buffer circuit is first accessed by setting registers through the I2C or SPI interface, that is, the address bits and data bits of the frame buffer circuit are directly read and written through the interface that controls the frame buffer circuit. Assuming that the data of the frame buffer is 8 bits wide and the address bit width is 16 bits, when register 0x00[0] is set to 1, debug mode is entered and the frame buffer is controlled by the register. When 0x00[0] is 0, it is a normal working mode and the frame buffer is controlled by the normal video read and write function. When the frame buffer circuit enters debug mode, register 0x00[1] is 1 for writing, 0x00[1] is 0 for reading, register 0x00[2] is 1 for enabling the frame buffer operation, and 0x00[2] is 0 for not operating the frame buffer.

[0108] To write data to the frame buffer circuit, first set the frame buffer address, for example, {0x02, 0x01} two registers control the address, {0x02, 0x01} = 0, read and write address 0, {0x02, 0x01} = 1, read and write address 1. The value of register 0x03 is the value to be written to the address of the frame buffer. For example, to write data 0x5a to address 5, set {0x02, 0x01} = 5, 0x03 = 0x5a, 0x00[0] = 1, 0x00[1] = 1, 0x00[2] = 1 to complete the write operation. Read the value of address 5 and save it in register 0x04. For example, set {0x02, 0x01} = 5, 0x00[0] = 1, 0x00[1] = 0, 0x00[2] = 1 to complete the read operation and store the data of the frame buffer read interface in register 0x04. Read the value of register 0x04 through the i2c or spi interface to get the value of the frame buffer.

[0109] Traverse each address, write 0x00 value first and then read it out, write 0xff value and then read it out, write 0x55 value and then read it out, write 0xaa value and then read it out. That is, the test values ​​are 0x00, 0xff, 0x55, 0xaa. When the read value is different from the written value, it is considered that there is a problem with the frame buffer of this address, that is, this address is saved as an error address in the micro display screen.

[0110] S200, determining the row and column positions of the pixel points of the LED array corresponding to the bad pixel address.

[0111] S300, performing pixel data compensation operation for each bad pixel address, the compensation operation process comprising:

[0112] Read the pixel data D of n adjacent left pixels in the same row of pixels corresponding to the bad pixel address 11 , D 12 ,……,D 1n , pixel data D of the adjacent right pixel 21 , D 22 ,……,D 2n and the pixel data D of the n adjacent upper pixels in the same column of pixels 31 , D 32 ,……,D 3n and the pixel data D of the adjacent lower pixel point 41 , D 42 ,……,D 4n The pixel data is the grayscale data or brightness data of the LED pixel array when displaying.

[0113] And the pixel data D 11 , D 12 ,……,D1n ; Pixel data D 21 , D 22 ,……,D 2n ; Pixel data D 31 , D 32 ,……,D 3n ; Pixel data D 41 , D 42 ,……,D 4n A weighted average operation is performed to obtain a pixel data compensation operation value, where the pixel data compensation operation value is the pixel data of the pixel point corresponding to the bad pixel address when being displayed.

[0114] The weighted average operation is:

[0115] [(D 11 +D 21 +D 31 +D 41 )*m1+(D 12 +D 22 +D 32 +D 42 )*m2+……+(D 1n +D 2n +D 3n +D 4n )*m n ] / n

[0116] Among them, the m1, ..., m n is the weight coefficient, and m1, ..., m n It can be set that the weight of the pixel data of the selected pixel points close to the pixel points corresponding to the bad pixel address is greater, while the weight of the pixel data of the selected pixel points far from the pixel points corresponding to the bad pixel address is smaller.

[0117] S400, driving the LED array pixel corresponding to each bad pixel address based on the result of the pixel data compensation operation performed on each bad pixel address.

[0118] Example 7

[0119] like Figure 1, as shown in FIG8 , the micro display chip of the present invention includes an LED array and a driving circuit, wherein the driving circuit includes a frame buffer circuit, wherein the frame buffer circuit includes an address bit and a corresponding data bit, and each storage address in the frame buffer circuit corresponds to a display pixel in the LED array. For example, when the frame buffer circuit input data bit width is 8 bits, and the resolution of the LED array is 640x480 (i.e., there are 640 columns and 480 rows), the bit width of the frame buffer circuit SRAM is also 8 bits, and one address stores one pixel, then address 0 represents the first row and the first column, address 10 represents the first row and the eleventh column, address 639 represents the first row and the 640th column, address 640 represents the second row and the first column, address 1280 represents the third row and the first column, and so on. When the SRAM bit width is 16 bits, one address stores two pixels, i.e., address 0 represents the first row and the second column pixels, and its high 8 bits are used to express that the first column or the second column pixel can be preset, and similarly. Address 319 represents row 1, column 639-630. As for the bit width of other different SRAMs, one address can store multiple pixels and can be preset.

[0120] like Figure 8 As shown, the bad pixel avoidance method of the frame buffer circuit of this embodiment includes:

[0121] S100, performing write and read operations on each address of the frame buffer circuit to determine a bad pixel address in the frame buffer circuit where the write and read operations cannot be correctly performed, and recording an error bit in the error data fed back by the bad pixel address.

[0122] In this embodiment, the frame buffer circuit is first accessed by setting registers through the I2C or SPI interface, that is, the address bits and data bits of the frame buffer circuit are directly read and written through the interface that controls the frame buffer circuit. Assuming that the data of the frame buffer is 8 bits wide and the address bit width is 16 bits, when register 0x00[0] is set to 1, debug mode is entered and the frame buffer is controlled by the register. When 0x00[0] is 0, it is a normal working mode and the frame buffer is controlled by the normal video read and write function. When the frame buffer circuit enters debug mode, register 0x00[1] is 1 for writing, 0x00[1] is 0 for reading, register 0x00[2] is 1 for enabling the frame buffer operation, and 0x00[2] is 0 for not operating the frame buffer.

[0123] To write data to the frame buffer circuit, first set the frame buffer address, for example, {0x02, 0x01} two registers control the address, {0x02, 0x01} = 0, read and write address 0, {0x02, 0x01} = 1, read and write address 1. The value of register 0x03 is the value to be written to the address of the frame buffer. For example, to write data 0x5a to address 5, set {0x02, 0x01} = 5, 0x03 = 0x5a, 0x00[0] = 1, 0x00[1] = 1, 0x00[2] = 1 to complete the write operation. Read the value of address 5 and save it in register 0x04. For example, set {0x02, 0x01} = 5, 0x00[0] = 1, 0x00[1] = 0, 0x00[2] = 1 to complete the read operation and store the data of the frame buffer read interface in register 0x04. Read the value of register 0x04 through the i2c or spi interface to get the value of the frame buffer.

[0124] Traverse each address, write 0x00 value first and then read it out, write 0xff value and then read it out, write 0x55 value and then read it out, write 0xaa value and then read it out. That is, the test values ​​are 0x00, 0xff, 0x55, 0xaa. When the read value is different from the written value, it is considered that there is a problem with the frame buffer of this address, that is, this address is saved as an error address in the micro display screen.

[0125] S200, determining the row and column positions of the pixel points of the LED array corresponding to the bad pixel address.

[0126] S300, performing pixel data compensation operation for each bad pixel address, wherein the compensation operation process uses the pixel data compensation operation method used in the above-mentioned embodiments 1 to 6.

[0127] S400, based on the result of the pixel data compensation operation performed on each bad pixel address, the error bits in the error data fed back by the bad pixel address are corrected. That is, only some bits of the 8-bit value read out in the error data are wrong, while the other bits are correct. Assuming that the data is 8 bits, 8 bits of bit error information are also stored following the error address information. When the bit of this 8-bit bit error information is 1, it means that there is no error in its bit, and when it is 0, it means that the corresponding bit is wrong. For example, if only bit1 of this address is wrong, the saved bit error information value should be 11111101, and only Bit1 is 0. If there are errors in bit2 and bit6 of this address, the saved bit error information value should be 10111011, that is, bit6 and bit2 are 0. The method of the above implementation column is added with the bit error information to obtain the final display value. For example, if the result obtained by the above calculation is x, read the data and bit error information of this pixel, retain the correct bit of this pixel, and fill the wrong bit with 0 or 1 according to the calculated x, so that the value closest to x is the final output value.

[0128] S500: driving the LED array pixel corresponding to each bad pixel address based on the corrected pixel data.

[0129] The present invention may be a system, method and / or computer program product at any possible level of integrated technical detail. The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon for causing a processor to perform various aspects of the present invention.

[0130] A computer-readable storage medium may be a tangible device that can retain and store instructions used by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a raised structure in a groove on which instructions are recorded, and any suitable combination of the above. A computer-readable storage medium, as used herein, should not be interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0131] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0132] The computer-readable program instructions for performing the operation of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source code or object code written in any combination of one or more programming languages ​​and process programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer as an independent software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network including a local area network (LAN) or a wide area network (WAN), or a connection to an external computer may be made (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuits, thereby performing various aspects of the present invention.

[0133] Various aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present invention. It is understood that each block of the flowchart illustration and / or block diagram, and combinations of blocks in the flowchart illustration and / or block diagram, can be implemented by computer-readable program instructions.

[0134] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing device to produce a machine so that the instructions executed by the processor of the computer or other programmable data processing device create instructions for implementing the flowcharts and / or block diagrams. Figure 1 These computer-readable program instructions may also be stored in a computer-readable storage medium capable of booting a computer, a programmable data processing device and / or other device that operates in a specific manner, so that the computer-readable storage medium having the instructions stored therein includes a manufactured product that includes instructions for implementing aspects of the functions / actions specified in the flowchart and / or block diagram blocks.

[0135] Computer readable program instructions may also be loaded onto a computer, other programmable data processing device, or other device to cause a series of operating steps to be performed on the computer, other programmable device or other device for producing a computer-implemented process, so that the instructions executed on the computer, other programmable device or other device implement the functions / actions specified in the flowchart and / or block diagram blocks.

[0136] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the system, method and computer program product according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment or portion of an instruction, which includes one or more executable instructions for implementing a specified logical function. In some optional implementations, the functions indicated in the block may occur outside the order indicated in the figure. For example, in fact, two blocks shown in succession can be completed as a step, and depending on the functions involved, they can be executed concurrently, substantially concurrently, in a partially or fully time-overlapping manner, or sometimes these blocks can be executed in reverse order. It will also be noted that each block of the block diagram and / or flowchart illustration, as well as the combination of blocks in the block diagram and / or flowchart illustration, can be implemented by a dedicated hardware-based system that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

[0137] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, apparatuses (devices) and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0138] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0139] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

Claims

1. A method for avoiding bad pixels in a frame buffer circuit in a micro display chip, characterized in that: The method comprises: Use I2C or SPI interface to access the frame buffer circuit by setting registers; set registers to put the frame buffer circuit into debug mode and make the frame buffer controlled by registers; Performing write and read operations on each address of the frame buffer circuit to determine the bad pixel address in the frame buffer circuit that cannot correctly perform write and read operations; controlling the write operation or read operation on the frame buffer address by the value in the predetermined first register address; and the values ​​of the predetermined second register address and the third register address represent the address of the frame buffer circuit corresponding to the write operation, the value of the predetermined fourth register address represents the test data value written to the address of the corresponding frame buffer circuit, and the predetermined fifth register address stores the read value read from the address of the corresponding frame buffer circuit; Using four test data values ​​to perform read and write operations on the address of each frame buffer circuit, when the read value is different from the written test data value, it is considered that there is a bad pixel in the frame buffer circuit of this address, and this address is saved as an error address; recording the error bit in the error data fed back by the bad pixel address; determining the row and column position of the pixel point of the LED array corresponding to the bad pixel address; A pixel data compensation operation is performed for each bad pixel address, and the compensation operation process includes: reading pixel data corresponding to a number of pixel points surrounding the pixel point corresponding to the bad pixel address, and calculating the pixel data of the pixel point corresponding to the bad pixel address according to the pixel data corresponding to the number of pixel points surrounding; based on the result of the pixel data compensation operation performed on each bad pixel address, correcting the error bit in the error data fed back by the bad pixel address; The LED array pixel point corresponding to each bad pixel address is driven based on the corrected pixel data.

2. The method for avoiding bad pixels in a frame buffer circuit in a micro display chip according to claim 1, characterized in that: Reading pixel data corresponding to several pixel points around the pixel point corresponding to the bad pixel address includes: reading pixel data D1 of adjacent left pixel points and pixel data D2 of adjacent right pixel points in the same row of pixels of the pixel point corresponding to the bad pixel address; and calculating the average value of the pixel data D1 and the pixel data D2.

3. The method for avoiding bad pixels in a frame buffer circuit in a micro display chip according to claim 1, characterized in that: Reading pixel data corresponding to several pixel points around the pixel point corresponding to the bad pixel address includes: reading pixel data D1 of adjacent upper pixel points and pixel data D2 of adjacent lower pixel points in the same column of pixels of the pixel point corresponding to the bad pixel address; and calculating the average value of the pixel data D1 and the pixel data D2.

4. The method for avoiding bad pixels in a frame buffer circuit in a micro display chip according to claim 1, characterized in that: Reading pixel data corresponding to a plurality of pixels around the pixel corresponding to the bad pixel address includes: reading pixel data D of n pixels adjacent to the left of the pixel corresponding to the bad pixel address in the same row of pixels. 11 , D 12 ,……,D 1n and the pixel data D of the adjacent right pixel 21 , D 22 ,……,D 2n ; and pixel data D 11 , D 12 ,……,D 1n and pixel data D 21 , D 22 ,……,D 2n Perform weighted average operation.

5. The method for avoiding bad pixels in a frame buffer circuit in a micro display chip according to claim 1, characterized in that: Reading pixel data corresponding to a plurality of pixel points around the pixel point corresponding to the bad pixel address includes: reading pixel data D of n adjacent upper pixel points in the same column of pixels of the pixel point corresponding to the bad pixel address. 11 , D 12 ,……,D 1n and the pixel data D of the adjacent lower pixel point 21 , D 22 ,……,D 2n ; and pixel data D 11 , D 12 ,……,D 1n and pixel data D 21 , D 22 ,……,D 2n Perform weighted average operation.

6. The method for avoiding bad pixels in a frame buffer circuit in a micro display chip according to claim 1, characterized in that: Reading pixel data corresponding to several pixel points around the pixel point corresponding to the bad pixel address includes: reading pixel data D1 of adjacent left pixel points and pixel data D2 of adjacent right pixel points in the same row of pixels of the pixel point corresponding to the bad pixel address, and simultaneously reading pixel data D3 of adjacent upper pixel points and pixel data D4 of adjacent lower pixel points in the same column of pixels of the pixel point corresponding to the bad pixel address; and calculating the average value of the pixel data D1, pixel data D2, pixel data D3 and pixel data D4.

7. The method for avoiding bad pixels in a frame buffer circuit in a micro display chip according to claim 1, characterized in that: Reading pixel data corresponding to a plurality of pixels around the pixel corresponding to the bad pixel address includes: reading pixel data D of n pixels adjacent to the left of the pixel corresponding to the bad pixel address in the same row of pixels. 11 , D 12 ,……,D 1n , pixel data D of the adjacent right pixel 21 , D 22 ,……,D 2n and the pixel data D of the n adjacent upper pixels in the same column of pixels 31 , D 32 ,……,D 3n and the pixel data D of the adjacent lower pixel point 41 , D 42 ,……,D 4n ; and pixel data D 11 , D 12 ,……,D 1n ; Pixel data D 21 , D 22 ,……,D 2n ; Pixel data D 31 , D 32 ,……,D 3n ; Pixel data D 41 , D 42 ,……,D 4n Perform weighted average operation.

8. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores computer-readable instructions. When the computer-readable instructions are executed by the processor, the bad pixel avoidance method as described in any one of claims 1 to 7 is executed.

9. A Micro-LED display chip, characterized in that: The driving circuit of the Micro-LED display chip drives the LED light-emitting element for display according to the bad pixel avoidance method as described in any one of claims 1 to 7.

Images