Message self-adaptive gating scheduling method and system based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a message adaptive gating scheduling method and system realized based on an FPGA. The method comprises the following steps: analyzing an input network message and carrying out flow monitoring; determining a gating configuration mode of message transmission according to flow monitoring; performing gating enqueue configuration according to the determined gating configuration mode, and then performing corresponding processing on the message; when self-adaptive gating configuration is carried out, configuration is carried out according to self-adaptive gating parameters, meanwhile, the optimal residence time is matched for a message according to back-stage link monitoring, a self-adaptive gating list is generated, and when the message arrives, the message is processed according to a priority message scheduling instruction, a storage instruction and the optimal residence time. According to the invention, high-precision and low-delay message transmission in a multi-service scene can be realized.

Description

Technical Field

[0001] The present invention relates to the field of message transmission, and in particular to a message adaptive gating scheduling method and system based on FPGA. Background Art

[0002] With the development of technologies such as smart vehicles, artificial intelligence, and mobile Internet, the scale of computer networks has expanded rapidly, and the types and number of network applications are increasing. Traditional industrial Ethernet cannot guarantee low-latency networks, deterministic delay networks, and other issues. Moreover, with the increase in network data traffic, the scheduling of multiple networks has become more complex and difficult, and the determinism of message transmission during network transmission cannot be guaranteed. Although TSN (Time Sensitive Network) technology can provide very high-precision message transmission delay, TSN networks require the support of specialized equipment and chips, and new network protocols need to be deployed. Summary of the invention

[0003] The main purpose of the present invention is to provide a high-precision, low-latency message adaptive gating scheduling method and device based on FPGA, which can realize zero-latency communication and scheduling of messages and improve the end-to-end determinism of messages.

[0004] The technical solution adopted by the present invention is:

[0005] A method for adaptive gating and scheduling of messages based on FPGA is provided, comprising the following steps:

[0006] Parse the input network messages and monitor the traffic;

[0007] Determine the gating configuration mode of message transmission according to traffic monitoring, including the default gating configuration mode and the adaptive gating configuration mode; when the adaptive gating configuration mode is determined, calculate the maximum residence time of the current message according to the rate, length, link delay and message sending time of the parsed network message, generate the corresponding adaptive gating parameters, and generate the priority message scheduling instruction and storage instruction according to the message priority;

[0008] The gated queue configuration is performed according to the determined gating configuration method, and then the message is processed accordingly; when adaptive gating configuration is performed, it is configured according to the adaptive gating parameters, and the optimal gating time is matched for the message according to the subsequent link monitoring, and an adaptive gating list is generated. When the message arrives, it is processed according to the priority message scheduling instructions, storage instructions, and optimal gating time.

[0009] According to the above technical solution, time synchronization is performed when the message is transmitted.

[0010] Following the above technical solution, the configuration parameters under the default gating configuration mode include: TSN type ID, TSN configuration packet length, configuration TSN gating time, configuration TSN gating list time slot, gating list cycle time, TSN gating list, TSN gating enable, gating cycle packet number ID, gating cycle packet number and TSN path delay.

[0011] Following the above technical solution, the messages configured by the default gating configuration method are then scheduled and shaped, specifically: the messages are stored according to the type of message analysis, and are shaped into corresponding output message queues according to the type of each message, and finally the corresponding gated messages are scheduled and output according to the gating instructions of the gated entry queue.

[0012] Following the above technical solution, the gated entry is specifically as follows:

[0013] The gating time is calculated based on the priority of each message and the link delay configuration:

[0014]

[0015] Where P K Indicates the current message flow rate * message length; T PRO T is the time to send the message in advance; delay is the current message link delay; k is the number of messages;

[0016] When the corresponding gating time arrives, the corresponding gating is turned on, and the queue is queried according to the priority level within a time slot to see if there is data to be sent. If there is data and the gating state is turned on, the queue is scheduled to be sent first.

[0017] Following the above technical solution, the gated queue entry also includes the steps of: making a judgment in advance based on the gate time and the current time when the message needs to be sent, and predicting whether the low-priority message can be sent within the protection band time before switching the gate state. If it cannot be completed, stop sending the message and wait for the gate state to switch, so as to prevent the gate state from switching when the message is halfway sent, resulting in fragmented packets.

[0018] Following the above technical solution, the packets configured by the default gating configuration mode are then scheduled and shaped, specifically:

[0019] Identify the current message type within the specified time threshold. For each type of message, first calculate the link delay of each input signal based on the gPTP message synchronization to obtain the message waiting time:

[0020] Tswait=Tsent-Tarrived

[0021] Among them, Tsent represents the message sending time; Tarrived represents the delay time for the message to reach FPGA;

[0022] According to the message length, the internal delay of the logic and the transmission rate of the specified port, the maximum residence time of the current message is obtained:

[0023] Tshold=Tswait-di*fq-Tdelay

[0024] Among them, Tdi*fq is the transmission time of the message; Tdelay is the logic delay of the internal processing of the current message;

[0025] According to the message type and the above calculation results, the message priority type within the time threshold is determined, and the corresponding output message queue is formed according to the priority type of each message. Finally, the corresponding gated message is scheduled to be output according to the gating instruction of the gated entry queue.

[0026] Following the above technical solution, the gated entry is specifically as follows:

[0027] Identify the number of each type of message within the specified time threshold, and match the optimal gating time according to the message packet length, sending rate, and message traffic factors in the current system:

[0028]

[0029] Among them, P K Indicates the current message flow rate * message length; k is the number of messages; T PRO Send message in advance; T delay Current message link delay;

[0030] When the corresponding gating time arrives, the corresponding gating is turned on, and the queue is queried according to the priority level within a time slot to see if there is data to be sent. If there is data and the gating state is turned on, the queue is scheduled to be sent first.

[0031] Following the above technical solution, if multiple messages of the same type appear within a specified time threshold and continuously occupy the gating time of other types, the gating list is updated again after the packet is sent within a time threshold, so as to meet the needs of the adaptive gating list.

[0032] The present invention also provides a message adaptive TSN gating scheduling system based on FPGA, comprising:

[0033] The message parsing module is used to parse the input network message;

[0034] A traffic monitoring module is used to monitor the traffic of input network messages;

[0035] A gating configuration module, used to determine the gating configuration mode of message transmission according to traffic monitoring, including a default gating configuration mode and an adaptive gating configuration mode;

[0036] The adaptive gating scheduling module is used to calculate the maximum residence time of the current message according to the rate, length, link delay and message sending time of the parsed network message when determining the adaptive gating configuration mode, generate corresponding adaptive gating parameters, and generate priority message scheduling instructions and storage instructions according to the message priority; when performing adaptive gating configuration, it is configured according to the adaptive gating parameters, and at the same time, the optimal gating time is matched for the message according to the subsequent link monitoring, and an adaptive gating list is generated. When the message arrives, the message is processed according to the priority message scheduling instruction, storage instruction and optimal gating time.

[0037] The present invention also provides a computer storage medium, which stores a computer program that can be executed by a processor, and the computer program implements the message adaptive gating scheduling method based on FPGA described in the above technical solution.

[0038] The beneficial effects of the present invention are as follows: the present invention utilizes the advantages of FPGA parallel computing to independently and parallelly store different data messages. In the face of complex and diverse message scenarios, it can autonomously schedule the current local traffic message, select an adaptive gating configuration method, and adapt the gating list. The scheme is flexible and configurable, which can ensure that the traffic is sent from scheduling to the network port outlet, the path delay is predictable, and the delay uncertainty at the software level can be compensated and eliminated, achieving zero-delay reliable communication, thereby improving the end-to-end certainty of the message.

[0039] Furthermore, the present invention adopts a pre-check and post-compensation mechanism, that is, before scheduling switching, the length of the sent message and the time required to send the frame message are first obtained, and the sending message time and the scheduling channel switching time are compared to determine whether there is enough time to send a frame of data. If not, time compensation can be performed to ensure high-priority data high-precision control output.

[0040] Furthermore, according to the characteristics of network data frames, the transmission priority is increased, and data of different priorities are independently stored and accurately scheduled in parallel through FPGA to ensure low-latency output of high-priority data streams.

[0041] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1This is a flow chart of a message adaptive gating scheduling method based on FPGA implemented in an embodiment of the present invention;

[0044] Figure 2 This is a flowchart of the adaptive gating scheduling process according to an embodiment of the present invention;

[0045] Figure 3 A schematic diagram of scheduling and shaping in a complex environment according to an embodiment of the present invention;

[0046] Figure 4 A schematic diagram of the deployment of a message adaptive gating scheduling device based on FPGA according to an embodiment of the present invention;

[0047] Figure 5 for Figure 4 Internal block diagram of a switch or terminal. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0049] It should be noted that the illustrations provided in the embodiments of the present invention are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout type may also be more complicated.

[0050] In the present invention, it is also necessary to explain that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0051] The high-precision zero-latency TSN adaptive gating scheduling method implemented based on FPGA in the present invention can realize high-precision and low-latency message transmission in multiple business scenarios, and can realize adaptive gating list determination, especially in key areas such as industrial control, autonomous driving, and smart grids.

[0052] like Figure 1 As shown, the message adaptive gating scheduling method based on FPGA implemented in the embodiment of the present invention includes the following steps:

[0053] S1. Parse the input network messages and monitor the traffic; for example, parse the data messages into normal traffic messages, PTP messages, and TSN gating messages, and parse the messages into corresponding messages for output according to the content in the messages;

[0054] S2. Determine the gating configuration mode of message transmission according to traffic monitoring, including the default gating configuration mode and the adaptive gating configuration mode; when the adaptive gating configuration mode is determined, calculate the maximum residence time of the current message according to the rate, length, link delay and message sending time of the parsed network message, generate the corresponding adaptive gating parameters, and generate the priority message scheduling instruction and storage instruction according to the message priority;

[0055] S3. Perform gating queue configuration according to the determined gating configuration method, and then process the message accordingly; when performing adaptive gating configuration, configure it according to the adaptive gating parameters, and at the same time match the optimal gating reservation time for the message according to the subsequent link monitoring, generate an adaptive gating list, and when the message arrives, process the message according to the priority message scheduling instruction, storage instruction, and optimal gating time.

[0056] Furthermore, if Figure 2 As shown, gPTP and SYNCE messages can also be used to achieve high-precision phase / frequency synchronization of messages, which can not only accurately measure the message link delay, but also use the high-precision characteristics of FPGA to achieve precise control of link delay, with the highest accuracy reaching NS level.

[0057] It can be seen that this embodiment uses the advantages of FPGA parallel computing to independently and parallelly store different data messages. In the face of complex and diverse message scenarios, it can autonomously schedule the current local traffic message, select the adaptive gating configuration method, and generate an adaptive gating list, thereby achieving predictable path delay, compensating for and eliminating delay uncertainty at the software level, achieving zero-delay reliable communication, and thus improving the end-to-end certainty of the message.

[0058] When the use environment is simple and the message does not change much, you can configure TSN gating according to the default configuration input. If the actual on-site environment is single, the entire environment can use this TSN gating configuration to schedule messages. The processing flow of this part is as follows:

[0059] Message monitoring and configuration adaptation: TSN gating is configured according to the input default configuration. If the actual on-site environment is single, the entire environment can use this TSN gating configuration to schedule messages. An adaptive gating configuration parameter format is shown in Table 1 below:

[0060] Table 1 Adaptive gating configuration parameters

[0061]

[0062] Scheduling and shaping: The current message rate and message length are known at the previous message parsing, and the TSN parameters corresponding to this type of message are also known. Therefore, the entire system knows the time of each gating list and the message priority. Therefore, the messages are stored according to the type of message parsing, and are shaped into corresponding message queues that need to be output according to the type of each message. Finally, the corresponding gated messages are scheduled and output according to the gating instructions of the gating queue.

[0063] Gate entry: According to the corresponding configuration parameters and data packets output by the control analysis, the packets are processed accordingly. Since the priority of each packet has been determined and the link delay has been configured, only the gate time (Gate) needs to be calculated:

[0064]

[0065] Where P K Indicates the current message flow rate * message length; k is the number of messages; T PRO T is the time to send the message in advance; delay The link delay of the current message.

[0066] When the corresponding gating time arrives, the corresponding gating is turned on, and the queue is queried according to the priority level within a time slot to see if there is data to be sent. If there is data and the gating state is turned on, the queue is scheduled to be sent first;

[0067] According to the gate time and the time when the message needs to be sent, a judgment is made in advance. Before switching the gate state, within the protection band time, it is predicted whether the low-priority message can be sent. If it cannot be completed, the message is stopped and the gate state is waited for to switch. This prevents the gate state from switching when the message is halfway through being sent, resulting in packet fragmentation.

[0068] If the system environment is complex, we can only know that there will be multiple TSN gating situations in this scenario, and there may also be complex scheduling such as frame preemption. At this time, the message monitoring module is used in the entire system to monitor the traffic of various messages. Therefore, frame preemption, burst messages, and invalid messages can be accurately detected. Adaptability tests can be performed based on the actual traffic used, and the high degree of parallelism inside the FPGA can be used. Therefore, the relevant control processing logic can be synchronously and adaptively configured in the entire system. The processing logic of this solution is as follows:

[0069] Scheduling shaping: Figure 3As shown in the figure, within the specified time threshold (the default value is 1 minute, generally TSN time network sends periodic network data, and the threshold can be configured according to the actual situation), the message type in the current device is identified. For each type of message, the link delay of each input signal is calculated according to the gPTP message synchronization, and then:

[0070] Tswait=Tsent-Tarrived

[0071] Among them, Tswait represents the waiting time of the message; Tsent represents the sending time of the message; Tarrived represents the delay time of the message reaching FPGA;

[0072] According to the message length, the internal delay of the logic and the transmission rate of the specified port, we can know:

[0073] Tshold=Tswait-di*fq-Tdelay

[0074] Wherein, Tshold is the maximum residence time of the current message, di*fq is the transmission time of the message, where di represents the message length, and fq represents the port transmission rate; Tdelay is the logic delay of the internal processing of the current message.

[0075] According to the message priority type of each type of message calculated above within the time threshold, the basic priority storage type is output. The basic priority is calculated based on the messages needed on site. For example, now that the site already knows which messages have high priority, the existing message types and the corresponding priorities of the types can be informed, and the current existing message priorities can be output according to the incoming message matching. If the message type is not informed, the message priority is matched by the input periodic message. For example, synchronous messages have the highest priority, and TSN type messages have the second highest priority. Different TSN messages count the traffic. The higher the traffic, the higher the priority. The remaining messages match the priority according to the traffic.

[0076] Through the above steps, according to the characteristics of network data frames, the transmission priority is increased, and the FPGA independently and parallelly stores and accurately schedules data of different priorities, so that the entire system can be adaptively adjusted, and the message can be autonomously scheduled and gated with zero delay after internal shaping, ensuring low-delay output of high-priority data streams.

[0077] Gated Enqueue: Within the specified time threshold T, the system will automatically identify and count the number of each type of message.

[0078] The time threshold T defaults to 1 minute, which is set for the periodic network data sent by the TSN time network and can be flexibly configured according to the actual needs of specific application scenarios.

[0079] Match the optimal gate time (Gate) based on factors such as packet length, message flow speed, and message flow in the current system:

[0080]

[0081] Where P K Indicates the current message traffic speed * message length; k is the number of messages, T PRO Send message in advance; T delay Current message link delay.

[0082] For example, the time required for type 1 messages within this time threshold is T0; the time required for type 2 messages within this time threshold is T2; the rest are low priority messages; the gating list a output this time is shown in Table 2 below:

[0083] Table 2 Gating list a

[0084] type Gate time Type 0 T0 Type 1 T1 Other types T-T0-T1

[0085] Therefore, the gating list in this scheduling output is: type 0 exclusively occupies window time slot T0, type 1 exclusively occupies window time slot T1, and other non-sensitive flows share T-T0-T1.

[0086] When gating list a reaches the specified threshold (configurable), a notification of updating gating list a is reported, and the entire system performs gating list control according to gating list a in the next gating cycle.

[0087] At this time, the message monitoring is still detecting messages. If there is a sudden occurrence of type 2 messages on site that continue to appear in the T1 time period and need to be transmitted, and type 1 messages can be sent in the T1-T3 time period, the gating list b is re-planned according to type 0 and type 1 according to type 2 messages. When the number of gating list b appears reaches the specified threshold, an update gating list notification will be reported, and the gating list b will be updated again after a time threshold T packet is sent, so as to meet the needs of the adaptive gating list. The new message gating list b is:

[0088] Table 3 Gating list b

[0089] type Gate time Type 0 T0 Type 2 T3 Type 1 T1-T3 Other types T-T0-T1

[0090] Therefore, in the entire system, the present invention can continuously update the gating list and message types to the entire system in real time, ensuring that the entire system is scheduled according to the optimal gating list.

[0091] It can be seen that the above scheduling algorithm has strong adaptability and high flexibility, and can pre-judge the message sending time of the current frame and the subsequent frame in advance, and perform seamless message switching to achieve zero-delay reliable communication. The present invention uses a pre-check and post-compensation scheduling method, that is, to ensure that the traffic is sent from the scheduling to the network port, the path delay is predictable, and the delay uncertainty at the software level can be compensated and eliminated to achieve zero-delay reliable communication, thereby utilizing the high precision of FPGA and the advantages of parallel computing to realize a zero-delay priority scheduling scheme.

[0092] TSNM MCA and ordinary MAC: mainly realize message MAC layer processing and link monitoring, mainly monitor the specified parameters and message traffic in real time, and feedback to the previous module for parameter optimization configuration when the specified indicators are reached.

[0093] In order to implement the above method embodiment, the present invention also provides a message adaptive TSN gating scheduling system based on FPGA, including:

[0094] A message parsing module is used to parse the input network messages;

[0095] A traffic monitoring module is used to monitor the traffic of input network messages;

[0096] A gating configuration module, used to determine the gating configuration mode of message transmission according to traffic monitoring, including a default gating configuration mode and an adaptive gating configuration mode;

[0097] The adaptive gating scheduling module is used to calculate the maximum residence time of the current message according to the rate, length, link delay and message sending time of the parsed network message when determining the adaptive gating configuration mode, generate corresponding adaptive gating parameters, and generate priority message scheduling instructions and storage instructions according to the message priority; when performing adaptive gating configuration, it is configured according to the adaptive gating parameters, and at the same time, the optimal gating time is matched for the message according to the subsequent link monitoring, and an adaptive gating list is generated. When the message arrives, the message is processed according to the priority message scheduling instruction, storage instruction and optimal gating time.

[0098] Each module is mainly used to implement each step of the above method embodiment, which will not be described one by one here.

[0099] Furthermore, if Figure 4 As shown, the above adaptive gating scheduling system can be deployed on terminals and switches, such as deploying multiple TSN switches 1, 2, 3...N between TSN terminal 1 and TSN terminal 2. Figure 5 As shown, each switch or terminal includes a CPU, a control circuit and a TSN adaptive gating scheduling system.

[0100] The present application also provides a computer-readable storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory (e.g., an SD or DX memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a disk, an optical disk, a server, an App application store, etc., on which a computer program is stored, and the program realizes corresponding functions when executed by a processor. The computer-readable storage medium of this embodiment realizes the message adaptive gating scheduling method based on FPGA implemented in the method embodiment when executed by a processor.

[0101] It should be pointed out that, according to the needs of implementation, the various steps / components described in this application can be split into more steps / components, and two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0102] The order of execution of each step in the above embodiment does not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0103] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A message adaptive gating scheduling method based on FPGA, characterized in that: The following steps are involved: Parse the input network messages and monitor the traffic; Determine the gating configuration mode of message transmission according to traffic monitoring, including the default gating configuration mode and the adaptive gating configuration mode; when the adaptive gating configuration mode is determined, calculate the maximum residence time of the current message according to the rate, length, link delay and message sending time of the parsed network message, generate the corresponding adaptive gating parameters, and generate the priority message scheduling instruction and storage instruction according to the message priority; Perform gated queue configuration according to the determined gated configuration mode, and then process the message accordingly; When performing adaptive gating configuration, configure it according to the adaptive gating parameters, and match the optimal gating time for the message according to the subsequent link monitoring, generate an adaptive gating list, and process the message according to the priority message scheduling instruction, storage instruction, and optimal gating time when the message arrives.

2. The message adaptive gating scheduling method based on FPGA according to claim 1 is characterized in that: Time synchronization is performed during message transmission.

3. The message adaptive gating scheduling method based on FPGA according to claim 1 is characterized in that: The configuration parameters under the default gating configuration mode include: TSN type ID, TSN configuration packet length, configuration TSN gating time, configuration TSN gating list time slot, gating list cycle time, TSN gating list, TSN gating enable, gating cycle packet number ID, gating cycle packet number and TSN path delay.

4. The message adaptive gating scheduling method based on FPGA according to claim 1 is characterized in that: The messages configured by the default gating configuration mode are then scheduled and shaped. Specifically, the messages are stored according to the type of message analysis, and are shaped into corresponding output message queues according to the type of each message. Finally, the gating instructions of the gating queue are used to schedule the output of the corresponding gated messages.

5. The message adaptive gating scheduling method based on FPGA according to claim 4 is characterized in that: The gated entry is as follows: The gating time is calculated based on the priority of each message and the link delay configuration: Where P K Indicates the current message flow rate * message length; T PRO To send the message in advance; T delay is the current message link delay; k is the number of messages; When the corresponding gating time arrives, the corresponding gating is turned on, and the queue is queried according to the priority level within a time slot to see if there is data to be sent. If there is data and the gating state is turned on, the queue is scheduled to be sent first.

6. The message adaptive gating scheduling method based on FPGA according to claim 5 is characterized in that: Gated queuing also includes the following steps: making a judgment in advance based on the gating time and the time when the message needs to be sent. Before switching the gate state, predict whether the low-priority message can be sent within the protection band time. If it cannot be completed, stop sending the message and wait for the gate state to switch, so as to prevent the gate state from switching when the message is halfway sent, resulting in fragmented packets.

7. The message adaptive gating scheduling method based on FPGA according to claim 1 is characterized in that: The packets configured by the default gating configuration mode are then scheduled and shaped as follows: The current message type is identified within the specified time threshold. For each type of message, the link delay of each input signal is calculated based on the gPTP message synchronization to obtain the message waiting time: Tswait=Tsent-Tarrived Among them, Tsent represents the message sending time; Tarrived represents the delay time for the message to reach FPGA; According to the message length, the internal delay of the logic and the transmission rate of the specified port, the maximum residence time of the current message is obtained: Tshold=Tswait-di*fq-Tdelay Among them, Tdi*fq is the transmission time of the message; Tdelay is the logic delay of the internal processing of the current message; According to the message type and the above calculation results, the message priority type within the time threshold is determined, and the corresponding output message queue is formed according to the priority type of each message. Finally, the corresponding gated message is scheduled to be output according to the gating instruction of the gated entry queue.

8. The message adaptive gating scheduling method based on FPGA according to claim 7 is characterized in that: The gated entry is as follows: Identify the number of each type of message within the specified time threshold, and match the optimal gating time according to the message packet length, sending rate, and message traffic factors in the current system: Among them, P K Indicates the current message flow rate * message length; k is the number of messages; T PRO Send message in advance; T delay Current message link delay; When the corresponding gating time arrives, the corresponding gating is turned on, and the queue is queried according to the priority level within a time slot to see if there is data to be sent. If there is data and the gating state is turned on, the queue is scheduled to be sent first.

9. The message adaptive gating scheduling method based on FPGA according to claim 8 is characterized in that: If multiple packets of the same type appear within a specified time threshold and continuously occupy the gating time of other types, the gating list is updated again after the packet is sent within a time threshold, so as to meet the requirements of the adaptive gating list.

10. A message adaptive TSN gating scheduling system based on FPGA, characterized in that: include: A message parsing module is used to parse the input network messages; A traffic monitoring module is used to monitor the traffic of input network messages; A gating configuration module, used to determine the gating configuration mode of message transmission according to traffic monitoring, including a default gating configuration mode and an adaptive gating configuration mode; The adaptive gating scheduling module is used to calculate the maximum residence time of the current message according to the rate, length, link delay and message sending time of the parsed network message when determining the adaptive gating configuration mode, generate corresponding adaptive gating parameters, and generate priority message scheduling instructions and storage instructions according to the message priority; when performing adaptive gating configuration, it is configured according to the adaptive gating parameters, and at the same time, the optimal gating time is matched for the message according to the subsequent link monitoring, and an adaptive gating list is generated. When the message arrives, the message is processed according to the priority message scheduling instruction, storage instruction and optimal gating time.

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