Output current limiting circuit and chip

Abstract

The embodiment of the invention provides an output current limiting circuit and a chip, and relates to the technical field of transistor circuits. The output current limiting circuit comprises a first output tube, a second output tube, a first feedback suppression module and a current detection processing module; the current detection processing module is used for detecting the current of the first output tube and generating a signal for controlling the first feedback suppression module. And the first feedback suppression module is used for suppressing the current of the first output tube according to the signal of the current detection processing module so as to prevent the first output tube from excessive power consumption and severe heating.

Description

Technical Field

[0001] The present application relates to the field of transistor circuit technology, and in particular to an output current limiting circuit and a chip. Background Art

[0002] The driving capability of an op amp is one of the key indicators of its design, but the greater the driving capability, the better. When the op amp works under a high power supply voltage, excessive output current will generate greater power consumption, causing the op amp to heat up more seriously. Long-term use in this way may cause damage to the chip.

[0003] In order to protect the chip and keep it in normal working state, the output drive capability can be limited to a certain extent to control its power consumption within an acceptable range. Limiting the output drive capability means limiting the current at the chip output end.

[0004] How to limit the current at the output end of a circuit such as an operational amplifier is a technical problem to be solved by this application. Summary of the invention

[0005] The purpose of the present application is to provide an output current limiting circuit and chip to limit the current at the output end of the circuit.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions.

[0007] In a first aspect, an embodiment of the present application provides an output current limiting circuit, including a first output tube, a second output tube, a first feedback suppression module, and a current detection processing module;

[0008] The first end of the first output tube receives a first signal, and the first end of the second output tube receives a second signal; the first end of the first output tube is a gate or a base, and the first end of the second output tube is a gate or a base;

[0009] The second end of the first output tube is connected to a first potential, and the second end of the second output tube is connected to a second potential;

[0010] The third end of the first output tube and the third end of the second output tube are connected together as an output end;

[0011] The first end of the current detection processing module is connected to the first end of the first output tube to detect the current of the first output tube;

[0012] The second end of the current detection processing module is connected to the first end of the first feedback suppression module to control the opening of the first feedback suppression module; the first end of the first feedback suppression module is a gate or a base;

[0013] The second end of the first feedback suppression module is connected to the first end of the first output tube, and the third end of the first feedback suppression module is connected to the second end of the first output tube;

[0014] When the current of the first output tube reaches a set value, the current detection processing module controls the first feedback suppression module to start, so as to control the voltage between the first end of the first output tube and the second end of the first output tube, thereby suppressing the current of the first output tube.

[0015] In a second aspect, an embodiment of the present application provides a chip, wherein the chip includes the output current limiting circuit of the first aspect.

[0016] Compared with the prior art, this application has the following beneficial effects:

[0017] The output current limiting circuit provided in the embodiment of the present application suppresses the current of the first output tube by controlling the voltage of the first end of the first output tube, thereby preventing the first output tube from consuming too much power and generating severe heat. Any output tube of the output current limiting circuit can be used as the above-mentioned first output tube; or both output tubes can be used as the above-mentioned first output tubes, that is, the currents of the two output tubes of the output current limiting circuit are limited in the manner of the first output tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of an output current limiting circuit provided in an embodiment of the present application;

[0020] Figure 2 A method provided in the embodiment of the present application is to Figure 1 Schematic diagram of output current limiting circuit with two output tubes interchanged;

[0021] Figure 3 A schematic diagram of an output current limiting circuit in which both output tubes are provided with current limiting, provided in an embodiment of the present application;

[0022] Figure 4 A schematic diagram of a current detection processing module composed of a first current mirror unit, a first current-voltage conversion unit and a control signal output unit provided in an embodiment of the present application;

[0023] Figure 5A schematic diagram of a control signal output unit composed of a first transistor, a current source and a third current mirror unit provided in an embodiment of the present application;

[0024] Figure 6 A schematic diagram of a first group of transistors and a second group of transistors provided in an embodiment of the present application, each of which includes two transistors connected in series;

[0025] Figure 7 A schematic diagram of a control signal output unit provided in an embodiment of the present application having a second resistor;

[0026] Figure 8 A schematic diagram of an alternative implementation of a control signal output unit provided in an embodiment of the present application;

[0027] Fig. 9 For the general Figure 7 A schematic diagram of an implementation scheme in which the first feedback suppression module and the control signal output unit circuit are symmetrically connected to the second output tube;

[0028] Fig.10 A schematic diagram of a current detection processing module composed of a first current mirror unit, a first current-voltage conversion unit, a second current mirror unit, a second current-voltage conversion unit and a control signal output unit provided in an embodiment of the present application;

[0029] Fig.11 A schematic diagram of an output current limiting circuit in which two output tubes share a current source is provided in an embodiment of the present application.

[0030] Description of reference numerals:

[0031] The first feedback suppression module 101

[0032] The first current mirror unit 102

[0033] The first current-voltage conversion unit 103

[0034] Control signal output unit 104

[0035] Second current-voltage conversion unit 105

[0036] The second current mirror unit 106 DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. The described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described in the drawings here can be arranged and designed in various different configurations.

[0038] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and features in the embodiments may be combined or replaced with each other, and the single transistor in the figure may be replaced with a composite transistor such as a Darlington transistor.

[0039] In the description of this application, it should be noted that relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.

[0040] like Figure 1 The embodiment of the present application provides an output current limiting circuit, which includes a first output tube, a second output tube, a first feedback suppression module and a current detection processing module. The current detection processing module is used to detect the current of the first output tube and generate a signal to control the first feedback suppression module. The first feedback suppression module is used to suppress the current of the first output tube according to the signal of the current detection processing module. Figure 1 , the output current limiting circuit has the following connection relationship:

[0041] The first end of the first output tube receives the first signal VB1, and the first end of the second output tube receives the second signal VB2; the first end of the first output tube is a gate or a base, and the first end of the second output tube is a gate or a base;

[0042] The second end of the first output tube is connected to the first potential V1, and the second end of the second output tube is connected to the second potential V2;

[0043] The third end of the first output tube and the third end of the second output tube are connected together as an output end (for example, an output end of an operational amplifier);

[0044] The first end of the current detection processing module is connected to the first end of the first output tube to detect the current of the first output tube;

[0045] The second end of the current detection processing module is connected to the first end of the first feedback suppression module to control the start of the first feedback suppression module; the first feedback suppression module can be composed of a triode or a field effect transistor, etc., and the first end of the first feedback suppression module is the gate or base of the transistor therein;

[0046] The second end of the first feedback suppression module is connected to the first end of the first output tube, and the third end of the first feedback suppression module is connected to the second end of the first output tube.

[0047] When the current of the first output tube reaches a set value, the current detection processing module controls the first feedback suppression module to start, so as to control the voltage between the first end of the first output tube and the second end of the first output tube, thereby suppressing the current of the first output tube and preventing the first output tube from consuming too much power and generating severe heat.

[0048] like Figure 2 , the current limiting circuit of the first output tube can be symmetrically set to the second output tube, such as Figure 3 , the two output tubes can set the current limiting circuit at the same time. ( Figure 2 An implementation method of each module will be combined later. Fig. 9 illustrate, Figure 3 An implementation method of each module will be combined later. Fig.10 , Fig.11 illustrate.)

[0049] like Figure 4 The output tube can be a MOSFET, the gate of the first output tube M1 receives the first signal VB1, the gate of the second output tube M2 receives the second signal VB2, and the drain of the first output tube M1 and the drain of the second output tube M2 are connected together as an output end.

[0050] The first feedback suppression module may include a transistor or a compound tube, such as Figure 4 The first feedback suppression module 101 is implemented by the ninth transistor M9.

[0051] like Figure 4 The current detection processing module may include a first current mirror unit, a first current-voltage conversion unit and a control signal output unit.

[0052] The current generated by the first current mirror unit is in a fixed ratio with the current of the first output tube M1, and the current of the first output tube M1 can be accurately detected; the fixed ratio can be N:1, N>1, for example, N≥10, N≥100, which can make the current of the first current mirror unit smaller, save power consumption and reduce heat. In other embodiments, N can also be set to be equal to 1.

[0053] like Figure 4 The first end of the first current mirror unit is connected to the first end of the first output tube M1, the second end of the first current mirror unit is connected to the first potential V1, and the third end of the first current mirror unit is connected to the second potential V2 through the first current-voltage conversion unit.

[0054] The first current-voltage conversion unit converts the current generated by the first current mirror unit into a voltage and provides it to the control signal output unit. The control signal output unit controls the first feedback suppression module according to the voltage across the first current-voltage conversion unit.

[0055] like Figure 5 The first current mirror unit 102 can be implemented by a third transistor M3, and the first current-voltage conversion unit 103 can be implemented by a first resistor R1. The control signal output unit 104 may include a first transistor M4, a current source and a third current mirror unit. The third current mirror unit may include a first group of transistors and a second group of transistors. The second group of transistors is used to track the current of the first group of transistors. Figure 5 In the embodiment shown, the first group of transistors includes a sixth transistor M6, and the second group of transistors includes a fifth transistor M5; Figure 6 , the first group of transistors may include 2 or more transistors connected in series, and the second group of transistors may also include 2 or more transistors connected in series. It should be noted that although "group" is used here, it also includes the case where only a single transistor is used. The control signal output unit has the following connection relationship:

[0056] The first group of transistors is connected in series with the current source and connected between the first potential V1 and the second potential V2;

[0057] The second group of transistors is connected in series with the first transistor M4 and connected between the first potential V1 and the second potential V2;

[0058] The connection point between the second group of transistors and the first transistor M4 is connected to the first end of the first feedback suppression module, and the connection point between the second group of transistors and the first transistor M4 is Figure 5 VCTL in.

[0059] Figure 5 The principle of the illustrated implementation is as follows: when the current of the first output tube M1 is small, the current mirrored by the third transistor M3 is small, and the voltage drop of the first resistor R1 is small, which is insufficient to turn on the first transistor M4. The fifth transistor M5 and the sixth transistor M6 form a current mirror. Since the first transistor M4 is turned off, the fifth transistor M5 is pressed into the linear region, the VCTL output is low, and the ninth transistor M9 cannot be turned on, and has no control effect on the current of the first output tube M1.

[0060] When the current of the first output tube M1 is large, the current mirrored by the third transistor M3 is large, and the voltage drop of the first resistor R1 is large enough to turn on the first transistor M4, the VCTL voltage rises, and the ninth transistor M9 is turned on to suppress the voltage rise of VB1, thereby suppressing the current of the first output tube M1, and achieving the effect of limiting the maximum current of the first output tube M1.

[0061] like Figure 7 , the control signal output unit may also include a second resistor R2, the first end of the first transistor M4 is connected to the second potential V2 through the second resistor R2, and the first resistor R1 is connected between the second potential V2 and the third end of the first current mirror unit; adding the second resistor R2 can suppress the influence of the temperature drift of the first resistor R1 and the change of the process angle on the first transistor M4. The process angle refers to the speed fluctuation range of the device set in advance. The produced device is qualified if the speed is within the range, and is scrapped if it exceeds the range. There are four process angles: fast NFET and fast PFET, slow NFET and slow PFET, fast NFET and slow PFET, and slow NFET and fast PFET.

[0062] Since whether the current limiting is turned on or not mainly depends on the voltage drop on the first resistor R1 and the threshold voltage of the fourth transistor M4, the current size when the current limiting is turned on is not fixed as the process angle and temperature of the resistor change. The addition of the second resistor R2 can suppress this change. When the first resistor R1 and the second resistor R2 increase, under the same mirror current of the third transistor M3, the voltage drop generated on the first resistor R1 increases, and the voltage drop generated on the second resistor R2 also increases. The second resistor R2 provides a certain offset effect for the first transistor M4, resulting in an increase in the threshold voltage of the first transistor M4. The voltage drop of the first resistor R1 and the threshold voltage of the first transistor M4 change in the same direction, thereby reducing the variation range of the current limiting value. When the resistance decreases, this effect also occurs, so that the current size when the current limiting is turned on will not change dramatically with the process angle and temperature, and the sensitivity to the process angle and temperature changes of the resistor is low.

[0063] Figure 8 An alternative embodiment of the control signal output unit is shown, the control signal output unit includes a first transistor M4 and a third resistor R33 (the third resistor R33 replaces Figure 5 The current source and the third current mirror unit in the circuit have the following connection relationship:

[0064] The first current-voltage conversion unit 103 converts the current generated by the first current mirror unit 102 into a voltage and provides it to the gate or base of the first transistor M4;

[0065] The first transistor M4 and the third resistor R33 are connected in series and connected between the first potential V1 and the second potential V2;

[0066] A connection point between the first transistor M4 and the third resistor R33 is connected to a first end of the first feedback suppression module 101 .

[0067] Above Figures 5 to 8 In the implementation manner, the first output tube M1 is an enhancement type N-channel MOSFET, and the first feedback suppression module limits the current of the enhancement type N-channel MOSFET.

[0068] The second output tube M2 is an enhanced P-channel MOSFET. Fig. 9 An implementation method of limiting the current of an enhancement mode P-channel MOSFET by a first feedback suppression module is shown. Fig. 9 similar Figure 5 The first current mirror unit 102 may be implemented by a third transistor M3, the first current-voltage conversion unit 103 may be implemented by a first resistor R1, the control signal output unit 104 may include a first transistor M4, a current source and a third current mirror unit, the third current mirror unit may include a first group of transistors and a second group of transistors, the second group of transistors is used to track the current of the first group of transistors, Fig. 9 In the embodiment shown, the first group of transistors includes the sixth transistor M6, and the second group of transistors includes the fifth transistor M5. The control signal output unit has the following connection relationship:

[0069] The first group of transistors is connected in series with the current source and connected between the first potential V1 and the second potential V2;

[0070] The second group of transistors is connected in series with the first transistor M4 and connected between the first potential V1 and the second potential V2;

[0071] The connection point between the second group of transistors and the first transistor M4 is connected to the first end of the first feedback suppression module, and the connection point between the second group of transistors and the first transistor M4 is Fig. 9 VCTL in.

[0072] like Fig. 9 The control signal output unit may further include a second resistor R2, the first end of the first transistor M4 is connected to the second potential V2 through the second resistor R2, and the first resistor R1 is connected between the second potential V2 and the third end of the first current mirror unit.

[0073] Fig. 9 and Figure 7 The connection relationship is symmetrical, and Fig. 9 The MOSFET in the Figure 7 The enhancement-mode P-channel MOSFET is replaced with an enhancement-mode N-channel MOSFET. Figure 7 The enhancement mode N-channel MOSFET is replaced with an enhancement mode P-channel MOSFET.

[0074] The above is an introduction to the implementation method of limiting the current of only one output tube. The following is an introduction to the implementation method of limiting the current of two output tubes at the same time.

[0075] for Figure 3 The implementation method of the second feedback suppression module and the current detection processing module in the embodiment of the present invention is as follows: Fig.10The current detection processing module includes a first current mirror unit, a first current-voltage conversion unit, a second current mirror unit, a second current-voltage conversion unit and a control signal output unit. The connection relationship is as follows:

[0076] A first end of the first current mirror unit is connected to a first end of the first output tube, a second end of the first current mirror unit is connected to a first potential V1, and a current generated by the first current mirror unit is in a fixed ratio to a current of the first output tube;

[0077] The third terminal of the first current mirror unit is connected to the second potential V2 through the first current-voltage conversion unit; the first current-voltage conversion unit converts the current generated by the first current mirror unit into a voltage and provides it to the control signal output unit;

[0078] The control signal output unit controls the first feedback suppression module according to the voltage across the first current-voltage conversion unit;

[0079] The first end of the second current mirror unit is connected to the first end of the second output tube, the second end of the second current mirror unit is connected to the second potential V2, and the current generated by the current mirror is in a fixed ratio to the current of the second output tube;

[0080] The third terminal of the second current mirror unit is connected to the first potential V1 through the second current-voltage conversion unit; the second current-voltage conversion unit converts the current generated by the second current mirror unit into a voltage and provides it to the control signal output unit;

[0081] The control signal output unit controls the second feedback suppression module according to the voltage across the second current-voltage conversion unit.

[0082] Figure 7 The illustrated embodiment incorporates Fig.10 , we can get an implementation method as Fig.11 :

[0083] The first feedback suppression module is a ninety-first transistor M91, and the second feedback suppression module is a ninety-second transistor M92;

[0084] The control signal output unit comprises a first transistor M4, a second transistor M12, a current source, a third current mirror unit and a fourth current mirror unit;

[0085] The third current mirror unit includes a first group of transistors 1011, a second group of transistors 1010 and a third group of transistors 1007; the second group of transistors 1010 tracks the current of the first group of transistors 1011; the third group of transistors 1007 tracks the current of the first group of transistors 1011; the first group of transistors includes an eleventh transistor M11, the second group of transistors includes a tenth transistor M10, and the third group of transistors 1007 includes a seventh transistor M7;

[0086] The fourth current mirror unit includes a fourth transistor group 1006 and a fifth transistor group 1005, the fifth transistor group 1005 tracks the current of the fourth transistor group 1006; the fourth transistor group 1006 includes a sixth transistor M6, and the fifth transistor group 1005 includes a fifth transistor M5;

[0087] The first current-voltage conversion unit 103 converts the current generated by the first current mirror unit 102 into a voltage and provides it to the gate or base of the first transistor M4;

[0088] The second current-voltage conversion unit 105 converts the current generated by the second current mirror unit 106 into a voltage and provides it to the gate or base of the second transistor M12;

[0089] The first transistor group 1011 is connected in series with the current source and connected between the first potential V1 and the second potential V2;

[0090] The second transistor group 1010 and the second transistor M12 are connected in series and connected between the first potential V1 and the second potential V2; the connection point between the second transistor group 1010 and the second transistor M12 is connected to the first end of the second feedback suppression module;

[0091] The third transistor group 1007 and the fourth transistor group 1006 are connected in series and connected between the first potential V1 and the second potential V2;

[0092] The fifth transistor 1005 and the first transistor M4 are connected in series and connected between the first potential V1 and the second potential V2; the connection point between the fifth transistor 1005 and the first transistor M4 is connected to the first end of the first feedback suppression module.

[0093] Similar to the second resistor R2, a fourth resistor R4 may be provided to be connected between the second transistor M12 and the first potential V1 to suppress the influence of the temperature drift of the second current-voltage conversion unit 105 on the second transistor M12 and achieve a relatively stable current limiting value.

[0094] The second resistor R2 and the fourth resistor R4 can also enable the circuit to generate a relatively stable current limiting value when the process angle changes.

[0095] Based on the above embodiment, the present application also provides a chip, which includes the above output current limiting circuit. The chip may be an operational amplifier chip.

[0096] In general, the present application proposes an output current limiting circuit and chip to prevent the first output tube from consuming too much power and generating too much heat, and also to suppress errors caused by temperature drift and process angle changes.

[0097] The above-described device and system embodiments are merely illustrative, and some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. A person skilled in the art may understand and implement the present embodiment without creative effort.

[0098] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An output current limiting circuit, characterized in that: It includes a first output tube, a second output tube, a first feedback suppression module and a current detection processing module; The first end of the first output tube receives a first signal (VB1), and the first end of the second output tube receives a second signal (VB2); the first end of the first output tube is a gate or a base, and the first end of the second output tube is a gate or a base; The second end of the first output tube is connected to a first potential (V1), and the second end of the second output tube is connected to a second potential (V2); The third end of the first output tube and the third end of the second output tube are connected together as an output end; The first end of the current detection processing module is connected to the first end of the first output tube to detect the current of the first output tube; The second end of the current detection processing module is connected to the first end of the first feedback suppression module to control the opening of the first feedback suppression module; The first feedback suppression module is connected to the first end of the first output tube and the second end of the first output tube; When the current of the first output tube reaches a set value, the current detection processing module controls the first feedback suppression module to start.

2. The output current limiting circuit according to claim 1, characterized in that: The current detection processing module includes a first current mirror unit, a first current-voltage conversion unit and a control signal output unit; The first end of the first current mirror unit is connected to the first end of the first output tube, the second end of the first current mirror unit is connected to the first potential (V1), and the current generated by the first current mirror unit is in a fixed ratio to the current of the first output tube; The third terminal of the first current mirror unit is connected to the second potential (V2) through the first current-voltage conversion unit; the first current-voltage conversion unit converts the current generated by the first current mirror unit into a voltage and provides it to the control signal output unit; The control signal output unit controls the first feedback suppression module according to the voltage across the first current-voltage conversion unit.

3. The output current limiting circuit according to claim 2, characterized in that: The ratio of the current of the first output tube to the current generated by the first current mirror unit is N:1, where N≥1.

4. The output current limiting circuit according to claim 2, characterized in that: The control signal output unit includes a first transistor, a current source and a third current mirror unit; The first current-voltage conversion unit converts the current generated by the first current mirror unit into a voltage and provides the voltage to the gate or base of the first transistor; The third current mirror unit includes a first group of transistors and a second group of transistors, wherein the second group of transistors is used to track the current of the first group of transistors; The first group of transistors is connected in series with the current source and then connected between the first potential (V1) and the second potential (V2); The second group of transistors is connected in series with the first transistor and is connected between the first potential (V1) and the second potential (V2); A connection point between the second group of transistors and the first transistor is connected to a first end of the first feedback suppression module.

5. The output current limiting circuit according to claim 4, characterized in that: The control signal output unit further includes a second resistor; The first current-voltage conversion unit includes a first resistor; the first resistor is connected between the second potential (V2) and the third end of the first current mirror unit; The first end of the first transistor is connected to the second potential (V2) through the second resistor, and the second end of the first transistor is connected to the first potential (V1) through the second group of transistors; The first resistor is used to suppress the influence of the temperature drift and process angle variation of the second resistor on the first transistor.

6. The output current limiting circuit according to claim 2, characterized in that: The control signal output unit includes a first transistor and a third resistor; The first current-voltage conversion unit converts the current generated by the first current mirror unit into a voltage and provides the voltage to the gate or base of the first transistor; The first transistor and the third resistor are connected in series and connected between the first potential (V1) and the second potential (V2); A connection point between the first transistor and the third resistor is connected to a first end of the first feedback suppression module.

7. The output current limiting circuit according to claim 1, characterized in that: The output current limiting circuit also includes a second feedback suppression module; The third end of the current detection processing module is connected to the first end of the second output tube to detect the current of the second output tube; The fourth end of the current detection processing module is connected to the first end of the second feedback suppression module to control the opening of the second feedback suppression module; the first end of the second feedback suppression module is a gate or a base; The second end of the second feedback suppression module is connected to the first end of the second output tube, and the third end of the second feedback suppression module is connected to the second end of the second output tube; When the current of the second output tube reaches a set value, the current detection processing module controls the second feedback suppression module to start, so as to control the voltage between the first end of the second output tube and the second end of the second output tube, thereby suppressing the current of the second output tube.

8. The output current limiting circuit according to claim 7, characterized in that: The current detection processing module includes a first current mirror unit, a first current-voltage conversion unit, a second current mirror unit, a second current-voltage conversion unit and a control signal output unit; The first end of the first current mirror unit is connected to the first end of the first output tube, the second end of the first current mirror unit is connected to the first potential (V1), and the current generated by the first current mirror unit is in a fixed ratio to the current of the first output tube; The third terminal of the first current mirror unit is connected to the second potential (V2) through the first current-voltage conversion unit; the first current-voltage conversion unit converts the current generated by the first current mirror unit into a voltage and provides it to the control signal output unit; The control signal output unit controls the first feedback suppression module according to the voltage across the first current-voltage conversion unit; The first end of the second current mirror unit is connected to the first end of the second output tube, the second end of the second current mirror unit is connected to the second potential (V2), and the current generated by the current mirror is in a fixed ratio to the current of the second output tube; The third terminal of the second current mirror unit is connected to the first potential (V1) through the second current-voltage conversion unit; the second current-voltage conversion unit converts the current generated by the second current mirror unit into a voltage and provides it to the control signal output unit; The control signal output unit controls the second feedback suppression module according to the voltage across the second current-voltage conversion unit.

9. The output current limiting circuit according to claim 8, characterized in that: The control signal output unit includes a first transistor, a second transistor, a current source, a third current mirror unit and a fourth current mirror unit; The first current-voltage conversion unit converts the current generated by the first current mirror unit into a voltage and provides the voltage to the gate or base of the first transistor; The second current-voltage conversion unit converts the current generated by the second current mirror unit into a voltage and provides the voltage to the gate or base of the second transistor; The third current mirror unit includes a first group of transistors, a second group of transistors and a third group of transistors; the second group of transistors tracks the current of the first group of transistors; the third group of transistors tracks the current of the first group of transistors; The fourth current mirror unit includes a fourth group of transistors and a fifth group of transistors, and the fifth group of transistors tracks the current of the fourth group of transistors; The first group of transistors is connected in series with the current source and then connected between the first potential (V1) and the second potential (V2); The second group of transistors is connected in series with the second transistor and is connected between the first potential (V1) and the second potential (V2); A connection point between the second group of transistors and the second transistor is connected to a first end of the second feedback suppression module; The third group of transistors and the fourth group of transistors are connected in series and connected between the first potential (V1) and the second potential (V2); The fifth group of transistors is connected in series with the first transistor and is connected between the first potential (V1) and the second potential (V2); A connection point between the fifth transistor group and the first transistor is connected to a first end of the first feedback suppression module.

10. A chip, characterized in that: The chip comprises the output current limiting circuit according to any one of claims 1 to 9.

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