QSPI serial port switching method and system and storage medium thereof

Abstract

The invention provides a QSPI serial port switching method and system and a storage medium, and the method comprises the steps: responding to a serial port signal sent by a QSPI serial port host, recognizing a target instruction according to the serial port signal, and determining the total data interaction direction of an internal communication interface according to the target instruction; then, first configuration information of the instruction register is read, and a target flash memory is determined in the multiple flash memories according to the first configuration information; then, reading second configuration information of the instruction register, determining a target partition bit in the target flash memory according to the second configuration information, and setting the numerical value of the target partition bit to be one so as to divide the target flash memory into a plurality of target storage partitions; finally, when the number of the target flash memories is multiple, according to the total data interaction direction, the target storage partitions in the multiple target flash memories and the QSPI serial port host are controlled to synchronously conduct data switching in a triple-modular redundancy mode, and then the QSPI serial port host can easily achieve the triple-modular redundancy transmission function in the flash memory data reading process.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a QSPI serial port transfer method, system and storage medium thereof. Background Art

[0002] In the space environment, the data in the memory chip is easily disturbed by cosmic radiation and causes error flipping. Therefore, in spacecraft applications, triple-mode redundancy technology is often required to back up and correct errors in stored data.

[0003] In aerospace application scenarios, the traditional QSPI serial port host controls multiple flash memory chips through multiple chip select signal lines, but does not support triple-mode redundant transmission function in the process of reading multiple flash memory chips. In order to add the triple-mode redundant function, it is necessary to modify the circuit design code inside the QSPI serial port host of different manufacturers, which makes it very cumbersome to implement the triple-mode redundant function of the QSPI serial port host; and, in aerospace application scenarios, the QSPI serial port host often requires two different boot programs, and the two sets of boot programs need to be equipped with two flash memory chips, which greatly increases the data storage cost of the QSPI serial port host. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to propose a QSPI serial port conversion method, system and storage medium thereof, which enables the QSPI serial port host to easily realize the triple-mode redundant transmission function in the process of reading flash memory data through the general direction of data interaction inside the conversion controller, and sets the partition bit of the flash memory storage address to one during the data exchange process, thereby dividing the storage address of the flash memory into two, so that the QSPI serial port host can burn two different boot programs based on the same flash memory, thereby reducing the data storage cost of the QSPI serial port host.

[0005] To achieve the above-mentioned purpose, a first aspect of an embodiment of the present application proposes a QSPI serial port transfer method, which is applied to a serial port transfer system. The serial port transfer system includes a transfer controller, an instruction register, a QSPI serial port host and multiple flash memories. The transfer controller is respectively connected to the instruction register, the QSPI serial port host and the flash memory for communication. The QSPI serial port transfer method includes: The transfer controller responds to the serial port signal sent by the QSPI serial port host, identifies the target instruction according to the serial port signal, and determines the overall direction of data interaction of the internal communication interface according to the target instruction; The transfer controller reads the first configuration information of the instruction register, and determines a target flash memory requiring data interaction among the plurality of flash memories according to the first configuration information; The transfer controller reads the second configuration information of the instruction register, determines the target partition bit of the physical storage address in the target flash memory according to the second configuration information, and sets the value of the target partition bit to one, so as to divide the target flash memory into a plurality of target storage partitions, the target storage partitions being located on both sides of the target partition bit; When there are multiple target flash memories, the transfer controller controls the target storage partitions in the multiple target flash memories to transfer data synchronously with the QSPI serial port host in a triple-mode redundant manner according to the general direction of data interaction.

[0006] Furthermore, in some embodiments, the QSPI serial port transfer method further includes: When the number of target flash memories is one, the transfer controller controls the target storage partition in the target flash memory to transfer data with the QSPI serial port host according to the general direction of data interaction.

[0007] Furthermore, in some embodiments, the transfer controller is provided with a timing counter, which responds to the serial port signal sent by the QSPI serial port host and identifies the target instruction according to the serial port signal, including: In response to the serial port signal sent by the QSPI serial port host, continuously read and detect the clock signal sent by the QSPI serial port host, and set the timing count value of the timing counter to the initial count value; Whenever the clock signal enters the falling edge state, the timing count value is incremented by 1 until the timing count value is equal to the first pre-designed value, the instruction code of the instruction register in the current rotation is locked and identified, the target instruction is obtained, and the timing count value is reset to the initial count value.

[0008] Further, in some embodiments, in response to a serial port signal sent by a QSPI serial port host, identifying a target instruction according to the serial port signal further includes: Whenever the clock signal enters the rising edge state, the data transmitted by the QSPI serial port host is saved in the instruction register.

[0009] Furthermore, in some embodiments, determining the overall direction of data interaction in the serial port data transfer process according to the target instruction includes: According to the target instruction, query and determine multiple time-sharing transfer tasks to be executed in the preset instruction table; Obtaining a first state mapping table, and querying the first state mapping table for the corresponding working state of the switching controller when executing each time-sharing switching task, to obtain a plurality of target working states that are asynchronous to each other; Obtaining a second state mapping table, and querying the second state mapping table for a data interaction sub-direction of the transfer controller in each target working state; The various data interaction sub-directions are combined according to the time-sharing sequence of each time-sharing transfer task to obtain the overall data interaction direction.

[0010] Further, in some embodiments, setting the value of the target partition bit to one includes: When the target working state of the transfer controller is the address state, continuously detecting the timing count value of the timing counter; When the timing count value of the counter is equal to the second pre-designed value, the current moment is determined as the partition moment, and the partition moment is the moment when the bit address of the data sent by the transfer controller to the target flash memory overlaps with the target partition bit; At the partition time, partition data with a value of one is sent to the target flash memory to set the value of the target partition bit to one.

[0011] Furthermore, in some embodiments, the serial port transfer system further includes an error flag register, which is communicatively connected to the transfer controller. In the process of controlling the target storage partitions in the plurality of target flash memories to transfer data with the QSPI serial port host in a triple-mode redundant manner, the serial port transfer method further includes the following steps: When the target working state of the transfer controller is a reading state, respectively reading the flash memory output parameters outputted from the target storage partitions of each target flash memory to the transfer controller; Align the bits of each flash memory output parameter, and compare whether the values ​​of the same bit in each flash memory output parameter are consistent; When the values ​​of the same bit in each flash memory output parameter are inconsistent, the bit with inconsistent values ​​is determined as an error bit, the value of the error bit is corrected, and an error signal is sent to the error flag register, so that the error flag register marks a comparison error flag in the target flash memory corresponding to the error bit according to the error signal.

[0012] Furthermore, in some embodiments, the type of the error signal includes a high level signal type and a low level signal type. After sending the error signal to the error flag register, the serial port transfer method further includes the following steps: Continuously check whether the misplaced value has been corrected; When the value of the error bit has been corrected, it is determined whether the type of the error signal is a high level signal type; When the type of the error signal is a high level signal type, an error clearing signal is sent to the error flag register so that the comparison error flag is cleared.

[0013] To achieve the above object, a second aspect of an embodiment of the present application provides a serial port switching system, comprising: A transfer controller, a command register, a QSPI serial port host, an error flag register and a plurality of flash memories, wherein the transfer controller is respectively connected to the command register, the QSPI serial port host, the flash memory and the error flag register for communication; The transfer controller is configured to, in response to a serial port signal sent by the QSPI serial port host, identify a target instruction according to the serial port signal, and determine the overall direction of data interaction in the data transfer process according to the target instruction; The switching controller is further configured to read first configuration information of the instruction register, and determine a target flash memory requiring data interaction among the plurality of flash memories according to the first configuration information; The transfer controller is further configured to read the second configuration information of the instruction register, and determine the target partition bit of the physical storage address in the target flash memory according to the second configuration information, and set the value of the target partition bit to one to divide the target flash memory into a plurality of target storage partitions, the target storage partitions being located on both sides of the target partition bit; The transfer controller is also configured to, when there are multiple target flash memories, control the target storage partitions in the multiple target flash memories and the QSPI serial port host to transfer data in a triple-mode redundant manner according to the general direction of data interaction.

[0014] To achieve the above-mentioned purpose, the third aspect of the embodiment of the present application proposes a storage medium, which is a computer-readable storage medium. The storage medium stores a computer program, and when the computer program is executed by the processor, the serial port conversion method of the above-mentioned first aspect embodiment is implemented.

[0015] The embodiments of the present application have the following beneficial effects: the present application responds to the serial port signal sent by the QSPI serial port host through the adapter controller, identifies the target instruction according to the serial port signal, and determines the general direction of data interaction of the internal communication interface according to the target instruction; then, the adapter controller reads the first configuration information of the instruction register, and determines the target flash memory that needs data interaction among multiple flash memories according to the first configuration information; then, the adapter controller reads the second configuration information of the instruction register, and determines the target partition bit of the physical storage address in the target flash memory according to the second configuration information, and sets the value of the target partition bit to one, so as to divide the target flash memory into multiple target storage partitions, and the target storage partitions are divided into multiple target storage partitions. The area is located on both sides of the target partition bit; finally, when the number of target flash memories is multiple, the transfer controller controls the target storage partitions in the multiple target flash memories to synchronously transfer data with the QSPI serial port host in a three-mode redundant manner according to the general direction of data interaction, and then based on the general direction of data interaction inside the transfer controller, the QSPI serial port host can easily realize the three-mode redundant transmission function in the process of reading flash memory data, and set the partition bit of the flash memory storage address to one during the data exchange process, so as to divide the storage address of the flash memory into two, so that the QSPI serial port host can burn two different boot programs based on the same flash memory, thereby reducing the data storage cost of the QSPI serial port host. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a flow chart of a QSPI serial port transfer method provided by some embodiments of the present application; Figure 2 is a schematic diagram of the jump of the working state of the switching controller provided in some embodiments of the present application; Figure 3 is a flow chart of a QSPI serial port transfer method provided by other embodiments of the present application; Figure 4 is a flowchart of identifying a target instruction according to a serial port signal provided by some embodiments of the present application; Figure 5 is a flowchart of identifying a target instruction according to a serial port signal provided by other embodiments of the present application; Figure 6 is a flowchart of determining the general direction of data interaction according to a target instruction provided in some embodiments of the present application; Figure 7 is a flow chart of setting the value of a target partition bit to one provided by some embodiments of the present application; Figure 8 , 9 is a flow chart after an error signal is sent to an error flag register provided by some embodiments of the present application; Fig.10It is a flow chart of synchronously transferring data between a target flash memory and a QSPI serial port host in a triple-mode redundant manner provided by some embodiments of the present application; Fig.11 It is a schematic diagram of the hardware structure of an electronic device provided in some embodiments of the present application. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0018] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0019] It should also be noted that in the description of this application, "several" means more than one, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used to distinguish the technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0021] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0022] First, some nouns involved in this application are analyzed: Triple Modular Redundancy (TMR) means that the same data is stored in three memories in advance. When the circuit is working, the controller reads the three memories at the same time. If the data from the three memories are not completely consistent, the same data is selected, commonly known as "three out of two". Among them, the data refers specifically to binary data. A single bit of binary data has only two states, 0 and 1, so the data of the same bit in the three memories will not be completely inconsistent.

[0023] In aerospace application scenarios, the traditional QSPI serial port host controls multiple flash memory chips through multiple chip select signal lines, but does not support triple-mode redundant transmission function in the process of reading multiple flash memory chips. In order to add the triple-mode redundant function, it is necessary to modify the circuit design code inside the QSPI serial port host of different manufacturers, which makes it very cumbersome to implement the triple-mode redundant function of the QSPI serial port host; and, in aerospace application scenarios, the QSPI serial port host often requires two different boot programs, and the two sets of boot programs need to be equipped with two flash memory chips, which greatly increases the data storage cost of the QSPI serial port host.

[0024] Based on this, the present application responds to the serial port signal sent by the QSPI serial port host through the adapter controller, identifies the target instruction according to the serial port signal, and determines the general direction of data interaction of the internal communication interface according to the target instruction; then, the adapter controller reads the first configuration information of the instruction register, and determines the target flash memory that needs data interaction among multiple flash memories according to the first configuration information; then, the adapter controller reads the second configuration information of the instruction register, and determines the target partition bit of the physical storage address in the target flash memory according to the second configuration information, and sets the value of the target partition bit to one to divide the target flash memory into multiple target storage partitions, and the target storage partitions are located in the target partition bit on both sides of the bit; finally, when the number of target flash memories is multiple, the transfer controller controls the target storage partitions in the multiple target flash memories to synchronously transfer data with the QSPI serial port host in a three-mode redundant manner according to the general direction of data interaction, and then based on the general direction of data interaction inside the transfer controller, the QSPI serial port host can easily realize the three-mode redundant transmission function in the process of reading flash memory data, and set the partition bit of the flash memory storage address to one during the data exchange process, so as to divide the storage address of the flash memory into two, so that the QSPI serial port host can burn two different boot programs based on the same flash memory, thereby reducing the data storage cost of the QSPI serial port host.

[0025] The embodiments of the present application provide a QSPI serial port transfer method, system and storage medium thereof, which are specifically described through the following embodiments.

[0026] In the first aspect, a QSPI serial port conversion method in an embodiment of the present application is first described. The QSPI serial port conversion method is applied to a serial port conversion system. The serial port conversion system includes a conversion controller, an instruction register, a QSPI serial port host and multiple flash memories. The conversion controller is respectively communicated with the instruction register, the QSPI serial port host and the flash memories.

[0027] Reference Figure 1 As shown, Figure 1 1 is a flowchart of a QSPI serial port transfer method provided in some embodiments of the present application. The QSPI serial port transfer method may include but is not limited to steps S101 to S105.

[0028] Step S101: the adapter controller responds to the serial port signal sent by the QSPI serial port host, identifies the target instruction according to the serial port signal, and determines the overall direction of data interaction of the internal communication interface according to the target instruction.

[0029] Among them, the serial port signal sent by the QSPI serial port host is the chip select signal qspi_slv_csn, and the QSPI serial port host and the adapter controller exchange data through the slave interface.

[0030] Specifically, the adapter controller responds to the chip select signal qspi_slv_csn sent by the QSPI serial port host. At this time, the slave interface of the adapter controller detects that the current chip select signal is valid at a low level, and the adapter controller jumps from an idle type working state to an instruction type working state. Then, the adapter controller identifies the target instruction according to the serial port signal, and determines the overall direction of data interaction of the internal communication interface according to the target instruction.

[0031] It should be noted that the working states of the transfer controller include: idle state (IDLE), instruction state (INSTR), address state (ADDR), operation code state (MODE), empty cycle state (DUNNY), ​​read state (READ), write state (PRGRM) and unknown state (X), among which the asynchronous jump relationship between each working state is as follows: Figure 2 As shown, Figure 2This is a jump diagram of the working state of the transfer controller provided in some embodiments of the present application. When the transfer controller is in an idle state, it can jump to the instruction state; when the transfer controller is in the instruction state, it can jump to the address state or the unknown state; when the transfer controller is in the unknown state, it can jump to the idle state; when the transfer controller is in the address state, it can jump to the operation code state or the empty cycle state or the reading state or the writing state; when the transfer controller is in the operation code state, it can jump to the empty cycle state or the reading state; when the transfer controller is in the empty cycle state, it can jump to the reading state; when the transfer controller is in the reading state, it can jump to the idle state; when the transfer controller is in the writing state, it can jump to the idle state.

[0032] Step S102: the adapter controller reads first configuration information of the instruction register, and determines a target flash memory requiring data exchange among a plurality of flash memories according to the first configuration information.

[0033] Among them, the multiple flash memories include a first flash memory (Flash0), a second flash memory (Flash1), and a third flash memory (Flash2). The instruction register is preset with first configuration information, and the first configuration information includes a first configuration signal qspi_cs_sel. The bit width of the first configuration signal qspi_cs_sel is 2. When the value of the first configuration signal qspi_cs_sel is 0, it indicates that the adapter controller needs to control the first flash memory to interact with the QSPI serial port host for data; when the value of the first configuration signal qspi_cs_sel is 1, it indicates that the adapter controller needs to control the second flash memory to interact with the QSPI serial port host for data; when the value of the first configuration signal qspi_cs_sel is 2, it indicates that the adapter controller needs to control the third flash memory to interact with the QSPI serial port host for data; when the value of the first configuration signal qspi_cs_sel is 3, it indicates that the adapter controller needs to control the first flash memory, the second flash memory, and the third flash memory to interact with the QSPI serial port host for data.

[0034] In an optional embodiment, the switching controller reads the first configuration information of the instruction register and obtains the value of the corresponding first configuration signal qspi_cs_sel is 3. Then, based on the value of the first configuration signal qspi_cs_sel being 3, the target flash memory requiring data interaction is determined among multiple flash memories, that is, the target flash memory includes the first flash memory (Flash0), the second flash memory (Flash1), and the third flash memory (Flash2).

[0035] In an optional embodiment, the switching controller reads the first configuration information of the instruction register and obtains that the value of the corresponding first configuration signal qspi_cs_sel is 0. Then, based on the value of the first configuration signal qspi_cs_sel being 0, a target flash memory requiring data interaction is determined among multiple flash memories, that is, the target flash memory includes the first flash memory (Flash0).

[0036] Step S103: the switching controller reads the second configuration information of the instruction register, determines the target partition bit of the physical storage address in the target flash memory according to the second configuration information, and sets the value of the target partition bit to one to divide the target flash memory into multiple target storage partitions.

[0037] Among them, the instruction register is also preset with second configuration information, and the first configuration information includes a second configuration signal qspi_half_enable and a third configuration signal qspi_cs_sel. The second configuration signal qspi_half_enable is used to select the bit of the storage address of the target flash memory as the target partition bit, and the third configuration signal qspi_cs_sel is used to divide the storage address of the target flash memory into two, so that the target partition bit of the target flash memory is fixed to 1.

[0038] Specifically, the transfer controller reads the second configuration information of the instruction register, determines the target partition bit of the physical storage address in the target flash memory according to the second configuration signal in the second configuration information, and sets the value of the target partition bit to one according to the third configuration signal in the second configuration information to divide the target flash memory into multiple target storage partitions.

[0039] It should be noted that the target storage partition is located on both sides of the target partition position.

[0040] Step S104: when there are multiple target flash memories, the transfer controller controls the target storage partitions in the multiple target flash memories to transfer data synchronously with the QSPI serial port host in a triple-mode redundant manner according to the general direction of data interaction.

[0041] In an optional embodiment, when the target flash memory includes a first flash memory (Flash0), a second flash memory (Flash1), and a third flash memory (Flash2), that is, when the number of target flash memories is multiple, the transfer controller controls the target storage partitions in the multiple target flash memories and the QSPI serial port host to synchronously transfer data in a triple-mode redundant manner according to the overall direction of data interaction.

[0042] Further, refer to Figure 3 As shown, Figure 3 It is a flowchart of a QSPI serial port transfer method provided in some other embodiments of the present application. The QSPI serial port transfer method may include but is not limited to step S301.

[0043] Step S301: When the number of target flash memories is one, the transfer controller controls the target storage partition in the target flash memory to transfer data with the QSPI serial port host according to the general direction of data interaction.

[0044] In an optional embodiment, when the target flash memory includes a first flash memory (Flash0), that is, the number of target flash memories is one, the transfer controller controls the target storage partition in the target flash memory to transfer data with the QSPI serial port host according to the general direction of data interaction.

[0045] Furthermore, the transfer controller is provided with a timing counter, and a timing count value is provided in the timing counter.

[0046] Reference Figure 4 As shown, Figure 4 This is a flowchart of identifying a target instruction according to a serial port signal provided by some embodiments of the present application. The method of identifying a target instruction according to a serial port signal may include but is not limited to steps S401 to S402.

[0047] Step S401: In response to the serial port signal sent by the QSPI serial port host, continuously read and detect the clock signal sent by the QSPI serial port host, and set the timing count value of the timing counter to the initial count value.

[0048] In a possible implementation, the adapter controller responds to the serial port signal sent by the QSPI serial port host, continuously reads and detects the clock signal qspi_slv_sclk sent by the QSPI serial port host, and sets the timing count value of the timing counter to 0.

[0049] The initial count value may be 0, 1, or 10, and this application does not make any specific limitation.

[0050] Step S402: Whenever the clock signal enters the falling edge state, the timing count value is incremented by 1 until the timing count value is equal to the first pre-designed value, the instruction code of the instruction register in the current rotation is locked and identified, the target instruction is obtained, and the timing count value is reset to the initial count value.

[0051] In one possible implementation, whenever the transfer controller detects that the clock signal qspi_slv_sclk enters a falling edge state, the timing count value is incremented by 1 until the timing count value is equal to the first preset count value of 7, the instruction code of the instruction register in the current rotation is locked and identified, the target instruction is obtained, and the timing count value is reset to 0.

[0052] When it is necessary to explain, the instruction codes for the instruction register rotation are shown in the following table:

[0053] Reference Figure 5 As shown, Figure 5 It is a flowchart of identifying target instructions according to serial port signals provided by other embodiments of the present application. The QSPI serial port conversion method may include but is not limited to step S501.

[0054] Step S501: Whenever the clock signal enters a rising edge state, the data transmitted by the QSPI serial port host is saved in the instruction register.

[0055] Wherein, whenever the transfer controller detects that the clock signal qspi_slv_sclk enters the rising edge state, the data transmitted by the QSPI serial port host (ie, the data on the slave interface) is saved to the instruction register.

[0056] Reference Figure 6 As shown, Figure 6 It is a flowchart of determining the general direction of data interaction according to target instructions provided by some embodiments of the present application. The determination of the general direction of data interaction according to target instructions may include but is not limited to steps S601 to S604.

[0057] Step S601: According to the target instruction, a plurality of time-sharing switching tasks to be executed are searched and determined in a preset instruction table.

[0058] In a possible implementation, for a target instruction of the read ID type, multiple time-sharing transfer tasks to be executed are queried in a preset instruction table as follows: the first time-sharing transfer task is for the transfer controller to receive an 8-bit instruction code from the QSPI serial port host, the second time-sharing transfer task is for the QSPI serial port host to receive 24-bit or 32-bit address data, the third time-sharing transfer task is for receiving an 8-bit operation code from the QSPI serial port host (dual-line I / O mode and four-line I / O mode), the fourth time-sharing transfer task is for receiving 4 empty cycles (four-line mode) from the QSPI serial port host, and the fifth time-sharing transfer task is for the transfer controller to cyclically send the read ID transmitted from the target flash memory to the QSPI serial port host.

[0059] In a possible implementation, for instructions of reading data types, multiple time-sharing transfer tasks to be executed are queried in a preset instruction table as follows: the first time-sharing transfer task is for the transfer controller to receive an 8-bit instruction code from the QSPI serial port host, the second time-sharing transfer task is for the transfer controller to receive 24-bit or 32-bit address data from the QSPI serial port host, the third time-sharing transfer task is for the transfer controller to receive an 8-bit operation code (dual-line I / O mode and four-line I / O mode) from the QSPI serial port host, the fourth time-sharing transfer task is for the transfer controller to receive 8 or 4 or 2 or 0 empty cycles (each instruction is different) from the QSPI serial port host, and the fifth time-sharing transfer task is for the transfer controller to cyclically send the read data transmitted from the target flash memory to the QSPI serial port host.

[0060] In a possible implementation, for instructions of writing data types, multiple time-sharing transfer tasks to be executed are queried in a preset instruction table as follows: the first time-sharing transfer task is that the transfer controller first receives an 8-bit instruction code from the QSPI serial port host, the second time-sharing transfer task is to receive 24-bit or 32-bit address data from the QSPI serial port host, and the third time-sharing transfer task is that the transfer controller continuously receives writing data from the QSPI serial port host.

[0061] Step S602: Obtain a first state mapping table, and search the first state mapping table for the corresponding working states of the switching controller when executing each time-sharing switching task, to obtain a plurality of target working states that are asynchronous with each other.

[0062] In a possible implementation, for instructions of read data types, the working state corresponding to the time-sharing transfer task "the transfer controller receives an 8-bit instruction code from the QSPI serial port host" is queried in the first state mapping table and is the instruction state; the working state corresponding to the time-sharing transfer task "receives 24-bit or 32-bit address data from the QSPI serial port host" is the address state; the working state corresponding to the time-sharing transfer task "receives an 8-bit operation code from the QSPI serial port host" is the operation code state; the working state corresponding to the time-sharing transfer task "receives 8 or 4 or 2 or 0 empty cycles from the QSPI serial port host" is the empty cycle state; the working state corresponding to the time-sharing transfer task "the transfer controller cyclically sends the read data transmitted from the target flash memory to the QSPI serial port host" is the read state.

[0063] In a possible implementation, for instructions of the writing data type, the working state corresponding to the time-sharing transfer task "the transfer controller receives an 8-bit instruction code from the QSPI serial port host" is queried in the first state mapping table as the instruction state; the working state corresponding to the time-sharing transfer task "receives 24-bit or 32-bit address data from the QSPI serial port host" is the address state; the working state corresponding to the time-sharing transfer task "the transfer controller continuously receives writing data from the QSPI serial port host" is the writing state. Step S603: Acquire the second state mapping table, and query the data interaction sub-direction of the switching controller in each target working state in the second state mapping table.

[0064] In a possible implementation, when the target flash memory includes a first flash memory (Flash0) and the target working state is an instruction state, the data interaction sub-directions are as follows: the data of the QSPI serial port host is transmitted to the adapter controller (that is, the slave interface of the adapter controller is in the input state), and the data of the adapter controller is transmitted to the target flash memory (that is, the host interface of the adapter controller is in the output state).

[0065] In a possible implementation, when the target flash memory includes a third flash memory (Flash2) and the target working state is the instruction state, the data interaction sub-directions are as follows: the data of the QSPI serial port host is transmitted to the adapter controller (that is, the slave interface of the adapter controller is in the input state), and the data of the adapter controller is transmitted to the target flash memory (that is, the host interface of the adapter controller is in the output state).

[0066] In a possible implementation, when the target flash memory includes a first flash memory (Flash0), a second flash memory (Flash1), and a third flash memory (Flash2) and the target working state is an instruction state, the data interaction sub-directions are as follows: data from the QSPI serial port host is transmitted to the adapter controller (i.e., the slave interface of the adapter controller is in the input state), and data from the adapter controller is transmitted to the target flash memory (i.e., the host interface of the adapter controller is in the output state).

[0067] In a possible implementation, when the target flash memory includes a second flash memory (Flash1) and the target working state is the instruction state, the data interaction sub-direction is as follows: the data of the adapter controller is transmitted to the QSPI serial port host (that is, the slave interface of the adapter controller is in the output state), and the data of the target flash memory is transmitted to the adapter controller (that is, the host interface of the adapter controller is in the input state).

[0068] In a possible implementation, for the target instruction being a Fast Read Quad I / O instruction, the data interaction sub-directions in the address state and the opcode state are as follows: data from the QSPI serial port host is transmitted to the adapter controller (i.e., the slave interface of the adapter controller is in the input state), and data from the adapter controller is transmitted to the target flash memory (i.e., the host interface of the adapter controller is in the output state); data from the adapter controller is transmitted to the QSPI serial port host (i.e., the slave interface of the adapter controller is in the output state), and data from the target flash memory is transmitted to the adapter controller (i.e., the host interface of the adapter controller is in the input state).

[0069] Step S604: Combine the data interaction sub-directions according to the time-sharing sequence of the time-sharing switching tasks to obtain the overall data interaction direction.

[0070] Specifically, each data interaction sub-direction is combined according to the time-sharing sequence of each time-sharing switching task to obtain the overall data interaction direction.

[0071] Reference Figure 7 As shown, Figure 7 It is a flowchart of setting the value of the target partition bit to one provided by some embodiments of the present application, and setting the value of the target partition bit to one may include but is not limited to steps S701 to S703.

[0072] Step S701: When the target working state of the transfer controller is the address state, the timing count value of the timing counter is continuously detected.

[0073] Specifically, when the target working state of the transfer controller is the address state, the timing count value of the timing counter is continuously detected.

[0074] Step S702: When the timing count value of the counter is equal to the second pre-designed value, the current time is determined as the partition time.

[0075] The partition time is the time when the bit address of the data sent by the transfer controller to the target flash memory overlaps with the target partition bit.

[0076] It should be noted that the second pre-designed value is used to confirm that at the current moment, the bit address of the data sent by the transfer controller to the target flash memory overlaps with the target partition bit.

[0077] Step S703: at the partition time, partition data with a value of one is sent to the target flash memory to set the value of the target partition bit to one.

[0078] Specifically, at the partition time, partition data with a value of one is sent to the target flash memory to set the value of the target partition bit to one.

[0079] Furthermore, the serial port switching system also includes an error flag register, which is communicatively connected to the switching controller.

[0080] Reference Figure 8 As shown, Figure 8 It is a flowchart of synchronously transferring data between a target flash memory and a QSPI serial port host in a triple-mode redundant manner provided by some embodiments of the present application. The method may include but is not limited to steps S801 to S803.

[0081] Step S801: when the target working state of the adapter controller is the reading state, respectively read the flash memory output parameters outputted from the target storage partitions of each target flash memory to the adapter controller.

[0082] In a possible implementation, when the target flash memory includes a first flash memory (Flash0), a second flash memory (Flash1), and a third flash memory (Flash2), and the target working state of the adapter controller is a read state, the flash memory output parameters (i.e., the first flash memory output parameters, the second flash memory output parameters, and the third flash memory output parameters) output to the adapter controller by the target storage partitions of the first flash memory, the second flash memory, and the third flash memory are read respectively.

[0083] Step S802: bit-align each flash memory output parameter, and compare whether the values ​​on the same bit in each flash memory output parameter are consistent.

[0084] In a possible implementation, when the target flash memory includes a first flash memory (Flash0), a second flash memory (Flash1), and a third flash memory (Flash2), the first flash memory output parameter, the second flash memory output parameter, and the third flash memory output parameter are bit-aligned, and the values ​​on the same bit in each flash memory output parameter are compared to see if they are consistent.

[0085] Step S803: When the values ​​on the same bit in each flash memory output parameter are inconsistent, the bit with inconsistent values ​​is determined as an error bit, the value of the error bit is corrected, and an error signal is sent to the error flag register, so that the error flag register marks a comparison error flag in the target flash memory corresponding to the error bit according to the error signal.

[0086] In a possible implementation, when the value of the first bit of the first flash output parameter is 0, and the values ​​of the first bits of the second flash output parameter and the third flash output parameter are both 1, it is confirmed that the value of the first bit of the first flash output parameter is inconsistent with the values ​​of the first bits of the other flash output parameters, and then the first bit of the first flash output parameter is confirmed as an error bit, and the value of the error bit is corrected from 0 to 1 (that is, the value of the first bit of the first flash output parameter is consistent with the values ​​of the first bits of the other flash output parameters), and then an error signal qspi_slv_tmr_err_cs0 is sent to the error flag register, so that the error flag register marks a comparison error flag in the target flash memory (that is, the first flash memory) corresponding to the error bit according to the error signal qspi_slv_tmr_err_cs0 or the error signal qspi_slv_tmr_err_tgl.

[0087] In a possible implementation, when the value of the second bit of the second flash output parameter is 1, and the values ​​of the second bits of the first flash output parameter and the third flash output parameter are both 0, it is confirmed that the value of the second bit of the second flash output parameter is inconsistent with the values ​​of the second bits of other flash output parameters, and then the second bit of the second flash output parameter is confirmed as an error bit, and the value of the error bit is corrected from 1 to 0 (that is, the value of the second bit of the second flash output parameter is consistent with the values ​​of the second bits of other flash output parameters), and then an error signal qspi_slv_tmr_err_cs1 is sent to the error flag register, so that the error flag register marks a comparison error flag in the target flash memory (that is, the second flash memory) corresponding to the error bit according to the error signal qspi_slv_tmr_err_cs1 or the error signal qspi_slv_tmr_err_tgl.

[0088] In a possible implementation, when the value of the third bit of the third flash output parameter is 0, and the values ​​of the third bits of the first flash output parameter and the second flash output parameter are both 1, it is confirmed that the value of the third bit of the third flash output parameter is inconsistent with the values ​​of the third bits of other flash output parameters, and then the third bit of the third flash output parameter is confirmed as an error bit, and the value of the error bit is corrected from 0 to 1 (that is, the value of the third bit of the third flash output parameter is consistent with the values ​​of the third bits of other flash output parameters), and then an error signal qspi_slv_tmr_err_c2 is sent to the error flag register, so that the error flag register marks a comparison error flag in the target flash memory (that is, the third flash memory) corresponding to the error bit according to the error signal qspi_slv_tmr_err_cs2 or the error signal qspi_slv_tmr_err_tgl.

[0089] Among them, the types of error signals include high-level signal types and low-level signal types, and the types of error signals qspi_slv_tmr_err_cs0, qspi_slv_tmr_err_cs1 and qspi_slv_tmr_err_cs2 are all high-level signal types, and the error signal qspi_slv_tmr_err_tgl is a low-level signal type.

[0090] Reference Fig. 9 As shown, Fig. 9 This is a flowchart after an error signal is sent to an error flag register provided by some embodiments of the present application. The method may include but is not limited to steps S901 to S903.

[0091] Step S901: Continue to detect whether the erroneous value has been corrected.

[0092] Step S902: When the value of the error bit has been corrected, determine whether the type of the error signal is a high level signal type.

[0093] Specifically, when the value of the error bit has been corrected, it is determined whether the type of the error signal is a high level signal type.

[0094] Step S903: When the type of the error signal is a high level signal type, an error clearing signal is sent to the error flag register so that the comparison error flag is cleared.

[0095] Specifically, when the type of the error signal is a high level signal type (ie, error signal qspi_slv_tmr_err_cs0 or error signal qspi_slv_tmr_err_cs1 or error signal qspi_slv_tmr_err_cs2), an error clearing signal qspi_slv_tmr_err_clr is sent to the error flag register so that the comparison error flag is cleared.

[0096] It should be noted that the reset value of the error signal qspi_slv_tmr_err_tgl is a low level, and a level flip occurs whenever an error occurs, and when the level flips, the comparison error flag is automatically cleared.

[0097] In a second aspect, the present application also provides a serial port switching system, referring to Fig.10 , Fig.10 The schematic diagram of the structure of the serial port switching system provided in some embodiments of the present application is as follows. The serial port switching system 1000 includes: A transfer controller 1001, an instruction register 1002, a QSPI serial port host 1003, an error flag register 1004, and multiple flash memories 1005. The transfer controller 1001 is respectively connected to the instruction register 1002, the QSPI serial port host 1003, the flash memory 1005, and the error flag register 1004 for communication; The transfer controller 1001 is configured to, in response to the serial port signal sent by the QSPI serial port host 1003, identify the target instruction according to the serial port signal, and determine the overall direction of data interaction in the data transfer process according to the target instruction; The switching controller 1001 is further configured to read the first configuration information of the instruction register 1002, and determine the target flash memory 1005 that needs data exchange among the multiple flash memories 1005 according to the first configuration information; The switching controller 1001 is further configured to read the second configuration information of the instruction register 1002, and determine the target partition bit of the physical storage address in the target flash memory 1005 according to the second configuration information, and set the value of the target partition bit to one, so as to divide the target flash memory 1005 into a plurality of target storage partitions, and the target storage partitions are located on both sides of the target partition bit; The switching controller 1001 is also configured to, when there are multiple target flash memories 1005 , control the target storage partitions in the multiple target flash memories 1005 to switch data with the QSPI serial port host 1003 in a triple-mode redundant manner according to the general direction of data interaction.

[0098] The above-mentioned serial port adapter system 1000 and the above-mentioned QSPI serial port adapter method are based on the same inventive concept. The above-mentioned process describes the serial port adapter system 900 of the embodiment of the present application, in which the adapter controller responds to the serial port signal sent by the QSPI serial port host, identifies the target instruction according to the serial port signal, and determines the overall direction of data interaction of the internal communication interface according to the target instruction; then, the adapter controller reads the first configuration information of the instruction register, and determines the target flash memory that needs data interaction in multiple flash memories according to the first configuration information; then, the adapter controller reads the second configuration information of the instruction register, and determines the target partition bit of the physical storage address in the target flash memory according to the second configuration information, and sets the value of the target partition bit to one to set the target The flash memory is divided into a plurality of target storage partitions, and the target storage partitions are located on both sides of the target partition bit; finally, when the number of target flash memories is multiple, the transfer controller controls the target storage partitions in the plurality of target flash memories to synchronously transfer data with the QSPI serial port host in a three-mode redundant manner according to the general direction of data interaction, and then based on the general direction of data interaction inside the transfer controller, the QSPI serial port host can easily realize the three-mode redundant transmission function in the process of reading the flash memory data, and in the process of data exchange, the partition bit of the flash memory storage address is set to one, so as to divide the storage address of the flash memory into two, so that the QSPI serial port host can burn two different boot programs based on the same flash memory, thereby reducing the data storage cost of the QSPI serial port host.

[0099] The embodiment of the present application also provides an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the above-mentioned QSPI serial port transfer method and / or cache data reading method when executing the computer program. The electronic device can be any smart terminal including a mobile phone, a tablet computer, a car computer, etc.

[0100] See also Fig.11 , Fig.11 : is a schematic diagram of the hardware structure of an electronic device provided in some embodiments of the present application, and the electronic device includes: The processor 1101 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the QSPI serial port transfer method and / or cache data reading method provided in the embodiments of the present application; The memory 1102 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1102 can store an operating system and other applications. When the technical solution provided in the embodiments of this specification is implemented by software or firmware, the relevant program code is stored in the memory 1102, and the processor 1101 calls and executes the QSPI serial port transfer method and / or cache data reading method provided in the embodiments of this application; Input / output interface 1103, used to implement information input and output; The communication interface 1104 is used to realize the communication interaction between the device and other devices. The communication can be realized through a wired manner (such as USB, network cable, etc.) or a wireless manner (such as mobile network, WIFI, Bluetooth, etc.); A bus 1105 that transmits information between various components of the device (e.g., the processor 1101, the memory 1102, the input / output interface 1103, and the communication interface 1104); The processor 1101 , the memory 1102 , the input / output interface 1103 and the communication interface 1104 are connected to each other in communication within the device via the bus 1105 .

[0101] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the QSPI serial port conversion method and / or cache data reading method provided in the embodiment of the present application are provided.

[0102] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0103] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0104] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0105] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0106] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0107] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0108] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0109] In the several embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0110] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0111] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0112] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-accessible storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0113] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A QSPI serial port transfer method, characterized in that: Applied to a serial port transfer system, the serial port transfer system includes a transfer controller, an instruction register, a QSPI serial port host and multiple flash memories, the transfer controller is respectively connected to the instruction register, the QSPI serial port host and the flash memories for communication, and the QSPI serial port transfer method includes: The transfer controller responds to the serial port signal sent by the QSPI serial port host, identifies the target instruction according to the serial port signal, and determines the overall direction of data interaction of the internal communication interface according to the target instruction; The transfer controller reads the first configuration information of the instruction register, and determines a target flash memory requiring data interaction among the plurality of flash memories according to the first configuration information; The transfer controller reads the second configuration information of the instruction register, determines the target partition bit of the physical storage address in the target flash memory according to the second configuration information, and sets the value of the target partition bit to one, so as to divide the target flash memory into a plurality of target storage partitions, the target storage partitions being located on both sides of the target partition bit; When there are multiple target flash memories, the transfer controller controls the target storage partitions in the multiple target flash memories to transfer data synchronously with the QSPI serial port host in a triple-mode redundant manner according to the general direction of data interaction.

2. The QSPI serial port transfer method according to claim 1, wherein: The QSPI serial port transfer method also includes: When the number of the target flash memory is one, the transfer controller transfers data between the target storage partition in the target flash memory and the QSPI serial port host according to the general direction of data interaction.

3. The QSPI serial port transfer method according to claim 1, wherein: The transfer controller is provided with a timing counter, which responds to the serial port signal sent by the QSPI serial port host and identifies the target instruction according to the serial port signal, including: In response to the serial port signal sent by the QSPI serial port host, continuously read and detect the clock signal sent by the QSPI serial port host, and set the timing count value of the timing counter to an initial count value; Whenever the clock signal enters a falling edge state, the timing count value is incremented by 1 until the timing count value is equal to a first pre-designed value, the instruction code of the instruction register in the current rotation is locked and identified, the target instruction is obtained, and the timing count value is reset to the initial count value.

4. The QSPI serial port transfer method according to claim 3, wherein: The method of responding to the serial port signal sent by the QSPI serial port host and identifying the target instruction according to the serial port signal also includes: Whenever the clock signal enters a rising edge state, the data transmitted by the QSPI serial port host is saved in the instruction register.

5. The QSPI serial port transfer method according to claim 3, wherein: Determining the overall direction of data interaction in the serial port data transfer process according to the target instruction includes: According to the target instruction, searching and determining a plurality of time-sharing transfer tasks to be executed in a preset instruction table; Acquire a first state mapping table, and query the first state mapping table for the corresponding working state of the switching controller when executing each of the time-sharing switching tasks, to obtain a plurality of target working states that are asynchronous to each other; Acquire a second state mapping table, and query the second state mapping table for the data interaction sub-direction of the transfer controller in each of the target working states; The data interaction sub-directions are combined according to the time-sharing sequence of the time-sharing switching tasks to obtain the overall data interaction direction.

6. The serial port switching method according to claim 5, characterized in that: The step of setting the value of the target partition bit to one includes: When the target working state of the transfer controller is the address state, continuously detecting the timing count value of the timing counter; When the sequential count value of the counter is equal to the second pre-designed value, the current moment is determined as the partition moment, and the partition moment is the moment when the bit address of the data sent by the transfer controller to the target flash memory overlaps with the target partition bit; At the partition time, partition data with a value of one is sent to the target flash memory to set the value of the target partition bit to one.

7. The serial port switching method according to claim 5, characterized in that: The serial port transfer system further includes an error flag register, which is in communication with the transfer controller. In the process of controlling the target storage partitions in the plurality of target flash memories to transfer data with the QSPI serial port host in a triple-mode redundant manner, the serial port transfer method further includes the following steps: When the target working state of the switching controller is a reading state, respectively reading the flash memory output parameters outputted from the target storage partitions of each target flash memory to the switching controller; Aligning the bits of the flash memory output parameters, and comparing whether the values ​​of the same bit in the flash memory output parameters are consistent; When the values ​​on the same bit in each of the flash memory output parameters are inconsistent, the bit with the inconsistent value is determined as an error bit, the value of the error bit is corrected, and an error signal is sent to the error flag register, so that the error flag register marks a comparison error flag in the target flash memory corresponding to the error bit according to the error signal.

8. The serial port switching method according to claim 7, characterized in that: The types of the error signal include a high level signal type and a low level signal type. After sending the error signal to the error flag register, the serial port switching method further includes the following steps: Continuously detecting whether the erroneous value has been corrected; When the value of the error bit has been corrected, determining whether the type of the error signal is a high level signal type; When the type of the error signal is a high level signal type, an error clearing signal is sent to the error flag register so that the comparison error flag is cleared.

9. A serial port switching system, characterized in that: include: A transfer controller, an instruction register, a QSPI serial port host, an error flag register and a plurality of flash memories, wherein the transfer controller is communicatively connected with the instruction register, the QSPI serial port host, the flash memory and the error flag register respectively; The transfer controller is configured to, in response to a serial port signal sent by the QSPI serial port host, identify a target instruction according to the serial port signal, and determine a general direction of data interaction in a data transfer process according to the target instruction; The switching controller is further configured to read the first configuration information of the instruction register, and determine the target flash memory requiring data interaction among the plurality of flash memories according to the first configuration information; The switching controller is further configured to read second configuration information of the instruction register, and determine a target partition bit of a physical storage address in the target flash memory according to the second configuration information, and set a value of the target partition bit to one, so as to divide the target flash memory into a plurality of target storage partitions, the target storage partitions being located on both sides of the target partition bit; The transfer controller is also configured to, when there are multiple target flash memories, control the target storage partitions in the multiple target flash memories to transfer data with the QSPI serial port host in a triple-mode redundant manner according to the general direction of data interaction.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the serial port switching method according to any one of claims 1 to 8 is implemented.

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