A gate transfer circuit and a display device

Abstract

The present invention provides a gate transfer circuit and a display device. The gate transfer circuit includes multiple stages of gate transfer units. Each stage of the gate transfer unit includes a pre-charge module, a first output module, a second output module, an output pull-down module, a node pull-down module, and a stabilization module. The pre-charge module charges a first node according to a previous-stage transfer signal and a previous-stage gate signal. The first output module outputs a gate signal of the current stage according to the potential of the first node and a first clock signal of the current stage. The second output module outputs a transfer signal of the current stage according to the potential of the first node and a first clock signal of the current stage. The output pull-down module pulls down a first output terminal according to a subsequent-stage gate signal and a first low-level signal. The pull-down module pulls down the first node according to a subsequent-stage gate signal and a second clock signal of the current stage. The stabilization module is used to maintain a low level. The present invention can reduce the falling-edge time of the gate signal and improve the image quality of the product.

Description

Technical Field

[0001] This invention relates to the field of display driving technology, and in particular to a gate transfer circuit and a display device. Background Technology

[0002] Display devices, such as liquid crystal displays (LCDs), have gradually replaced traditional cathode ray tube displays due to their numerous advantages, including being lightweight, energy-efficient, and radiation-free. They are widely used in electronic devices such as high-definition digital televisions, desktop computers, personal digital assistants, laptops, mobile phones, and digital cameras.

[0003] Display devices can be configured with a gate transfer circuit to provide a gate signal to the gate line. Changes in the high and low levels of the gate signal can activate or deactivate the thin-film transistor connected to the gate line, thereby controlling the switching of pixels and achieving image display. However, to avoid image quality abnormalities, it is necessary to reduce the falling edge time of the gate signal to improve signal transmission rate and timing accuracy. This requires replacing the switching element that outputs the gate signal in the gate transfer circuit with a larger-sized switching element, but this also increases the clock load and the power consumption of the display device. Therefore, it is necessary to provide an improved technical solution to overcome the above-mentioned technical problems existing in the prior art. Summary of the Invention

[0004] In view of this, the present invention provides a gate transfer circuit and a display device that can reduce the falling edge time of the gate signal and improve the image quality of the product.

[0005] This invention provides a gate transfer circuit, including multiple gate transfer units. Each gate transfer unit includes a pre-charge module, a first output module, a second output module, an output pull-down module, a node pull-down module, and a stabilization module. The pre-charge module is connected to a first node and charges the first node according to the previous stage transfer signal and the previous stage gate signal. The first output module is connected to the pre-charge module at the first node and outputs the gate signal of the current stage at a first output terminal according to the potential of the first node and the first clock signal of the current stage. The second output module is connected to the pre-charge module at the first node and outputs the gate signal of the current stage at a first output terminal according to the potential of the first node and the first clock signal of the current stage. The clock signal is output at the second output terminal, and the transmission signal of this stage is output at the second output terminal; the output pull-down module is connected to the first output module at the first output terminal, and pulls the first output terminal to a low level according to the gate signal of the subsequent stage and the first low-level signal; the node pull-down module is connected to the pre-charge module at the first node, and pulls the first node to a low level according to the gate signal of the subsequent stage and the second clock signal of this stage; the stabilization module is connected to the first node, the first output terminal and the second output terminal, and the stabilization module is used to maintain the first node, the first output terminal and the second output terminal at a low level when the first node is pulled to a low level.

[0006] Specifically, the pre-charge module includes a first switching element, which includes a first control terminal, a first path terminal, and a second path terminal. The first control terminal of the first switching element receives the pre-stage transmitted signal, the first path terminal of the first switching element receives the pre-stage gate signal, and the second path terminal of the first switching element is connected to the first node.

[0007] Specifically, the first output module includes a second switching element, which includes a second control terminal, a third path terminal, and a fourth path terminal. The second control terminal of the second switching element is connected to the first node, the third path terminal of the second switching element receives the first clock signal of this stage, and the fourth path terminal of the second switching element is connected to the first output terminal.

[0008] Specifically, the second output module includes a third switching element, which includes a third control terminal, a fifth path terminal, and a sixth path terminal. The third control terminal of the third switching element is connected to the first node, the fifth path terminal of the third switching element receives the first clock signal of this stage, and the sixth path terminal of the third switching element is connected to the second output terminal.

[0009] Specifically, the output pull-down module includes a fourth switching element, which includes a fourth control terminal, a seventh path terminal, and an eighth path terminal. The fourth control terminal of the fourth switching element receives the subsequent gate signal, the seventh path terminal of the fourth switching element receives the first output terminal, and the eighth path terminal of the fourth switching element is connected to the first low-level signal.

[0010] Specifically, the node pull-down module includes a fifth switching element, which includes a fifth control terminal, a ninth path terminal, and a tenth path terminal. The fifth control terminal of the fifth switching element receives the gate signal of the subsequent stage, the ninth path terminal of the fifth switching element is connected to the first node, and the tenth path terminal of the fifth switching element receives the second clock signal of this stage.

[0011] Specifically, the stabilization module includes six to nineteenth switching elements. The sixth switching element includes a sixth control terminal, an eleventh path terminal, and a twelfth path terminal. The sixth control terminal of the sixth switching element receives a first control signal. The eleventh path terminal of the sixth switching element is connected to the sixth control terminal, and the twelfth path terminal is connected to a second node. The seventh switching element includes a seventh control terminal, a thirteenth path terminal, and a fourteenth path terminal. The seventh control terminal of the seventh switching element receives the first control signal. The thirteenth path terminal of the seventh switching element receives a second low-level signal, and the fourteenth path terminal is connected to a third node. The eighth switching element includes an eighth control terminal, a fifteenth path terminal, and a sixteenth path terminal. The eighth control terminal of the eighth switching element receives a second control signal. The fifteenth path terminal of the eighth switching element is connected to the third node, and the sixteenth path terminal is connected to the eighth control terminal. The ninth switching element includes a ninth control terminal, a seventeenth path terminal, and an eighteenth path terminal. The ninth control terminal of the ninth switching element receives the second control signal, the seventeenth path terminal of the ninth switching element is connected to the second node, and the eighteenth path terminal of the ninth switching element receives the second low-level signal. The tenth switching element includes a tenth control terminal, a nineteenth path terminal, and a twentieth path terminal. The tenth control terminal of the tenth switching element is connected to the first node, the nineteenth path terminal of the tenth switching element receives the second low-level signal, and the twentieth path terminal of the tenth switching element is connected to the second node. The eleventh switching element includes an eleventh control terminal, a twenty-first path terminal, and a twenty-second path terminal. The eleventh control terminal of the eleventh switching element is connected to the first node, the twenty-first path terminal of the eleventh switching element receives the second low-level signal, and the twenty-second path terminal of the eleventh switching element is connected to the third node. The twelfth switching element includes a twelfth control terminal, a twenty-third path terminal, and a twenty-fourth path terminal. The twelfth control terminal of the twelfth switching element is connected to the second node, the twenty-third path terminal of the twelfth switching element is connected to the first node, and the twenty-fourth path terminal of the twelfth switching element receives the second low-level signal. The thirteenth switching element includes a thirteenth control terminal, a twenty-fifth path terminal, and a twenty-sixth path terminal. The thirteenth control terminal of the thirteenth switching element is connected to the third node, the twenty-fifth path terminal of the thirteenth switching element receives the second low-level signal, and the twenty-sixth path terminal of the thirteenth switching element is connected to the first node.The fourteenth switching element includes a fourteenth control terminal, a twenty-seventh path terminal, and a twenty-eighth path terminal. The fourteenth control terminal of the fourteenth switching element is connected to the second node, the twenty-seventh path terminal of the fourteenth switching element is connected to the first output terminal, and the twenty-eighth path terminal of the fourteenth switching element receives a first low-level signal. The fifteenth switching element includes a fifteenth control terminal, a twenty-ninth path terminal, and a thirtieth path terminal. The fifteenth control terminal of the fifteenth switching element is connected to the third node, the twenty-ninth path terminal of the fifteenth switching element is connected to the twenty-eighth path terminal of the fourteenth switching element and receives the first low-level signal, and the thirtieth path terminal of the fifteenth switching element is connected to the first output terminal. The sixteenth switching element includes a sixteenth control terminal, a thirty-first path terminal, and a thirty-second path terminal. The sixteenth control terminal of the sixteenth switching element is connected to the second node, the thirty-first path terminal of the sixteenth switching element is connected to the second output terminal, and the thirty-second path terminal of the sixteenth switching element receives the first low-level signal. The seventeenth switching element includes a seventeenth control terminal, a thirty-third path terminal, and a thirty-fourth path terminal. The seventeenth control terminal of the seventeenth switching element is connected to the third node. The thirty-third path terminal of the seventeenth switching element is connected to the thirty-second path terminal of the sixteenth switching element to receive the first low-level signal. The thirty-fourth path terminal of the seventeenth switching element is connected to the second output terminal.

[0012] Specifically, the first control signal and the second control signal have opposite polarities, and their polarities are reversed once per frame.

[0013] Specifically, the output pull-down module is located at the tail end of the gate line and is connected to the first output terminal through the gate line.

[0014] This invention also provides a display device including the gate transfer circuit described above.

[0015] The gate transfer circuit and display device provided by this invention include a multi-stage gate transfer unit. Each stage of the gate transfer unit includes a pre-charge module, a first output module, a second output module, an output pull-down module, a node pull-down module, and a stabilization module. The output pull-down module is connected to the first output module at a first output terminal and pulls the first output terminal down to a low level based on the subsequent gate signal and a first low-level signal. Therefore, the gate transfer circuit can sequentially output multiple gate signals, exhibiting strong output capability and stability. Furthermore, it can reduce the falling edge time of the gate signal without increasing the clock load, thus improving product image quality. Simultaneously, the gate transfer circuit uses fewer unit components, effectively saving layout area and facilitating narrow bezel design in the display device.

[0016] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] Figure 1 This is a circuit connection diagram of a gate transfer unit in a gate transfer circuit according to an embodiment of the present invention.

[0018] Figures 2 to 5 yes Figure 1 Timing diagram of the gate transfer unit in four stages.

[0019] Figure 6 This is a cascaded circuit diagram of a gate transfer circuit according to an embodiment of the present invention.

[0020] Figure 7 This is a full-stage circuit diagram of a gate transfer circuit according to an embodiment of the present invention.

[0021] Figure 8 and Figure 9 They are Figure 7 A clock signal diagram and a gate signal diagram in one embodiment.

[0022] Figure 10 yes Figure 1 A schematic diagram comparing the gate signals of a structure with a 17T1C gate transfer unit and a structure with a 16T1C gate transfer unit.

[0023] Figure 11 This is a schematic diagram of the gate transfer circuit according to another embodiment of the present invention.

[0024] Figure 12 yes Figure 11 The circuit connection diagram of a gate transfer unit.

[0025] Figure 13 and Figure 14 They are Figure 11 A clock signal diagram and a gate signal diagram in one embodiment. Detailed Implementation

[0026] To further illustrate the technical means and effects of the present invention in order to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, provides a detailed explanation of the specific implementation methods, steps, structures, features, and effects of the gate transfer circuit and display device proposed according to the present invention.

[0027] Figure 1 This is a circuit connection diagram of a gate transfer unit in a gate transfer circuit according to an embodiment of the present invention. Please refer to [link / reference]. Figure 1The gate transfer circuit of this embodiment includes a multi-stage gate transfer unit. Each stage of the gate transfer unit includes: a pre-charge module 10, a first output module 20, a second output module 30, an output pull-down module 40, a node pull-down module 50, and a stabilization module 60.

[0028] In embodiments of the present invention, the gate transfer units can be connected sequentially and continuously or sequentially and spaced apart. Figure 1 In an example, gate transfer units are connected sequentially at intervals. For instance, the nth-stage gate transfer unit is connected to the (n-2)th-stage gate transfer unit and the (n+2)th-stage gate transfer unit. The gate signal and transfer signal output by the nth-stage gate transfer unit can be represented by Gn and Zn, respectively. The gate signal and transfer signal received by the nth-stage gate transfer unit from the previous stage can be represented by Gn-2 and Zn-2, respectively. The gate transfer signal received by the nth-stage gate transfer unit from the next stage can be represented by Gn+2.

[0029] The pre-charge module 10 is connected to the first node Qn and charges the first node Qn according to the front-stage transmission signal Zn-2 and the front-stage gate signal Gn-2.

[0030] The first output module 20 is connected to the precharge module 10 at the first node Qn. Based on the potential of the first node Qn and the first clock signal CLK2 of this stage, the first output module outputs the gate signal Gn of this stage to the connected gate line.

[0031] The second output module 30 is connected to the precharge module 10 at the first node Qn. Based on the potential of the first node Qn and the first clock signal CLK2 of this stage, it outputs the transmission signal Zn of this stage at the second output terminal.

[0032] The output pull-down module 40 is connected to the first output module 20 at the first output terminal, and pulls the first output terminal down to the low level according to the subsequent gate signal Gn+2 and the first low-level signal VGL.

[0033] The node pull-down module 50 is connected to the pre-charge module 10 at the first node Qn. Based on the subsequent gate signal Gn+2 and the second clock signal CLK3 of this stage, the first node Qn is pulled down to a low level.

[0034] The stabilization module 60 is connected to the first node Qn, the first output terminal, and the second output terminal. The stabilization module 60 is used to keep the first node Qn, the first output terminal, and the second output terminal at a low level when the first node Qn is pulled down to a low level.

[0035] It is worth noting that if the nth-stage gate transfer unit at the beginning of the circuit is not connected to a preceding gate transfer unit, then an external signal circuit needs to provide the preceding gate signal Gn-2 and the preceding transfer signal Zn-2. The preceding gate signal Gn-2 and the preceding transfer signal Zn-2 can be provided directly by the timing control circuit or via the source drive circuit to provide the corresponding enable signal STV1. If the nth-stage gate transfer unit at the end of the circuit is not connected to a following gate transfer unit, then an external signal circuit needs to provide the following gate signal Gn+2. This following gate signal Gn+2 can be provided directly by the timing control circuit or via the source drive circuit to provide the corresponding pull-down signal STV2.

[0036] In one embodiment of the present invention, the pre-charge module 10 may include a first switching element M1. The first switching element M1 includes a first control terminal, a first path terminal and a second path terminal. The first control terminal of the first switching element M1 receives the pre-stage transmission signal Zn-2, the first path terminal of the first switching element M1 receives the pre-stage gate signal Gn-2, and the second path terminal of the first switching element M1 is connected to the first node Qn.

[0037] In one embodiment of the present invention, the first output module 20 may include a second switching element M2, the second switching element M2 including a second control terminal, a third path terminal and a fourth path terminal, the second control terminal of the second switching element M2 is connected to the first node Qn, the third path terminal of the second switching element M2 receives the first clock signal CLK2 of this stage, and the fourth path terminal of the second switching element M2 is connected to the first output terminal.

[0038] In one embodiment of the present invention, the second output module 30 may include a third switching element M3, the third switching element M3 including a third control terminal, a fifth path terminal and a sixth path terminal, the third control terminal of the third switching element M3 is connected to the first node Qn, the fifth path terminal of the third switching element M3 receives the first clock signal CLK2 of this stage, and the sixth path terminal of the third switching element M3 is connected to the second output terminal.

[0039] In one embodiment of the present invention, the output pull-down module 40 may include a fourth switching element M4, which includes a fourth control terminal, a seventh path terminal and an eighth path terminal. The fourth control terminal of the fourth switching element M4 receives the subsequent gate signal Gn+2, the seventh path terminal of the fourth switching element M4 is connected to the first output terminal, and the eighth path terminal of the fourth switching element M4 is connected to the first low-level signal VGL.

[0040] In one embodiment of the present invention, the node pull-down module 50 may include a fifth switching element M5, the fifth switching element M5 includes a fifth control terminal, a ninth path terminal and a tenth path terminal, the fifth control terminal of the fifth switching element M5 receives the subsequent gate signal Gn+2, the ninth path terminal of the fifth switching element M5 is connected to the first node Qn, and the tenth path terminal of the fifth switching element M5 receives the second clock signal CLK3 of this stage.

[0041] In one embodiment of the present invention, the stabilization module 60 may include: a sixth switching element M6, a seventh switching element M7, an eighth switching element M8, a ninth switching element M9, a tenth switching element M10, an eleventh switching element M11, a twelfth switching element M12, a thirteenth switching element M13, a fourteenth switching element M14, a fifteenth switching element M15, a sixteenth switching element M16, and a seventeenth switching element M17.

[0042] The sixth switching element M6 includes a sixth control terminal, an eleventh path terminal, and a twelfth path terminal. The sixth control terminal of the sixth switching element M6 receives a first control signal V1. The eleventh path terminal of the sixth switching element M6 is connected to the sixth control terminal of the sixth switching element M6, and the twelfth path terminal of the sixth switching element M6 is connected to the second node QB1. The seventh switching element M7 includes a seventh control terminal, a thirteenth path terminal, and a fourteenth path terminal. The seventh control terminal of the seventh switching element M7 is connected to the eleventh path terminal of the sixth switching element M6 and receives the first control signal V1. The thirteenth path terminal of the seventh switching element M7 receives a second low-level signal VSQ, and the fourteenth path terminal of the seventh switching element M7 is connected to the third node QB2. The eighth switching element M8 includes an eighth control terminal, a fifteenth path terminal, and a sixteenth path terminal. The eighth control terminal of the eighth switching element M8 receives a second control signal V2. The fifteenth path terminal of the eighth switching element M8 is connected to the third node QB2, and the sixteenth path terminal of the eighth switching element M8 is connected to the eighth control terminal of the eighth switching element M8. The ninth switching element M9 includes a ninth control terminal, a seventeenth path terminal, and an eighteenth path terminal. The ninth control terminal of the ninth switching element M9 is connected to the sixteenth path terminal of the eighth switching element M8 and receives the second control signal V2. The seventeenth path terminal of the ninth switching element M9 is connected to the second node QB1, and the eighteenth path terminal of the ninth switching element M9 receives the second low-level signal VSQ. The tenth switching element M10 includes a tenth control terminal, a nineteenth path terminal, and a twentieth path terminal. The tenth control terminal of the tenth switching element M10 is connected to the first node Qn. The nineteenth path terminal of the tenth switching element M10 receives the second low-level signal VSQ, and the twentieth path terminal of the tenth switching element M10 is connected to the second node QB1. The eleventh switching element M11 includes an eleventh control terminal, a twenty-first path terminal, and a twenty-second path terminal. The eleventh control terminal of the eleventh switching element M11 is connected to the first node Qn. The twenty-first path terminal of the eleventh switching element M11 is connected to the nineteenth path terminal of the tenth switching element M10 and receives the second low-level signal VSQ. The twenty-second path terminal of the eleventh switching element M11 is connected to the third node QB2.

[0043] The twelfth switching element M12 includes a twelfth control terminal, a twenty-third path terminal, and a twenty-fourth path terminal. The twelfth control terminal of the twelfth switching element M12 is connected to the second node QB1, the twenty-third path terminal of the twelfth switching element M12 is connected to the first node Qn, and the twenty-fourth path terminal of the twelfth switching element M12 receives the second low-level signal VSQ. The thirteenth switching element M13 includes a thirteenth control terminal, a twenty-fifth path terminal, and a twenty-sixth path terminal. The thirteenth control terminal of the thirteenth switching element M13 is connected to the third node QB2, the twenty-fifth path terminal of the thirteenth switching element M13 is connected to the twenty-fourth path terminal of the twelfth switching element M12 and receives the second low-level signal VSQ, and the twenty-sixth path terminal of the thirteenth switching element M13 is connected to the first node Qn. The fourteenth switching element M14 includes a fourteenth control terminal, a twenty-seventh path terminal, and a twenty-eighth path terminal. The fourteenth control terminal of the fourteenth switching element M14 is connected to the second node QB1, the twenty-seventh path terminal of the fourteenth switching element M14 is connected to the first output terminal, and the twenty-eighth path terminal of the fourteenth switching element M14 receives the first low-level signal VGL. The fifteenth switching element M15 includes a fifteenth control terminal, a twenty-ninth path terminal, and a thirtieth path terminal. The fifteenth control terminal of the fifteenth switching element M15 is connected to the third node QB2. The twenty-ninth path terminal of the fifteenth switching element M15 is connected to the twenty-eighth path terminal of the fourteenth switching element M14 and receives the first low-level signal VGL. The thirtieth path terminal of the fifteenth switching element M15 is connected to the first output terminal. The sixteenth switching element M16 includes a sixteenth control terminal, a thirty-first path terminal, and a thirty-second path terminal. The sixteenth control terminal of the sixteenth switching element M16 is connected to the second node QB1. The thirty-first path terminal of the sixteenth switching element M16 is connected to the second output terminal. The thirty-second path terminal of the sixteenth switching element M16 receives the first low-level signal VGL. The seventeenth switching element M17 includes a seventeenth control terminal, a thirty-third path terminal, and a thirty-fourth path terminal. The seventeenth control terminal of the seventeenth switching element M17 is connected to the third node QB2. The thirty-third path terminal of the seventeenth switching element M17 is connected to the thirty-second path terminal of the sixteenth switching element M16 and receives the first low-level signal VGL. The thirty-fourth path terminal of the seventeenth switching element M17 is connected to the second output terminal.

[0044] In one embodiment of the present invention, the first control signal V1 and the second control signal V2 are low-frequency clock signals (i.e., their frequencies are lower than the frequency of a clock signal), and the first control signal V1 and the second control signal V2 alternately reach a high level, so that when the first control signal V1 is high, the second control signal V2 is low; and when the second control signal V2 is high, the first control signal V1 is low. In one embodiment of the present invention, the first control signal V1 and the second control signal V2 have opposite polarities, and their polarities are reversed once per frame. During the stable phase, the first control signal V1 controls the sixth switch element M6 and the seventh switch element M7 to be in a conducting state. The conducting sixth switch element M6 charges the second node QB1, and the conducting seventh switch element M7 discharges the third node QB2 to the second low-level signal VSQ. Alternatively, the second control signal V2 controls the eighth switch element M8 and the ninth switch element M9 to be in a conducting state. The conducting eighth switch element M8 charges the third node QB2, and the conducting ninth switch element M9 discharges the second node QB1 to the second low-level signal VSQ. Thus, the first control signal V1 and the second control signal V2 alternately control the second node QB1 and the third node QB2 to be at high and low levels, causing the twelfth switch element M12, the fourteenth switch element M14, and the sixteenth switch element M16 connected to the second node QB1, and the thirteenth switch element M13, the fifteenth switch element M15, and the seventeenth switch element M17 connected to the third node QB2 to alternately conduct. Thus, the first node Qn alternately receives the second low-level signal VSQ through the connected twelfth and thirteenth switching elements M12 and M13, the first output terminal alternately receives the first low-level signal VGL through the connected fourteenth and fifteenth switching elements M15, and the second output terminal alternately receives the first low-level signal VGL through the connected sixteenth and seventeenth switching elements M17, thereby achieving a stable low-level effect.

[0045] In one embodiment of the present invention, the gate transfer unit further includes a first capacitor C1, the first end of the first capacitor C1 being connected to the first node Qn, and the second end of the first capacitor C1 being connected to the first output terminal.

[0046] In one embodiment of the present invention, the first capacitor C1 may be, but is not limited to, an external capacitor between the first node Qn and the first output terminal. By utilizing the coupling effect of the capacitor, the voltage pull-up effect of the first node Qn can be improved.

[0047] In one embodiment of the present invention, the duty cycle of the first clock signal CLK2 and the second clock signal CLK3 of the current stage may be, but is not limited to, 50%, and the phase difference between the first clock signal CLK2 and the second clock signal CLK3 of the current stage may be, but is not limited to, a quarter of a cycle.

[0048] In one embodiment of the present invention, the first switching element M1 to the seventeenth switching element M17 may be, but is not limited to, an N-type TFT, an NMOS transistor, or an N-type triode. The corresponding first control terminal to the seventeenth control terminal of the first switching element M1 to the seventeenth switching element M17 are all gates. The corresponding pass terminals of the first switching element M1 to the seventeenth switching element M17 are drains or sources.

[0049] Figures 2 to 5 yes Figure 1 Timing diagrams of the gate transfer cell in four stages. The following will combine... Figures 1 to 5 This section explains the operation of the gate transfer unit in this embodiment. The operation of the gate transfer unit includes four stages: pre-charge stage, output stage, pull-down stage, and stabilization stage.

[0050] Pre-charging phase:

[0051] Please refer to Figure 2 At the box, the front-stage transmission signal Zn-2 and the front-stage gate signal Gn-2 switch from low level to high level. The pre-charge module 10 controls the first node Qn to receive the high-level front-stage gate signal Gn-2, and the first node Qn starts charging.

[0052] In one embodiment, the front-stage transmission signal Zn-2 and the front-stage gate signal Gn-2 switch from low level to high level. The first control terminal of the first switching element M1 receives the high-level front-stage transmission signal Zn-2 and becomes on. The first node Qn receives the high-level front-stage gate signal Gn-2 through the on-state first switching element M1, and the first node Qn is charged.

[0053] In one embodiment, when the first node Qn is charged and pulled up to a high level, the second control terminal of the second switching element M2 and the third control terminal of the third switching element M3 connected to the first node Qn become high level, and the second switching element M2 and the third switching element M3 become conducting, and the first output module 20 and the second output module 30 enter the working state.

[0054] In one embodiment, when the first node Qn is charged and pulled up to a high level, the tenth control terminal of the tenth switching element M10 and the eleventh control terminal of the eleventh switching element M11 connected to the first node Qn become high level. Then, the tenth switching element M10 and the eleventh switching element M11 become on. As a result, the second node QB1, which is connected to the twentieth path terminal of the tenth switching element M10, receives the second low-level signal VSQ on the nineteenth path terminal of the tenth switching element M10 through the on-state tenth switching element M10. At the same time, the third node QB2, which is connected to the twenty-second path terminal of the eleventh switching element M11, receives the second low-level signal VSQ on the twenty-first path terminal of the eleventh switching element M11 through the on-state eleventh switching element M11. When both the second node QB1 and the third node QB2 are at a low level, the corresponding control terminals of the twelfth switching element M12 to the seventeenth switching element M17 are at a low level. Therefore, the twelfth switching element M12 to the seventeenth switching element M17 are in an open state, the stabilization module 60 enters a non-working state, and stops discharging the first node Qn, the first output terminal, and the second output terminal.

[0055] Output phase:

[0056] Please refer to Figure 3 In the box, the first node Qn has been pulled high, and the first clock signal CLK2 of this stage transitions from low to high. Based on the high level of the first node Qn and the high level of the first clock signal CLK2, the first output module 20 outputs a high-level gate signal Gn at its first output terminal. Simultaneously, the second output module 30 outputs a high-level transmission signal Zn at its second output terminal based on the high level of the first node Qn and the high level of the first clock signal CLK2. Afterwards, the subsequent gate signal Gn+2 transitions from low to high. The output pull-down module 40, based on the high-level subsequent gate signal Gn+2 and the first low-level signal VGL, quickly pulls the first output terminal down to a low level. This effectively reduces the falling edge time of the gate signal without increasing the clock load, thus improving product image quality.

[0057] In one embodiment, the first node Qn has been pulled up to a high level, so the second switching element M2 is in a conducting state; the first clock signal CLK2 of this stage transitions from a low level to a high level; the first output terminal receives the high-level first clock signal CLK2 of this stage through the conducting second switching element M2, thereby outputting a high-level gate signal Gn of this stage. In another embodiment, the first node Qn is further pulled up by the first capacitor C1, causing the level of the first node Qn to rise further and fully turn on the second switching element M2.

[0058] In one embodiment, the first node Qn has been pulled up to a high level, so the third switching element M3 is in the on state; the first clock signal CLK2 of this stage jumps from a low level to a high level; the second output terminal receives the high-level first clock signal CLK2 of this stage through the on-state third switching element M3, thereby the second output terminal outputs the high-level transmission signal Zn of this stage.

[0059] In one embodiment, the gate signal Gn+2 transitions from low to high level. The fourth control terminal of the fourth switching element M4 receives the high-level gate signal Gn+2, and the fourth switching element M4 becomes on. The first output terminal receives the first low-level signal VGL through the on-state fourth switching element M4 and quickly pulls it down to low level. This can effectively reduce the falling edge time of the gate signal without increasing the clock load, thereby improving the image quality of the product.

[0060] Drop-down phase:

[0061] Please refer to Figure 4 In the box, when the gate signal Gn+2 of the subsequent stage jumps from low level to high level, the node pull-down module 50 controls the first node Qn to receive the second clock signal CLK3 of this stage. Then, when the second clock signal CLK3 of this stage jumps from high level to low level, the first node Qn is stably pulled down to low level.

[0062] In one embodiment, when the gate signal Gn+2 transitions from low to high, the fifth control terminal of the fifth switching element M5 receives the high-level gate signal Gn+2, and the fifth switching element M5 becomes on. Consequently, the first node Qn, connected to the ninth path terminal of the fifth switching element M5, receives the second clock signal CLK3 of this stage from the tenth path terminal of the fifth switching element M5 through the on-state fifth switching element M5. Therefore, when the second clock signal CLK3 transitions from high to low, the first node Qn is stably pulled down to a low level.

[0063] In one embodiment, when the first node Qn is pulled down to a low level, the second control terminal of the second switching element M2 and the third control terminal of the third switching element M3 connected to the first node Qn become low level, and the second switching element M2 and the third switching element M3 become disconnected, thereby causing the first output module 20 and the second output module 30 to enter a non-working state.

[0064] In one embodiment, when the first node Qn is pulled down to a low level, the tenth control terminal of the tenth switching element M10 and the eleventh control terminal of the eleventh switching element M11 connected to the first node Qn become low level, thus the tenth switching element M10 and the eleventh switching element M11 become disconnected. Simultaneously, because the first control signal V1 and the second control signal V2 have opposite polarities, the first control signal V1 controls the sixth switching element M6 and the seventh switching element M7 to be in a conducting state, charging the second node QB1 through the conducting sixth switching element M6 and discharging the third node QB2 to the second low-level signal VSQ through the conducting seventh switching element M7; or the second control signal V2 controls the eighth switching element M8 and the ninth switching element M9 to be in a conducting state, charging the third node QB2 through the conducting eighth switching element M8 and discharging the second node QB1 to the second low-level signal VSQ through the conducting ninth switching element M9. Therefore, the first control signal V1 and the second control signal V2 alternately control the second node QB1 and the third node QB2 to be at high and low levels, causing the twelfth switch element M12, the fourteenth switch element M14, and the sixteenth switch element M16 connected to the second node QB1, and the thirteenth switch element M13, the fifteenth switch element M15, and the seventeenth switch element M17 connected to the third node QB2 to conduct alternately. Thus, the first node Qn alternately receives the second low-level signal VSQ through the connected twelfth switch element M12 and the thirteenth switch element M13, the first output terminal alternately receives the first low-level signal VGL through the connected fourteenth switch element M14 and the fifteenth switch element M15, and the second output terminal alternately receives the first low-level signal VGL through the connected sixteenth switch element M16 and the seventeenth switch element M17, achieving a stable low-level effect.

[0065] Stable phase:

[0066] Please refer to Figure 5 In the boxed area, i.e., during the time period excluding the first three stages, if the pre-charge module 10 receives a low-level front-stage transmission signal Zn-2, then the pre-charge module 10 enters a non-operating state. Similarly, if the node pull-down module 50 receives a low-level rear-stage gate signal Gn+2, then the node pull-down module 50 enters a non-operating state. Therefore, the pre-charge module 10 and the node pull-down module 50 have no effect on the first node Qn, and the stabilization module 60 can be used to maintain the first node Qn, the first output terminal, and the second output terminal at a low level.

[0067] In one embodiment, during the stabilization phase, the first node Qn has been pulled down to a low level. Then, the second control terminal of the second switching element M2 and the third control terminal of the third switching element M3 connected to the first node Qn are at a low level. Thus, the second switching element M2 and the third switching element M3 are in an open state, thereby causing the first output module 20 and the second output module 30 to enter a non-working state.

[0068] In one embodiment, during the stabilization phase, the first node Qn has been pulled down to a low level. Therefore, the tenth control terminal of the tenth switching element M10 and the eleventh control terminal of the eleventh switching element M11, both connected to the first node Qn, are at a low level, and thus the tenth and eleventh switching elements M10 and M11 are in an off state. Simultaneously, because the first control signal V1 and the second control signal V2 have opposite polarities, the first control signal V1 controls the sixth and seventh switching elements M6 to be in a conducting state. The conducting sixth switching element M6 charges the second node QB1, and the conducting seventh switching element M7 discharges the third node QB2 to the second low-level signal VSQ. Alternatively, the second control signal V2 controls the eighth and ninth switching elements M8 to be in a conducting state. The conducting eighth switching element M8 charges the third node QB2, and the conducting ninth switching element M9 discharges the second node QB1 to the second low-level signal VSQ. Therefore, the first control signal V1 and the second control signal V2 alternately control the second node QB1 and the third node QB2 to be at high and low levels, causing the twelfth switch element M12, the fourteenth switch element M14, and the sixteenth switch element M16 connected to the second node QB1, and the thirteenth switch element M13, the fifteenth switch element M15, and the seventeenth switch element M17 connected to the third node QB2 to be alternately turned on. Thus, the first node Qn alternately receives the second low-level signal VSQ through the connected twelfth switch element M12 and the thirteenth switch element M13, the first output terminal alternately receives the first low-level signal VGL through the connected fourteenth switch element M14 and the fifteenth switch element M15, and the second output terminal alternately receives the first low-level signal VGL through the connected sixteenth switch element M16 and the seventeenth switch element M17, achieving a stable low-level effect.

[0069] Therefore, during the stabilization phase, regardless of the changes in the pre-charge module 10's received front-stage transmission signal Zn-2 and front-stage gate signal Gn-2, the node pull-down module 50's received rear-stage gate signal Gn+2 and local-stage second clock signal CLK3, and the first output module 20 and second output module 30's received local-stage first clock signal CLK2, the stabilization module 60 can maintain the first node Qn, the first output terminal, and the second output terminal at a low level. This releases charges, such as those coupled due to clock feedthrough in the parasitic capacitance of the second switching element M2, ensuring the stability of the first node Qn, the output local-stage gate signal Gn, and the local-stage transmission signal. Furthermore, during the pre-charge phase, each voltage pull-up on the first node Qn occurs on the second low-level signal VSQ, resulting in a relatively stable pull-up voltage. This prevents voltage drift in the first node Qn, making the voltage of the first node Qn more stable, thereby increasing circuit stability and improving display reliability. In one embodiment, the voltages of the second node QB1 and the third node QB2 are more stable, which makes the operating state of the connected switching elements more stable and reduces the impact of ambient temperature on the circuit. That is, due to the original drift phenomenon, the voltage drift will not exceed a certain threshold when the temperature is too high or too low, causing the connected switching elements to operate abnormally. In addition, the more stable voltages of the second node QB1 and the third node QB2 will also broaden the timing design of the second node QB1 and the third node QB2.

[0070] Figure 6 This is a cascaded circuit diagram of a gate transfer circuit according to an embodiment of the present invention. The gate transfer circuit of this embodiment includes multiple... Figure 1 In the gate transfer unit, the gate transfer units can be connected sequentially or sequentially with intervals between them. Figure 6 In the example, the nth-stage gate transfer unit is connected to the (n-2)th-stage gate transfer unit and the (n+2)th-stage gate transfer unit respectively. The number of gate transfer units in the gate transfer circuit is not limited; it can be 4, 8, or more, for example, the number of gate lines. Figure 6In the example, each gate transfer unit receives the preceding stage gate signal Gn-2, the preceding stage transfer signal Zn-2, and the following stage gate signal Gn+2, and outputs its own stage gate signal Gn and its own stage transfer signal Zn. The preceding stage gate signal Gn-2 and the preceding stage transfer signal Zn-2 received by the first two gate transfer units can be corresponding enable signals STV1, and the following stage gate signal Gn+2 received by the last two gate transfer units can be corresponding pull-down signals STV2. Each gate transfer unit can also share multiple input signals, including a first low-level signal VGL, a second low-level signal VQS, two control signals, and a set of clock signals. In one embodiment, when receiving the two control signals, the first control signal V1 received by any gate transfer unit is the second control signal V2 received by the adjacent gate transfer unit. In one embodiment, the set of clock signals consists of N phase difference clocks, and the phase difference between two adjacent phase difference clocks is one-Nth of a period, where N can be 4 or 8, etc. In one embodiment, when receiving the set of clock signals, the phase difference between the first clock signal of the current stage received by any gate transfer unit and the first clock signal of the current stage received by the adjacent gate transfer unit is one-Nth of a period, and the phase difference between the second clock signal of the current stage received by any gate transfer unit and the second clock signal of the current stage received by the adjacent gate transfer unit is one-Nth of a period.

[0071] In one embodiment of the present invention, a gate transfer circuit is provided on one of the left and right sides of the display panel, and a plurality of gate transfer units of the gate transfer circuit are connected to the gate lines one by one.

[0072] In one embodiment of the present invention, gate transfer circuits are provided on both the left and right sides of the display panel, and multiple gate lines are alternately connected to the gate transfer unit on the left and the gate transfer unit on the right.

[0073] In one embodiment of the present invention, such as Figure 6 As shown, gate transfer circuits are provided on both the left and right sides of the display panel, and gate transfer units are provided at both ends of any gate line. One of the two gate transfer units at both ends of the gate line outputs a gate signal for non-double-ended charging; or, both gate transfer units at both ends of the gate line output gate signals simultaneously for double-ended charging.

[0074] Figure 7This is a full-stage circuit diagram of a gate transfer circuit according to an embodiment of the present invention. The gate transfer circuit of this embodiment further includes a signal providing module 200, which provides corresponding input signals to multiple gate transfer units. The signal providing module 200 can be composed of multi-stage substrate gate driving circuits and signal lines. In one embodiment, the signal providing module 200 is disposed in the middle of multiple gate transfer units, thereby allowing multiple gate transfer units to be connected upwards and downwards, and / or to the left and right, respectively. Figure 7 Taking the displayed gate transfer circuit as an example, the signal providing module 200 can be provided with eight gate transfer units on each of its upper left, lower left, upper right, and lower right sides. The eight gate transfer units on each of these four sides achieve eight-level output connections, allowing the signal providing module 200 to connect to the gate transfer units on each side and provide an input signal to each side. Figure 8 In the example, each gate transfer unit receives the preceding gate signal Gn-2, the preceding transfer signal Zn-2, and the following gate signal Gn+2, and outputs its own gate signal Gn and its own transfer signal Zn. The preceding gate signal Gn-2 and the preceding transfer signal Zn-2 received by the first two gate transfer units on each side can be corresponding enable signals STV1 provided by the signal providing module 200 or other external signal circuits. The following gate signal Gn+2 received by the last two gate transfer units can be corresponding pull-down signals STV2 provided by the signal providing module 200 or other external signal circuits. Each gate transfer unit can also share multiple input signals, including a first low-level signal VGL, a second low-level signal VQS, two control signals, and a set of clock signals. In one embodiment, when receiving the two control signals, the first control signal V1 received by any gate transfer unit is the second control signal V2 received by the adjacent gate transfer unit. In one embodiment, the set of clock signals consists of N phase difference clocks, and the phase difference between two adjacent phase difference clocks is one-Nth of a period, where N can be 4 or 8, etc. Figure 8 For example, this set of clock signals consists of four phase-difference clocks, with the phase difference between any two adjacent phase-difference clocks being one-quarter of a cycle. The phase difference between the first clock signal CLK2 received by any gate transfer unit and the first clock signal CLK2 received by the adjacent gate transfer unit is one-quarter of a cycle. Similarly, the phase difference between the second clock signal CLK3 received by any gate transfer unit and the second clock signal CLK3 received by the adjacent gate transfer unit is one-quarter of a cycle. Figure 9As shown, multiple gate transfer units in the gate transfer circuit can sequentially output the gate signal of the current stage. For example, four consecutive gate transfer units can sequentially output the gate signals Gn-2, Gn-1, Gn and Gn+1 of the current stage, and the falling edge time of each gate signal of the current stage is short, that is, it is quickly pulled down to the low level.

[0075] Figure 10 yes Figure 1 A comparative schematic diagram of gate signals for a 17T1C gate transfer unit and a 16T1C gate transfer unit is shown. In one embodiment of the present invention, the gate transfer unit of the gate transfer circuit is provided with an output pull-down module 40, such as... Figure 1 The diagram shows a 17T1C structure, consisting of 17 switching elements and 1 capacitor. In contrast, a gate pass unit without an output pull-down module 40 represents a 16T1C structure, consisting of 16 switching elements and 1 capacitor. From... Figure 10 It can be seen that the falling edge time of the gate signal in the 17T1C structure gate transfer unit of this embodiment is shorter than that in the 16T1C structure gate transfer unit. Measurements show that the falling edge time of the gate signal in the 17T1C structure gate transfer unit of this embodiment is 5.3 μs, and the falling edge time of the gate signal in the 16T1C structure gate transfer unit is 7.7 μs. Therefore, this embodiment can reduce the falling edge time of the gate signal and improve product image quality without increasing the clock load.

[0076] Figure 11 This is a schematic diagram of the gate transfer circuit according to another embodiment of the present invention. Figure 12 yes Figure 11 The circuit connection diagram of the gate transfer unit 100 is shown below. Please refer to the diagram. Figure 11 and Figure 12 The basic structure, principle, and technical effects of the gate transfer circuit in this embodiment are basically the same as those in the previous embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content of the previous embodiment. The difference in this embodiment is that the output pull-down module 40 is located at the tail end of the gate line and is connected to the first output terminal through the gate line.

[0077] Specifically, a gate transfer unit 100 is disposed on one side of the display panel, such as the left side. The first output terminal of the gate transfer unit 100 is connected to the left end of a gate line. The gate line is connected to multiple thin-film transistors on the display panel, generating corresponding resistors RGate and capacitors Cgate. An output pull-down module 40 is disposed on the other side of the display panel, such as the right side. The output pull-down module 40 is connected to the tail end Gn_end of the gate line, and is then connected to the first output terminal through the gate line. In the output stage of the gate transfer unit 100, the first output terminal outputs a high-level gate signal Gn. Then, the subsequent gate signal Gn+2 jumps from low to high. The fourth control terminal of the fourth switch element M4 in the output pull-down module 40 receives the high-level subsequent gate signal Gn+2, and the fourth switch element M4 becomes on. The first output terminal receives the first low-level signal VGL through the gate line and the on-state fourth switch element M4, and quickly pulls down to low. This can effectively reduce the falling edge time of the gate signal without increasing the clock load, thus improving the image quality of the product. At the same time, it can reduce the space occupied by the gate transfer unit 100 on one side of the display panel, effectively saving layout area and facilitating the narrow bezel design of the display device.

[0078] In one embodiment of the present invention, a gate transfer circuit is provided on one side of the display panel, and a plurality of gate transfer units 100 of the gate transfer circuit are connected to the gate lines one by one. A plurality of output pull-down modules 40 are provided on the other side of the display panel, and the output pull-down modules 40 are located at the end of the gate lines and are connected to the first output terminal through the gate lines.

[0079] In one embodiment of the present invention, such as Figure 11 As shown, gate transfer circuits are provided on both sides of the display panel. The output pull-down module 40 in the gate transfer unit 100 is located on the opposite side. Among the two adjacent gate lines, the first gate line is connected to the gate transfer unit 100 on the left and the output pull-down module 40 on the right. The second gate line is connected to the output pull-down module 40 on the left and the gate transfer unit 100 on the right.

[0080] Figure 13 and Figure 14 They are Figure 11A clock signal diagram and a gate signal diagram are shown in one embodiment. In one embodiment, gate transfer circuits are provided on both sides of the display panel. The output pull-down module 40 in the gate transfer unit 100 is located on the opposite side. For example, the first-stage gate transfer unit 100 is located on the left side of the display panel, and the corresponding output pull-down module 40 is located on the right side of the display panel; the second-stage gate transfer unit 100 is located on the right side of the display panel, and the corresponding output pull-down module 40 is located on the left side of the display panel, and so on, in sequence. Each gate transfer unit receives the previous stage gate signal Gn-4, the previous stage transfer signal Zn-4, and the subsequent stage gate signal Gn+4, and outputs the current stage gate signal Gn and the current stage transfer signal Zn. The previous stage gate signal Gn-4 and the previous stage transfer signal Zn-4 received by the first two gate transfer units on each side can be the corresponding enable signal STV1, and the subsequent stage gate signal Gn+4 received by the last two gate transfer units can be the corresponding pull-down signal STV2. Each gate transfer unit can also share multiple input signals, including a first low-level signal VGL, a second low-level signal VQS, two control signals, and a set of clock signals. In one embodiment, when receiving the two control signals, the first control signal V1 received by any gate transfer unit is the second control signal V2 received by the adjacent gate transfer unit. In one embodiment, the set of clock signals consists of N phase difference clocks, and the phase difference between two adjacent phase difference clocks is one-Nth of a period, where N can be 4 or 8, etc. Figure 13 For example, this set of clock signals consists of eight phase difference clocks, with the phase difference between any two adjacent phase difference clocks being one-eighth of a period. The first phase difference clock CLK1, the third phase difference clock CLK3, the fifth phase difference clock CLK5, and the seventh phase difference clock CLK7 can be placed on the left side of the display panel, and the second phase difference clock CLK2, the fourth phase difference clock CLK4, the sixth phase difference clock CLK6, and the eighth phase difference clock CLK8 can be placed on the right side of the display panel. The phase difference between the first clock signal CLK2 received by any gate transfer unit and the first clock signal CLK2 received by an adjacent gate transfer unit is one-eighth of a period, and the phase difference between the second clock signal CLK4 received by any gate transfer unit and the second clock signal CLK4 received by an adjacent gate transfer unit is one-eighth of a period. For example... Figure 14 As shown, multiple gate transfer units in the gate transfer circuit can sequentially output the gate signal of their respective stage. For example, eight consecutive gate transfer units can sequentially output the gate signals Gn-4, Gn-3, Gn-2, Gn-1, Gn, Gn+1, Gn+2, and Gn+3 of their respective stage, and the falling edge time of each gate signal is relatively short, that is, it is quickly pulled down to a low level.

[0081] Based on the same inventive concept, embodiments of the present invention also provide a display device, which includes a gate transfer circuit as provided in the above embodiments, for providing gate signals to the gate lines of the display panel. Implementation of this display device can refer to the embodiments of the gate transfer circuit described above; repeated details will not be elaborated further.

[0082] The gate transfer circuit and display device provided by this invention include a multi-stage gate transfer unit. Each stage of the gate transfer unit includes a pre-charge module, a first output module, a second output module, an output pull-down module, a node pull-down module, and a stabilization module. The output pull-down module is connected to the first output module at a first output terminal and pulls the first output terminal down to a low level based on the subsequent gate signal and a first low-level signal. Therefore, the gate transfer circuit can sequentially output multiple gate signals, exhibiting strong output capability and stability. Furthermore, it can reduce the falling edge time of the gate signal without increasing the clock load, thus improving product image quality. Simultaneously, the gate transfer circuit uses fewer unit components, effectively saving layout area and facilitating narrow bezel design in the display device.

[0083] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the invention without departing from the scope of the invention shall still fall within the scope of the present invention.

Claims

1. A gate pass circuit comprising a plurality of stages of gate pass cells, characterized by, Each stage of the gate transfer unit includes: A pre-charge module (10) is connected to a first node (Qn) and charges the first node (Qn) according to the front-end transmission signal and the front-end gate signal. The first output module (20) is connected to the precharge module (10) at the first node (Qn). Based on the potential of the first node (Qn) and the first clock signal of this stage, the first output module (20) outputs the gate signal of this stage at the first output terminal. The second output module (30) is connected to the pre-charge module (10) at the first node (Qn). Based on the potential of the first node (Qn) and the first clock signal of this stage, the second output module (30) outputs the transmission signal of this stage at the second output terminal. Output pull-down module (40), the output pull-down module (40) is disposed at the tail end of the gate line, electrically connected to the first output terminal through the gate line, and receives the subsequent gate signal and the first low level signal (VGL), and is used to pull down the end of the gate line to a low level when the subsequent gate signal is valid, so as to compensate for the signal delay caused by the resistance and capacitance of the gate line; A node pull-down module (50) is connected to the precharge module (10) at the first node (Qn). The node pull-down module (50) pulls the first node (Qn) down to a low level according to the subsequent gate signal and the second clock signal of this stage. A stabilization module (60) is connected to the first node (Qn), the first output terminal and the second output terminal. The stabilization module (60) is used to maintain the first node (Qn), the first output terminal and the second output terminal at a low level when the first node (Qn) is pulled down to a low level.

2. The gate-pass circuit according to claim 1, wherein The pre-charge module (10) includes a first switching element (M1), which includes a first control terminal, a first path terminal, and a second path terminal. The first control terminal of the first switching element (M1) receives the pre-stage transmission signal, the first path terminal of the first switching element (M1) receives the pre-stage gate signal, and the second path terminal of the first switching element (M1) is connected to the first node (Qn).

3. The gate-pass circuit according to claim 1, wherein The first output module (20) includes a second switching element (M2), which includes a second control terminal, a third path terminal and a fourth path terminal. The second control terminal of the second switching element (M2) is connected to the first node, the third path terminal of the second switching element (M2) receives the first clock signal of the current stage, and the fourth path terminal of the second switching element (M2) is connected to the first output terminal.

4. The gate-pass circuit according to claim 1, wherein The second output module (30) includes a third switching element (M3), which includes a third control terminal, a fifth path terminal and a sixth path terminal. The third control terminal of the third switching element (M3) is connected to the first node (Qn), the fifth path terminal of the third switching element (M3) receives the first clock signal of this stage, and the sixth path terminal of the third switching element (M3) is connected to the second output terminal.

5. The gate-pass circuit according to claim 1, wherein The output pull-down module (40) includes a fourth switching element (M4), which includes a fourth control terminal, a seventh path terminal, and an eighth path terminal. The fourth control terminal of the fourth switching element (M4) receives the subsequent gate signal, the seventh path terminal of the fourth switching element (M4) receives the first output terminal, and the eighth path terminal of the fourth switching element (M4) is connected to the first low-level signal (VGL).

6. The gate-pass circuit according to claim 1, wherein The node pull-down module (50) includes a fifth switching element (M5), which includes a fifth control terminal, a ninth path terminal, and a tenth path terminal. The fifth control terminal of the fifth switching element (M5) receives the gate signal of the subsequent stage, the ninth path terminal of the fifth switching element (M5) is connected to the first node (Qn), and the tenth path terminal of the fifth switching element (M5) receives the second clock signal of this stage.

7. The gate transfer circuit according to claim 1, characterized in that, The stabilization module (60) includes: The sixth switching element (M6) includes a sixth control terminal, an eleventh path terminal, and a twelfth path terminal. The sixth control terminal of the sixth switching element (M6) receives a first control signal. The eleventh path terminal of the sixth switching element (M6) is connected to the sixth control terminal of the sixth switching element (M6). The twelfth path terminal of the sixth switching element (M6) is connected to the second node (QB1). The seventh switching element (M7) includes a seventh control terminal, a thirteenth path terminal, and a fourteenth path terminal. The seventh control terminal of the seventh switching element (M7) is connected to the eleventh path terminal of the sixth switching element (M6) and receives the first control signal (V1). The thirteenth path terminal of the seventh switching element (M7) receives a second low-level signal (VSQ). The fourteenth path terminal of the seventh switching element (M7) is connected to the third node (QB2). The eighth switching element (M8) includes an eighth control terminal, a fifteenth path terminal, and a sixteenth path terminal. The eighth control terminal of the eighth switching element (M8) receives a second control signal (V2). The fifteenth path terminal of the eighth switching element (M8) is connected to the third node (QB2). The sixteenth path terminal of the eighth switching element (M8) is connected to the eighth control terminal of the eighth switching element (M8). The ninth switching element (M9) includes a ninth control terminal, a seventeenth path terminal, and an eighteenth path terminal. The ninth control terminal of the ninth switching element (M9) is connected to the sixteenth path terminal of the eighth switching element (M8) and receives the second control signal (V2). The seventeenth path terminal of the ninth switching element (M9) is connected to the second node (QB1). The eighteenth path terminal of the ninth switching element (M9) receives the second low-level signal (VSQ). The tenth switching element (M10) includes a tenth control terminal, a nineteenth path terminal, and a twentieth path terminal. The tenth control terminal of the tenth switching element (M10) is connected to the first node (Qn). The nineteenth path terminal of the tenth switching element (M10) receives the second low-level signal (VSQ). The twentieth path terminal of the tenth switching element (M10) is connected to the second node (QB1). The eleventh switching element (M11) includes an eleventh control terminal, a twenty-first path terminal, and a twenty-second path terminal. The eleventh control terminal of the eleventh switching element (M11) is connected to the first node (Qn), the twenty-first path terminal of the eleventh switching element (M11) is connected to the nineteenth path terminal of the tenth switching element (M10), and receives the second low-level signal (VSQ). The twenty-second path terminal of the eleventh switching element (M11) is connected to the third node (QB2). The twelfth switching element (M12) includes a twelfth control terminal, a twenty-third path terminal, and a twenty-fourth path terminal. The twelfth control terminal of the twelfth switching element (M12) is connected to the second node (QB1), the twenty-third path terminal of the twelfth switching element (M12) is connected to the first node (Qn), and the twenty-fourth path terminal of the twelfth switching element (M12) receives the second low-level signal (VSQ). The thirteenth switching element (M13) includes a thirteenth control terminal, a twenty-fifth path terminal, and a twenty-sixth path terminal. The thirteenth control terminal of the thirteenth switching element (M13) is connected to the third node (QB2). The twenty-fifth path terminal of the thirteenth switching element (M13) is connected to the twenty-fourth path terminal of the twelfth switching element (M12) and receives the second low-level signal (VSQ). The twenty-sixth path terminal of the thirteenth switching element (M13) is connected to the first node (Qn). The fourteenth switching element (M14) includes a fourteenth control terminal, a twenty-seventh path terminal, and a twenty-eighth path terminal. The fourteenth control terminal of the fourteenth switching element (M14) is connected to the second node (QB1), the twenty-seventh path terminal of the fourteenth switching element (M14) is connected to the first output terminal, and the twenty-eighth path terminal of the fourteenth switching element (M14) receives the first low-level signal (VGL). The fifteenth switching element (M15) includes a fifteenth control terminal, a twenty-ninth path terminal, and a thirtieth path terminal. The fifteenth control terminal of the fifteenth switching element (M15) is connected to the third node (QB2). The twenty-ninth path terminal of the fifteenth switching element (M15) is connected to the twenty-eighth path terminal of the fourteenth switching element (M14) and receives the first low-level signal (VGL). The thirtieth path terminal of the fifteenth switching element (M15) is connected to the first output terminal. The sixteenth switching element (M16) includes a sixteenth control terminal, a thirty-first path terminal, and a thirty-second path terminal. The sixteenth control terminal of the sixteenth switching element (M16) is connected to the second node, the thirty-first path terminal of the sixteenth switching element (M16) is connected to the second output terminal, and the thirty-second path terminal of the sixteenth switching element (M16) receives the first low-level signal (VGL). The seventeenth switching element (M17) includes a seventeenth control terminal, a thirty-third path terminal, and a thirty-fourth path terminal. The seventeenth control terminal of the seventeenth switching element (M17) is connected to the third node (QB2). The thirty-third path terminal of the seventeenth switching element (M17) is connected to the thirty-second path terminal of the sixteenth switching element (M16) and receives the first low-level signal (VGL). The thirty-fourth path terminal of the seventeenth switching element (M17) is connected to the second output terminal.

8. The gate transfer circuit according to claim 7, characterized in that, The first control signal and the second control signal have opposite polarities, and their polarities are reversed once per frame.

9. A display device, characterized in that, Includes the gate transfer circuit as described in any one of claims 1-8.

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