EFlash controller based on AHB bus and electronic equipment

Abstract

The invention discloses an eFlash controller based on an AHB bus and electronic equipment, which are applied to the technical field of on-chip flash memories, the eFlash controller comprises a control module and a storage module, the control module is connected with the AHB bus, and the control module is connected with the storage module; a storage space in the storage module comprises a plurality of protection areas, and each protection area comprises at least one data page; the protection area is provided with a corresponding write protection bit; and when the write protection bit represents that the data page in the corresponding protection area is subjected to write protection, the control module is used for at least invalidating the erase operation and / or write operation executed on the data page subjected to write protection. By setting the protection area and the corresponding write protection position, whether the corresponding erase operation and the corresponding write operation are invalid or not is determined according to the state recorded by the write protection position when the erase operation is carried out, so that the write protection function is realized, and the on-chip flash memory is ensured not to generate data loss due to the erase operation.

Description

Technical Field

[0001] The present invention relates to the technical field of on-chip flash memory, and in particular to an eFlash controller based on an AHB bus and an electronic device. Background Art

[0002] eFlash (embedded Flash) is a flash memory technology integrated on the chip. It has programmable and erasable functions, can store and retain data, and can maintain data integrity even in the case of power failure. eFlash is often used in integrated circuit chips (ICs) to store program code, configuration information and other important data. The eFlash process usually uses smaller storage units, which can save chip area and provide higher storage density.

[0003] eFlash is mainly used in integrated circuit chips for high-density storage and program code storage. eFlash is easy to operate, has low power consumption and short operation time, but block operation is very inconvenient and may cause data loss due to improper operation. Therefore, how to design an eFlash controller architecture that is easy to use is an urgent problem that technicians in this field need to solve. Summary of the invention

[0004] An object of the present invention is to provide an eFlash controller based on an AHB bus, supporting write protection in units of pages to ensure that data will not be lost; another object of the present invention is to provide an electronic device, supporting write protection in units of pages to ensure that data will not be lost.

[0005] In order to solve the above technical problems, the present invention provides an eFlash controller based on an AHB bus, comprising: a control module and a storage module, wherein the control module is connected to the AHB bus, and the control module is connected to the storage module;

[0006] The storage space in the storage module includes multiple protection zones, each of which includes at least one data page; the protection zones have corresponding write protection bits; when the write protection bits indicate that the corresponding data page in the protection zone is write-protected, the control module is used to invalidate at least the erase operation and / or write operation performed on the write-protected data page.

[0007] Optionally, the control module is specifically used for:

[0008] The erase operation and / or write operation of the target including the write-protected data page is completely invalidated.

[0009] Optionally, the control module is further used for:

[0010] After the invalid erase operation and / or write operation, an interrupt signal based on hardware triggering is generated, and the interrupt signal is sent to the processor through the AHB bus.

[0011] Optionally, the data page is provided with a corresponding read protection bit, and when the write protection bit indicates that the corresponding data page is read protected, the control module is used to invalidate the read operation of the corresponding read protected data page.

[0012] Optionally, the control module is further used for:

[0013] After the invalid read operation, an interrupt signal based on hardware triggering is generated, and the interrupt signal is sent to the processor through the AHB bus.

[0014] Optionally, the storage space includes a main storage area and an information block, each protection area in the main storage area includes four data pages, and each protection area in the information block includes one data page.

[0015] Optionally, the control module is provided with an erase operation timing corresponding to the erase operation, a write operation timing corresponding to the write operation, and a read operation timing corresponding to the read operation;

[0016] The erase operation timing, the write operation timing and the read operation timing have operation times configured by registers, and the operation times include setup time and / or hold time of corresponding operations;

[0017] The operation time corresponding to the erase operation, the operation time corresponding to the write operation, and the operation time corresponding to the read operation are all different.

[0018] Optionally, the control module is provided with an operation state machine, the operation state machine includes a plurality of state paths, and the state paths correspond one-to-one to the types of operations executable by the storage module;

[0019] The control module is used for:

[0020] The corresponding state path is executed according to the received instruction, and a control signal of the corresponding operation type is generated and sent to the storage module, so that the storage module executes the corresponding operation.

[0021] Optionally, it also includes an external interrupt module, through which the control module is connected to the storage module; the external interrupt module is connected to a sleep signal line of the processor.

[0022] The present invention also provides an electronic device, comprising any one of the above-mentioned eFlash controllers based on the AHB bus.

[0023] An AHB bus-based eFlash controller provided by the present invention comprises: a control module and a storage module, wherein the control module is connected to the AHB bus, and the control module is connected to the storage module; the storage space in the storage module comprises a plurality of protection zones, each protection zone comprises at least one data page; the protection zones have corresponding write protection bits; when the write protection bit indicates that the data page in the corresponding protection zone is write-protected, the control module is used to invalidate at least an erase operation and / or a write operation performed on the write-protected data page.

[0024] By setting the protection zone and the corresponding write protection bit, when performing erase and write operations, it is determined whether the corresponding erase and write operations are invalid according to the status recorded in the write protection bit, thereby realizing the write protection function and ensuring that the on-chip flash memory will not cause data loss due to erase and write operations.

[0025] This embodiment also provides an electronic device, which also has the above-mentioned beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] FIG1 is a schematic diagram of the structure of an AHB bus-based eFlash controller provided by an embodiment of the present invention;

[0028] Figure 2 is a schematic diagram of the control module interface;

[0029] FIG3 is a schematic diagram of an operation state machine;

[0030] Figure 4 This is a schematic diagram of the sleep state machine;

[0031] Figure 5 This is a schematic diagram of the external interrupt module interface;

[0032] Figure 6 This is the timing diagram for the read operation;

[0033] Figure 7 This is the timing diagram for write operation;

[0034] Figure 8 This is the timing diagram of page erase operation;

[0035] Fig. 9 This is the chip erase operation timing diagram;

[0036] Fig.10 This is the timing diagram for write / erase abort operation;

[0037] Fig.11 This is the timing diagram for entering and exiting sleep mode (CS=1, SLEEP=1);

[0038] Fig.12 This is the timing diagram for entering and exiting sleep mode (CS=0);

[0039] Fig.13 This is the power-on timing diagram. DETAILED DESCRIPTION

[0040] The core of the present invention is to provide an eFlash controller based on the AHB bus. In the prior art, eFlash is easy to operate, has low power consumption and short operation time, but the block operation is very inconvenient and data loss may occur when the operation is not done properly.

[0041] The present invention provides an eFlash controller based on an AHB bus, comprising: a control module and a storage module, wherein the control module is connected to the AHB bus, and the control module is connected to the storage module; the storage space in the storage module comprises a plurality of protection zones, each protection zone comprises at least one data page; the protection zones have corresponding write protection bits; when the write protection bit indicates that the data page in the corresponding protection zone is write-protected, the control module is used to invalidate at least an erase operation and / or a write operation performed on the write-protected data page.

[0042] By setting the protection zone and the corresponding write protection bit, when performing erase and write operations, it is determined whether the corresponding erase and write operations are invalid according to the status recorded in the write protection bit, thereby realizing the write protection function and ensuring that the on-chip flash memory will not cause data loss due to erase and write operations.

[0043] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0044] Embodiment 1

[0045] Please refer to Figures 1 to Fig.13 , FIG. 1 is a schematic diagram of the structure of an eFlash controller based on an AHB bus provided by an embodiment of the present invention; FIG. 2 is a schematic diagram of a control module interface; FIG. 3 is a schematic diagram of an operation state machine; Figure 4 This is a schematic diagram of the sleep state machine; Figure 5 This is a schematic diagram of the external interrupt module interface; Figure 6 This is the timing diagram for the read operation; Figure 7This is the timing diagram for write operation; Figure 8 This is the timing diagram of page erase operation; Fig. 9 This is the chip erase operation timing diagram; Fig.10 This is the timing diagram for write / erase abort operation; Fig.11 This is the timing diagram for entering and exiting sleep mode (CS=1, SLEEP=1); Fig.12 This is the timing diagram for entering and exiting sleep mode (CS=0); Fig.13 This is the power-on timing diagram.

[0046] Referring to FIG. 1 , in this embodiment, an eFlash controller based on an AHB bus includes: a control module and a storage module, wherein the control module is connected to the AHB bus, and the control module is connected to the storage module; the storage space in the storage module includes a plurality of protection zones, each of which includes at least one data page; the protection zones have corresponding write protection bits; when the write protection bit indicates that the corresponding data page in the protection zone is write-protected, the control module is used to invalidate at least an erase operation and / or a write operation performed on the write-protected data page.

[0047] The AHB (Advanced High Performance Bus) bus is mainly used for the connection between high-performance modules (such as eFlash, CPU, DMA and DSP, etc.) as the on-chip system bus of SoC (System on Chip). eFlash (Embedded Flash) is an embedded flash memory, a non-volatile memory that can retain data for a long time without current supply. Its storage characteristics are equivalent to hard disks. This characteristic is the basis for flash memory to become the storage medium of various portable digital devices.

[0048] This embodiment mainly provides an eFlash controller, wherein the control module mainly implements the control function of the eFlash, and the storage module is mainly used to implement the storage function of the eFlash. The control module usually needs to be connected to the AHB (Advanced High Performance Bus) bus, and other components usually access the eFlash through the AHB bus. The data transmitted from the AHB bus will first pass through the control module, and the operation of the storage space in the eFlash is implemented through the control module.

[0049] In this embodiment, the storage space of the eFlash is specifically divided into pages and blocks, wherein a page generally includes 1K bytes, and a block generally includes at least one page. In this embodiment, the storage space includes multiple protection zones, and each protection zone includes at least one data page, and a data page generally includes 1K bytes. Of course, in this embodiment, there is no specific limitation on the specific size of a data page, which depends on the specific situation.

[0050] In this embodiment, the above-mentioned protection zone has a corresponding write protection bit, and the mark recorded in the write protection bit can indicate whether the data page in the corresponding protection zone is write-protected. For example, when the write protection bit of a protection zone is recorded as 1, it means that the data page in the protection zone is write-protected; when the write protection bit of a protection zone is recorded as 0, it means that the data page in the protection zone is not write-protected.

[0051] In this embodiment, when the write protection bit indicates that the data page in the corresponding protection zone is write-protected, the control module is used to invalidate at least the erase operation and / or write operation performed on the write-protected data page. That is, when the control module determines that the erase operation and write operation it receives are specifically performed on the write-protected data page, at least the operation performed on the write-protected data page will be invalidated to achieve write protection of the data page.

[0052] Specifically, in this embodiment, the control module is specifically used to: invalidate the entire erase operation and / or write operation whose target includes the write-protected data page. For example, when a certain erase operation specifically erases data of three data pages, that is, the target of the erase operation corresponds to three data pages, and one of the data pages is write-protected by its corresponding write protection bit, when the control module receives the above erase operation, the entire erase operation will be invalidated, that is, the data in the above three data pages will not be erased.

[0053] In this embodiment, the control module is further used to: after the invalid erase operation and / or write operation, generate an interrupt signal based on hardware triggering, and send the interrupt signal to the processor through the AHB bus. That is, after the control module invalidates the erase operation or write operation according to the above content, it will generate an interrupt signal based on hardware generation, and send the interrupt signal to the processor through the AHB bus for processing. The interrupt signal is specifically generated by hardware, not by software, so that the reliability of the interrupt signal can be guaranteed.

[0054] In this embodiment, the data page is provided with a corresponding read protection bit. When the write protection bit indicates that the corresponding data page is read protected, the control module is used to invalidate the read operation of the corresponding read protected data page.

[0055] That is, this embodiment can implement the read protection function in units of data pages. Specifically, similar to the above-mentioned write protection, in this embodiment, a corresponding read protection bit is set for each data page, and the identifier recorded in the read protection bit can indicate whether the corresponding data page is read protected. For example, when a read protection bit is recorded as 1, it means that the data page is read protected; when a read protection bit is recorded as 0, it means that the data page is not read protected.

[0056] In this embodiment, when the read protection bit indicates that the corresponding data page is read-write protected, the control module is used to invalidate the read operation of the corresponding read-protected data page. That is, when the control module determines that the read operation it receives is specifically an operation performed on the above-mentioned read-protected data page, the read operation performed on the read-protected data page will be invalidated to achieve read protection of the data page.

[0057] In this embodiment, the control module is further used to: generate an interrupt signal based on hardware triggering after an invalid read operation, and send the interrupt signal to the processor through the AHB bus. That is, after the control module invalidates the read operation according to the above content, it will generate an interrupt signal based on hardware generation, and send the interrupt signal to the processor through the AHB bus for processing. The interrupt signal is specifically generated by hardware, not by software, so that the reliability of the interrupt signal can be guaranteed.

[0058] In this embodiment, the storage space generally includes a main storage area and an information block. Each protection area in the main storage area includes four data pages, and each protection area in the information block includes one data page.

[0059] In this embodiment, 128K bytes of on-chip main storage and 16K bytes of information storage can be used as an example to illustrate the storage space of the system program, wherein the on-chip main storage corresponds to the above-mentioned main storage area, and the information storage corresponds to the above-mentioned information block. Of course, in this embodiment, the size of the eFlash storage space can be dynamically adjusted according to the actual application situation. In this embodiment, the eFlash controller supports read operations, page erase, and full chip erase, and can be programmed to write data in 32-bit mode, and its erase and write life is at least 100,000 times. The main storage area can be specifically divided into 128 pages, 1K bytes per page; the information block can be specifically divided into 16 pages, 1K bytes per page. The starting address of the main storage area is: 0x0800_0000-0x0801_FFFF, and the starting address of the information block is: 0x0400_0000-0x0400_3FFF. The specific memory distribution is shown in Tables 1 and 2 below:

[0060] Table 1. eFlash main storage space

[0061]

[0062] Table 2. eFlash information block storage space

[0063]

[0064] In this embodiment, the specific composition of eFlash is described as follows:

[0065] The flash memory space consists of 64-bit wide storage units, which can store both code and data. The main storage area is set as 128 pages of 1K bytes per page or 32 write protection areas of 4K bytes per block. The main storage area can be erased by page (Page Erase) and read protected by page. The main storage area is set with 4 pages (4K bytes) as a write protection area to set write protection. The entire on-chip Flash consists of two parts: one is the main storage area, and the other is the information block.

[0066] In this embodiment, the main storage area is used to store user codes and data. The main storage area can be erased, written, and read based on the user code. Each 1K byte in the main storage area is called a page, which is the smallest unit that can be erased; in addition, write protection is allocated in units of 1 write protection area (4K bytes, 4 pages = 1 write protection area). For the information block part, the user can erase, write, and read it through the specified process.

[0067] In addition to the control module and storage module, this embodiment generally includes an external interrupt module, through which the control module is connected to the storage module; the external interrupt module is connected to the sleep signal line of the processor. The external interrupt module is used to implement the sleep function and the sleep wake-up function of the eFlash controller, and is responsible for the transmission of signals between the control module and the storage module.

[0068] Referring to FIG. 1 , in this embodiment, the control module generally includes the address decoding and generating logic of eFlash_addr, as well as the read-write-erase protection mechanism, configuration register, status register, etc., which is connected to the AHB bus, DFT test port, JTAG burning port, etc.; the external interrupt module generally receives the control signal generated by the eFlash control sleep mode FSM (sleep state machine) and the control signal generated by the eFlash control read-write-erase main FSM (operation state machine); the storage module generally includes functional sub-modules such as a high voltage generator, control logic, address cache, Flash storage unit, etc.

[0069] In this embodiment, the eFlash controller is generally divided into register read and write, address decoding, read-write and erase protection mechanism and read-write and erase timing generation according to the design function. The specific description of the control module, ie, the eflash_ctrl module interface, is shown in FIG2 .

[0070] The key signals of the control module interface are explained as shown in Table 3 below:

[0071] Table 3. Input and output interface signals of the control module in the eFlash controller

[0072]

[0073] In this embodiment, the control module is provided with an operation state machine, and the operation state machine includes a plurality of state paths, and the state paths correspond to the types of operations executable by the storage module one by one; the control module is used to: execute the corresponding state path according to the received instruction, generate a control signal of the corresponding operation type and send it to the storage module, so that the storage module performs the corresponding operation. In this embodiment, the data reading, writing and erasing are realized by controlling the jump of the operation state machine, because in the digital circuit design, the control signal generated by the state machine is more stable and safer than that generated by the conventional circuit design. Therefore, in this embodiment, the control signal is generated based on the jump of the control operation state machine in the above manner, and then the data reading, writing and erasing operations are realized according to the control signal, which can ensure the stability of the operation of the eFlash controller.

[0074] In this embodiment, the main state machine is generated in the read-write-erase timing of the control module, that is, the above-mentioned operation state machine is designed as shown in FIG3 , and each state of the operation state machine is described in detail as follows:

[0075] ST_PRE_CS: Idle state. When the system starts to power on, the state machine is in this state. A software soft reset can also put the state machine in this state. The system will enter the next state after the power-on state stabilizes for at least tPUW=10us (see the subsequent power-on sequence).

[0076] ST_PRE_OE: Read mode enable state. After the chip select (CS) is pulled high, wait for tCSHOEH = 5us to be high level, and then the read mode enable (OE) is pulled high again (see the subsequent power-on sequence).

[0077] ST_PRE_RD: Read data mode setup time state. After OE is pulled high, wait for at least tRDEN = 20.1us to be high level, AE (address enable) is pulled high, or the TBIT signal is in the process of 1->0 falling edge (see the subsequent read operation timing).

[0078] ST_TRIM: trim option wait time status.

[0079] ST_WAIT: Enter the read-write-erase waiting state. In this state, the read-write-erase state is selected according to different read-write-erase modes.

[0080] ST_WAKE_UP: The CPU wakes up from sleep mode. It will wake up according to the signal generated by other peripherals outside the chip, so that the chip can continue to work normally.

[0081] ST_RD: Read mode state. In this state, data is read and sent to the chip external peripheral module through the AHB bus to control its operation.

[0082] ST_EXT_RD: exit the read mode state. When exiting this state, you need to wait for at least tEXTRD = 10.1us to be high level, or the TBIT signal is in the process of 1->0 falling edge (see the subsequent read operation timing).

[0083] ST_RDOEH: The length of time that OE remains high in read mode. After OE is pulled high in read mode, it remains high for at least tRDOEH = 25us.

[0084] ST_PROGRAM: Write mode state. In write mode, the write operation needs to maintain a high level for a maximum of tPROG = 20us. When the maximum time is reached, it is necessary to jump out of this state and enter the ST_WAIT state for the next round of operations, or the TBIT signal is in the process of falling edge from 1 to 0 (see the subsequent write operation timing).

[0085] ST_EP: Page erase mode state. In the page erase mode, the erase operation needs to maintain a high level for a maximum of tSER = 2ms. When the maximum time is reached, it is necessary to jump out of this state and enter the ST_WAIT state for the next round of operation, or the TBIT signal is in the process of falling edge from 1->0 (see the subsequent page erase operation timing).

[0086] ST_EM: Chip erase mode state. In chip erase mode, the erase operation needs to maintain a high level for a maximum of tMER = 10ms. When the maximum time is reached, it is necessary to jump out of this state and enter the ST_WAIT state for the next round of operations, or the TBIT signal is in the process of falling edge from 1->0 (see the subsequent chip erase operation timing).

[0087] In this embodiment, the normal read-write-erase closed-loop jump operation of the operating state machine is as follows:

[0088] Read Operation:

[0089] The closed-loop jump path of a normal read (read) of the eFlash controller state machine is: ST_PRE_CS (this state is processed only when powered on) -> ST_PRE_OE -> ST_PRE_RD -> ST_TRIM -> ST_WAIT -> ST_RD -> ST_WAIT -> ST_EXT_RD -> ST_PRE_OE.

[0090] Write Operation:

[0091] The closed-loop jump path of a normal program in the eFlash controller state machine is: ST_PRE_CS->ST_PRE_OE->ST_PRE_RD->ST_TRIM->ST_WAIT->ST_PROGRAM->ST_WAIT ->ST_PRE_OE.

[0092] Page Erase Operation:

[0093] The closed-loop jump path of a normal page erase in the eFlash controller state machine is: ST_PRE_CS->ST_PRE_OE->ST_PRE_RD->ST_TRIM->ST_WAIT->ST_EP->ST_WAIT->ST_PRE_OE.

[0094] Chip Erase Operation:

[0095] The closed-loop jump path of a normal chip erase in the eFlash controller state machine is: ST_PRE_CS->ST_PRE_OE->ST_PRE_RD->ST_TRIM->ST_WAIT->ST_EM->ST_WAIT->ST_PRE_OE.

[0096] Wake-up sleep mode operation:

[0097] The closed-loop jump path for the eFlash controller state machine to exit sleep mode is: ST_PRE_CS->ST_PRE_OE->ST_PRE_RD->ST_TRIM-> ST_WAKEUP ->ST_PRE_RD.

[0098] In this embodiment, the internal sleep state machine of the control module is designed as follows Figure 4 As shown, each state of the sleep state machine is described in detail as follows:

[0099] ST_IDLE: Sleep idle state.

[0100] ST_OELSLEEPH: Enter the sleep mode waiting state. OE remains at a low level for at least tOELSLEEPH = 10us and enters the next state (see the subsequent entry and exit sleep mode timing).

[0101] ST_SLEEP: Sleep mode state. To enter this state, you need to wait for at least tSLEEP = 10us in this state (see the subsequent entry and exit sleep mode timing).

[0102] ST_WAIT_WK: Waiting for CPU wake-up state.

[0103] ST_SLEEPLOEH: exit sleep mode. To enter this state, you need to wait for the SLEEP signal to be low for tSLEEPOEH=5us and then pull up the OE signal, which needs to be high for tRDEN=20us to exit sleep mode (see the subsequent timing of entering and exiting sleep mode).

[0104] The above external interrupt module interface is described in detail as follows Figure 5 shown.

[0105] The key signals of the external interrupt module interface inside the eFlash controller are explained as shown in Table 4 below:

[0106] Table 4 Input and output interface signals of external interrupt module in eFlash controller

[0107]

[0108] In this embodiment, the control module is provided with an erase operation timing corresponding to the erase operation, a write operation timing corresponding to the write operation, and a read operation timing corresponding to the read operation; the erase operation timing, the write operation timing and the read operation timing have an operation time configured by a register, and the operation time includes a setup time and / or a hold time of the corresponding operation; the operation time corresponding to the erase operation is different from the operation time corresponding to the write operation and the operation time corresponding to the read operation.

[0109] Since a certain timing needs to be set for reading, writing and erasing data, and the operation time corresponding to the erasing operation, the operation time corresponding to the writing operation, and the operation time corresponding to the reading operation in this embodiment are all different, this embodiment can realize the time required to establish and maintain each operation timing dynamically by configuring the register at any time according to the working clock frequency of different projects, thereby achieving the purpose of multiplexing different projects. Because in digital circuit design, once the circuit code is changed, a lot of verification work is required, and there is a risk of bugs. However, this embodiment changes the time required for each operation timing by configuring the register, and different project reuse can be achieved without changing the circuit code.

[0110] Specifically, in this embodiment, the control module is provided with an erase operation sequence corresponding to the erase operation, a write operation sequence corresponding to the write operation, and a read operation sequence corresponding to the read operation; the erase operation sequence has an erase operation setup time and / or an erase operation hold time configured by a register, the write operation sequence has a write operation setup time and / or a write operation hold time configured by a register, and the read operation sequence has a read operation setup time and / or a read operation hold time configured by a register. The erase operation setup time is different from the write operation setup time and the read operation setup time, and / or the erase operation hold time is different from the write operation hold time and the read operation hold time, so that the operation time corresponding to the erase operation, the operation time corresponding to the write operation, and the operation time corresponding to the read operation are obviously different, which facilitates the system to distinguish according to each operation sequence.

[0111] In this embodiment, the read operation timing is designed as follows: Figure 6 As shown, it should be noted that:

[0112] 1. During the read operation, the CS (chip select) pin remains high. At the same time, PROG (write cycle), SERA (page erase), MASE (chip erase), and NVSTR (non-volatile operation) remain low and maintain this state until the operation is completed.

[0113] 2. For a successful read operation, AE_RESET must remain low.

[0114] 3. IFREN (information block enable) determines whether the main storage area or the information block is to be accessed. No glitches are allowed on IFREN during the entire operation (from AE raising to data reading).

[0115] 4. To select the word, refer to the page address table.

[0116] 5. In order for the macro to take effect, the CS pin should be kept high; if the CS pin is not high, the macro will ignore any changes in the control pins and address.

[0117] 6. AE (address enable) access time refers to the delay from AE stabilization to output data validity.

[0118] In this embodiment, the write operation timing is designed as follows: Figure 7 As shown, it should be noted that:

[0119] 1. During the write operation, CS is high, OE, SERA and MASE are low, and this state is maintained until the operation is completed.

[0120] 2. IFREN[15:0] determines whether the data is written to the main block or the information block. No glitches are allowed during the entire operation (from AE rising to TBIT falling) of IFREN.

[0121] 3. In the information block write operation, ADDR[5:0] and AP[1:0] are used to select the word to be written. When the IFREN value is high, ADDR[12:6] should be 0.

[0122] 4. TBIT will be controlled by the internal timer of the macro to indicate the status of the erase / write process.

[0123] In this embodiment, the page erase operation timing is designed as follows: Figure 8 As shown, the following points should be noted in the page erase operation:

[0124] 1. During the page erase operation, CS is high, OE, PROG and MASE are low, and this state is maintained until the operation is completed.

[0125] 2. IFREN[15:0] determines whether the data is written to the main block or the information block. No glitches are allowed during the entire operation (from AE rising to TBIT falling) of IFREN.

[0126] 3. In the information block write operation, ADDR[5:0] and AP[1:0] are used to select the word to be written. When the IFREN value is high, ADDR[12:6] should be 0.

[0127] 4. TBIT will be controlled by the internal timer of the macro to indicate the status of the erase / write process.

[0128] In this embodiment, the chip erase operation timing is designed as follows: Fig. 9 As shown, the following points should be noted when performing chip erase operation:

[0129] 1. During the chip erase operation, CS is high, OE, PROG and SERA are low, and this state is maintained until the operation is completed.

[0130] 2. The IFREN pin determines whether the main block is erased together with the information block in the macro erase operation. For specific behavior, refer to the truth table of IFREN. During the entire operation (from the rising edge of AE to the falling edge of TBIT), no glitches are allowed on IFREN to ensure the accuracy of the operation.

[0131] 3. TBIT will be controlled by the internal timer of the macro to indicate the erase / write process.

[0132] In this embodiment, the timing design of the write abort operation and the erase abort operation is as follows: Fig.10As shown, the write / erase abort operation needs to pay attention to:

[0133] 1. When the RESETB signal is inserted (i.e. becomes low level) after the power is normal, the macro of the Flash memory will terminate the currently executing Program (write) or Erase (erase) operation. However, this termination of the operation has no effect on the Read (read) operation, that is, the read operation can continue normally and is not affected by the RESETB signal.

[0134] 2. When the write / erase operation is aborted by the RESETB signal, the data of the selected address or page will not remain in the previous state, but will enter an indeterminate state. This means that after the RESETB signal is triggered, the data content of these addresses or pages will become uncertain and may not be directly read or used.

[0135] Therefore, when operating the Flash memory, you need to carefully handle the RESETB signal to avoid unnecessary data loss or damage. At the same time, you also need to consider the abnormal situations that may occur during data writing or erasing, and take corresponding error handling measures to protect the integrity and security of the data.

[0136] In this embodiment, the timing of entering and exiting the sleep mode (CS=1, SLEEP=1) is designed as follows Fig.11 As shown in Figure 1, the timing of entering sleep mode and exiting sleep mode (CS=0) is designed as follows: Fig.12 As shown, the power-on timing design is as follows Fig.13 As shown. From the above content, it can be seen that the various operations of this embodiment can be distinguished by their different operation times, and the operation time is set by the register configuration. Therefore, this embodiment can dynamically change the time required for establishment and maintenance by configuring the register, so as to achieve the purpose of multiplexing different projects.

[0137] The register overview of the eFlash controller in this embodiment is shown in the following table:

[0138]

[0139] Among them, the CFG_CR register is specifically:

[0140] Reset value: 0x0

[0141] Offset address: 0x00

[0142]

[0143] The specific contents of the CFG_CR1 register are:

[0144] Reset value: 0x0

[0145] Offset address: 0x04

[0146]

[0147] The CFG_PGM_DIS register is as follows:

[0148] Reset value: 0x0

[0149] Offset address: 0x08

[0150]

[0151] The CFG_PGI_DIS register is specifically:

[0152] Reset value: 0x0

[0153] Offset address: 0x0C

[0154]

[0155] The CFG_RDM_DIS register is specifically:

[0156] Reset value: 0x0

[0157] Offset address: 0x10

[0158]

[0159] The CFG_RDI_DIS register is specifically:

[0160] Reset value: 0x0

[0161] Offset address: 0x14

[0162]

[0163] The CFG_ERM_DIS register is specifically:

[0164] Reset value: 0x0

[0165] Offset address: 0x18

[0166]

[0167] The CFG_ERI_DIS register is as follows:

[0168] Reset value: 0x0

[0169] Offset address: 0x1C

[0170]

[0171] The CFG_INTR register is specifically:

[0172] Reset value: 0x0

[0173] Offset address: 0x20

[0174]

[0175] The CFG_INTR_CLR register is specifically:

[0176] Reset value: 0x0

[0177] Offset address: 0x24

[0178]

[0179] The CFG_ST register is as follows:

[0180] Reset value: 0x0

[0181] Offset address: 0x28

[0182]

[0183] The specific CFG_KEY1 register is:

[0184] Reset value: 0x0

[0185] Offset address: 0x64

[0186]

[0187] The specific CFG_KEY2 register is:

[0188] Reset value: 0x0

[0189] Offset address: 0x68

[0190]

[0191] The CFG_tRDEN register is specifically:

[0192] Reset value: 0x0

[0193] Offset address: 0x6C

[0194]

[0195] The specific CFG_tRDOEH register is:

[0196] Reset value: 0x0

[0197] Offset address: 0x70

[0198]

[0199] The CFG_tEXTRD register is specifically:

[0200] Reset value: 0x0

[0201] Offset address: 0x74

[0202]

[0203] The CFG_tPROG register is specifically:

[0204] Reset value: 0x0

[0205] Offset address: 0x78

[0206]

[0207] The CFG_tSER register is specifically:

[0208] Reset value: 0x0

[0209] Offset address: 0x7C

[0210]

[0211] The CFG_tMER register is specifically:

[0212] Reset value: 0x0

[0213] Offset address: 0x80

[0214]

[0215] The CFG_tSLEEP register is as follows:

[0216] Reset value: 0x0

[0217] Offset address: 0x84

[0218]

[0219] The CFG_tSLEEPLOEH register is specifically:

[0220] Reset value: 0x0

[0221] Offset address: 0x88

[0222]

[0223] The CFG_tOELSLEEPH register is as follows:

[0224] Reset value: 0x0

[0225] Offset address: 0x8C

[0226]

[0227] In this embodiment, the specific operation application process of the eFlash controller for each operation is as follows:

[0228] Read Operation:

[0229] After the system is powered on, the flash can be read directly. The read operation is enabled by default. CR.mode is configured to 0 to enable the read operation.

[0230] Write Operation:

[0231] Flash memory only supports writing from 1 to 0, not from 0 to 1. If you need to write from 0 to 1, you must perform an erase operation.

[0232] Write operation process:

[0233] 1) Set CR.mode to 01;

[0234] 2) Write an address;

[0235] 3) Set CR.mode to 00;

[0236] 4) Read ST.BUSY until ST.BUSY is 0, which means the write operation is completed.

[0237] Page Erase:

[0238] 1) Set CR.mode to 02;

[0239] 2) Write the first address of the page to be erased to 0;

[0240] 3) Set CR.mode to 0;

[0241] 4) Read ST.BUSY. If ST.BUSY is 0, it means the write operation is completed.

[0242] Block Erase:

[0243] 1) Set CR.mode to 03;

[0244] 2) Write any address;

[0245] 3) Set CR.mode to 0;

[0246] 4) Read ST.BUSY. If ST.BUSY is 0, it means the write operation is completed.

[0247] Main storage area write protection:

[0248] 1) Configure KEY_1 / KEY_2 and enable the protection mechanism;

[0249] 2) Configure the PGM_DIS register and select the page to be protected.

[0250] If a write operation occurs on a protected page, the write operation will not succeed and an interrupt will be generated.

[0251] Information storage area write protection:

[0252] 1) Configure KEY_1 / KEY_2 and enable the protection mechanism;

[0253] 2) Configure the PGI_DIS register and select the page to be protected.

[0254] If a write operation occurs on a protected page, the write operation will not succeed and an interrupt will be generated.

[0255] Main storage area read protection:

[0256] 1) Configure KEY_1 / KEY_2 and enable the protection mechanism;

[0257] 2) Configure the RDM_DIS register and select the page to be protected.

[0258] Page0~page3 cannot be set to read protection; if a read operation occurs on the protected page, the value in the flash will not be returned and an interrupt will be generated.

[0259] Information storage area read protection:

[0260] 1) Configure KEY_1 / KEY_2 and enable the protection mechanism;

[0261] 2) Configure the RDI_DIS register and select the page to be protected.

[0262] Main storage area wipe protection:

[0263] 1) Configure KEY_1 / KEY_2 and enable the protection mechanism;

[0264] 2) Configure the ERM_DIS register and select the page to be protected.

[0265] Information storage area wipe protection:

[0266] 1) Configure KEY_1 / KEY_2 and enable the protection mechanism;

[0267] 2) Configure the ERI_DIS register and select the page to be protected.

[0268] Embodiment 2

[0269] Different from the above-mentioned invention embodiment, the present invention embodiment further introduces the electronic device on the basis of the above-mentioned invention embodiment. The specific structure of the electronic device can correspond to the structure of the above-mentioned controller.

[0270] In an embodiment of the present invention, the electronic device includes an eFlash controller based on the AHB bus as described in the above embodiment. The specific structure of the controller has been described in detail in the above invention embodiment, and will not be repeated here. The electronic device provided in this embodiment is provided with the above eFlash controller, so the performance of the electronic device is higher and the data security is higher.

[0271] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0272] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0273] The above is a detailed introduction to an eFlash controller and electronic device based on the AHB bus provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. An eFlash controller based on AHB bus, characterized in that: include: A control module and a storage module, wherein the control module is connected to the AHB bus, and the control module is connected to the storage module; The storage space in the storage module includes multiple protection zones, each of which includes at least one data page; the protection zones have corresponding write protection bits; when the write protection bits indicate that the corresponding data page in the protection zone is write-protected, the control module is used to invalidate at least the erase operation and / or write operation performed on the write-protected data page.

2. The controller according to claim 1, characterized in that: The control module is specifically used for: The erase operation and / or write operation of the target including the write-protected data page is completely invalidated.

3. The controller according to claim 2, characterized in that: The control module is also used for: After the invalid erase operation and / or write operation, an interrupt signal based on hardware triggering is generated, and the interrupt signal is sent to the processor through the AHB bus.

4. The controller according to claim 1, characterized in that: The data page is provided with a corresponding read protection bit. When the write protection bit indicates that the corresponding data page is read protected, the control module is used to invalidate the read operation of the corresponding read protected data page.

5. The controller according to claim 4, characterized in that: The control module is also used for: After the invalid read operation, an interrupt signal based on hardware triggering is generated, and the interrupt signal is sent to the processor through the AHB bus.

6. The controller according to claim 1, characterized in that: The storage space includes a main storage area and an information block. Each protection area in the main storage area includes four data pages, and each protection area in the information block includes one data page.

7. The controller according to claim 1, characterized in that: The control module is provided with an erase operation timing corresponding to the erase operation, a write operation timing corresponding to the write operation, and a read operation timing corresponding to the read operation; The erase operation timing, the write operation timing and the read operation timing have operation times configured by registers, and the operation times include setup time and / or hold time of corresponding operations; The operation time corresponding to the erase operation, the operation time corresponding to the write operation, and the operation time corresponding to the read operation are all different.

8. The controller according to claim 1, characterized in that: The control module is provided with an operation state machine, the operation state machine includes a plurality of state paths, and the state paths correspond one-to-one to the types of operations executable by the storage module; The control module is used for: The corresponding state path is executed according to the received instruction, and a control signal of the corresponding operation type is generated and sent to the storage module, so that the storage module executes the corresponding operation.

9. The controller according to claim 1, characterized in that: It also includes an external interrupt module, through which the control module is connected to the storage module; the external interrupt module is connected to the sleep signal line of the processor.

10. An electronic device, characterized in that: It comprises an AHB bus-based eFlash controller as claimed in any one of claims 1 to 9.

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