Display panel and driving method

Abstract

The application discloses a display panel and a driving method. The display panel comprises multiple rows of pixels, receives data signals output by data output channels on a data driving chip for driving, and each row of pixels is divided into multiple pixel groups. Each pixel group comprises a first pixel, a second pixel, a third pixel and a fourth pixel. The first pixel and the second pixel are connected with an Nth row of scanning lines, and the third pixel and the fourth pixel are connected with an N+1th row of scanning lines. An Mth column of data lines connected with the first pixel and an M+2th column of data lines connected with the third pixel are connected with an Sth data channel on the data driving chip, and an M+1th column of data lines connected with the second pixel and an M+3th column of data lines connected with the fourth pixel are connected with an S+1th data channel on the data driving chip. Two data lines are connected with each data channel, and the two data lines are connected with two pixels controlled by two rows of scanning lines. The application not only further saves the cost of the data driving chip, but also improves the shaking lines caused by polarity inversion.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and driving method. Background Technology

[0002] Liquid Crystal Displays (LCDs) have many advantages such as thinness, energy saving, and no radiation, and have been widely used. In the development of large-size and high-refresh-rate display panels, Dual Line Gate (DLG) technology has attracted attention. DLG technology is also known as frequency doubling refresh technology. Its principle is that the panel's GDL circuit simultaneously opens two rows of scan lines, and the two rows input the same scan signal. In this mode, it is equivalent to reducing the number of pixels in the vertical display by half. Without changing the original hardware and chip computing power, the refresh rate can be doubled.

[0003] In the LCD display industry, DRD (Double Row Driving), or 2G1D design, is increasingly used because it can save on the number of data driver chips and chip-on-film (COF) films. It opens a complete row of pixels through two rows of gate lines, thus halving the number of data lines (sources) and doubling the number of gate lines, thereby saving source IC costs. However, when VCOM is not under optimal conditions, the display panel will have different brightness of positive and negative pixels due to the asymmetry of pixel polarity, resulting in head-shaking patterns and affecting the display effect. Summary of the Invention

[0004] The purpose of this application is to provide a display panel and driving method that can reduce the number of data driver chips, lower the cost of the display panel, and improve the display panel and driving method for removing head-shaking patterns.

[0005] This application discloses a display panel comprising multiple rows of pixels, driven by data signals output from a data output channel on a data driver chip. Each row of pixels is divided into multiple pixel groups, each pixel group comprising a first pixel, a second pixel, a third pixel, and a fourth pixel. The first pixel and the second pixel are connected to the Nth row of scan lines, and the third pixel and the fourth pixel are connected to the N+1th row of scan lines. The Mth column of data lines connected to the first pixel and the M+2th column of data lines connected to the third pixel are connected to the Sth data channel on the data driver chip, and the M+1th column of data lines connected to the second pixel and the M+3th column of data lines connected to the fourth pixel are connected to the S+1th data channel on the data driver chip.

[0006] Where N, M, and T are natural numbers greater than or equal to 1.

[0007] Optionally, along the extension direction of the scan line, the first pixel, the second pixel, the third pixel, and the fourth pixel are arranged sequentially. The first pixel and the third pixel have the same polarity, the second pixel and the fourth pixel have the same polarity, and the first pixel and the second pixel have different polarities. The Mth column data line connected to the first pixel and the M+2th column data line connected to the third pixel are arranged on the same layer. The M+1th column data line connected to the second pixel and the M+3th column data line connected to the fourth pixel are arranged on the same layer. The Mth column data line connected to the first pixel and the M+1th column data line connected to the second pixel are arranged on different layers. The Mth column data line is connected to the Sth data channel through a first fan-out trace, and the M+2th column data line is connected to the S+1th data channel through a second fan-out trace.

[0008] Wherein, the length of the first fan-out trace is less than the length of the second fan-out trace, the cross-sectional area of ​​the first fan-out trace is less than the cross-sectional area of ​​the second fan-out trace, and the resistance values ​​of the first fan-out trace and the second fan-out trace are equal.

[0009] Optionally, the Sth data channel and the (S+1)th data channel are stacked on the data driver chip, and the Sth data channel is disposed on the (S+1)th data channel; the Sth data channel and the Mth column data line have the same height, and the (S+1)th data channel and the (M+1)th column data line have the same height.

[0010] Optionally, between two adjacent rows of scan lines, the first pixel, the second pixel, the third pixel, and the fourth pixel are arranged in two rows and two columns. Along the extension direction of the data lines, the first pixel and the third pixel are arranged sequentially, and the second pixel and the third pixel are arranged sequentially. The M+2th column data line is disposed between the Mth column data line and the M+1th column data line, and the M+1th column data line is disposed between the M+2th column data line and the M+3th column data line. The Mth column data line, the M+1th column data line, the M+2th column data line, and the M+3th column data line are disposed on the same layer.

[0011] Optionally, the first pixel and the second pixel are primary pixels, and the third pixel and the fourth pixel are secondary pixels. The transmittance of the first pixel is greater than that of the third pixel, and the transmittance of the second pixel is greater than that of the fourth pixel. The first common line corresponding to the first pixel and the second pixel receives a first common voltage level, and the second common line corresponding to the third pixel and the fourth pixel receives a second common voltage level. When the gray levels of the first pixel and the third pixel are the same, the voltages of the first common voltage level and the second common voltage level are different.

[0012] Optionally, the display panel includes a refresh rate adjustment circuit and a gate driving circuit. The gate driving circuit includes a first gate driving unit and a second gate driving unit. The first gate driving unit is connected to the input terminal of the Nth scan line, and the second gate driving unit is connected to the input terminal of the N+1th scan line. The refresh rate adjustment module controls the gate driving signals of the first gate driving unit and the second gate driving unit to be output simultaneously or time-divisionally to the input terminals of the Nth scan line and the N+1th scan line to achieve different refresh rates.

[0013] Optionally, the display panel further includes a first compensation circuit, a second compensation circuit, and a screen detection module. The input terminal of the first compensation circuit is connected between the first gate driver and the input terminal of the Nth row of scan lines, and the output terminal is connected to the screen detection module. The input terminal of the second compensation circuit is connected between the second gate driver and the input terminal of the N+1th row of scan lines, and the output terminal is connected to the screen detection module.

[0014] The image detection module generates a first compensation voltage and a second compensation voltage based on the brightness level, which are then input to the first compensation circuit and the second compensation circuit, respectively. The magnitudes of the first compensation voltage and the second compensation voltage are different.

[0015] This application also discloses a driving method for driving any of the display panels described above, the driving method comprising:

[0016] The corresponding gate drive signals are generated and output to the first pixel and the second pixel respectively, which are connected to the Nth row of scan lines. The third pixel and the fourth pixel are connected to the N+1th row of scan lines.

[0017] The corresponding data driving signals are generated and output to the Mth column data line connected to the first pixel and the M+2th column data line connected to the third pixel through the corresponding Sth data channel, respectively. The corresponding S+1th data channel is simultaneously output to the M+1th column data line connected to the second pixel and the M+3th column data line connected to the fourth pixel.

[0018] Where N, M, and T are natural numbers greater than or equal to 1.

[0019] Optionally, the first pixel, second pixel, third pixel, and fourth pixel are arranged in two rows and two columns. Along the extension direction of the data line, the first pixel and third pixel are arranged sequentially, and the second pixel and fourth pixel are arranged sequentially. Along the extension direction of the scan line, the first pixel and second pixel are arranged sequentially, and the third pixel and fourth pixel are arranged sequentially. The first common line corresponding to the first pixel and second pixel receives a first common voltage level, and the second common line corresponding to the third pixel and fourth pixel receives a second common voltage level. The driving method further includes the step:

[0020] The grayscale values ​​of the first pixel and the third pixel are detected, and it is determined whether the grayscale values ​​are the same. If they are the same, the first common level and the second common level with different voltage values ​​are output to the first common line and the second common line respectively. If they are different, the first common level and the second common level with the same voltage value are output to the first common line and the second common line respectively.

[0021] Optionally, the display panel includes a refresh rate adjustment circuit, a gate driving circuit, a first compensation circuit, a second compensation circuit, and a screen detection module. The step of generating corresponding gate driving signals and outputting them to the first pixel and the second pixel to connect to the Nth row of scan lines, and the third pixel and the fourth pixel to connect to the N+1th row of scan lines, includes:

[0022] The system detects the next frame of the image and generates a first compensation voltage and a second compensation voltage based on the brightness level to compensate the gate drive signals of the first gate drive unit and the second gate drive unit.

[0023] The display mode of the next frame is detected. If it is a frequency multiplication display, the gate drive signals of the first gate drive unit and the second gate drive unit are simultaneously output to the input terminals of the Nth and N+1th scan lines. If it is a normal display, the gate drive signals of the first and second gate drive units are output to the input terminals of the Nth and N+1th scan lines in a time-division manner.

[0024] Compared to display panels using the DRD architecture, this application further improves upon the DRD architecture by dividing each row of pixels into multiple pixel groups. Each pixel group includes a first pixel, a second pixel, a third pixel, and a fourth pixel. The first and second pixels are connected to the Nth row of scan lines, and the third and fourth pixels are connected to the N+1th row of scan lines. The Mth column of data lines connected to the first pixel and the M+2th column of data lines connected to the third pixel are connected to the Sth data channel on the data driver chip, and the M+1th column of data lines connected to the second pixel and the M+3th column of data lines connected to the fourth pixel are connected to the S+1th data channel on the data driver chip. This effectively increases the number of gate lines by 6 times, and the data driver chip only requires one-third of that used in DRD architecture display panels. The new pixel architecture not only further reduces the cost of the data driver chip but also avoids the appearance of head-shaking patterns when polarity is reversed. Attached Figure Description

[0025] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0026] Figure 1 This is a schematic diagram of an exemplary pixel structure (1G1D) of this application;

[0027] Figure 2 This is a schematic diagram of an exemplary pixel structure (2G1D) of this application;

[0028] Figure 3 This is a schematic diagram of an exemplary pixel structure (TRD) of this application;

[0029] Figure 4 This is a schematic diagram of the structure of the display panel according to the first embodiment of this application;

[0030] Figure 5 This is a schematic diagram of the display panel structure according to the second embodiment of this application;

[0031] Figure 6 This is a schematic diagram of the structure of another display panel according to the second embodiment of this application;

[0032] Figure 7 This is a schematic diagram of the structure of the display panel according to the third embodiment of this application;

[0033] Figure 8 This is a schematic diagram of the structure of the display panel according to the fourth embodiment of this application;

[0034] Figure 9 This is a schematic flowchart of the driving method according to the fifth embodiment of this application;

[0035] Figure 10 This is a schematic flowchart of the driving method according to the sixth embodiment of this application;

[0036] Figure 11 This is a schematic flowchart of the driving method according to the seventh embodiment of this application.

[0037] Among them, 100 is the display panel; 110 is the pixel; 120 is the pixel group; 121 is the first pixel; 122 is the second pixel; 123 is the third pixel; 124 is the fourth pixel; 130 is the scan line; 140 is the data line; 150 is the fan-out area; 151 is the first fan-out trace; 152 is the second fan-out trace; 161 is the first common line; 162 is the second common line; 170 is the refresh rate adjustment circuit; 180 is the gate drive circuit; 191 is the first compensation circuit; 192 is the second compensation circuit; 200 is the data driver chip; 210 is the data channel; and 220 is the screen detection module. Detailed Implementation

[0038] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0039] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0040] refer to Figures 1 to 3 As shown, the conventional display panel architecture is 1G1D (such as...). Figure 1 ) Improved to 2G1D (such as Figure 2 This refers to the DRD (double rate driving) architecture, where G1 is the first scan line, G2 is the second scan line, ..., G6 is the sixth scan line, ..., Gn is the Nth scan line, D1 is the first column data line, D2 is the second column data line, ..., D7 is the seventh column data line, and Dn is the Nth column data line. The 1G1D architecture can open a complete row of pixels using two rows of gates, thus halving the source lines and doubling the gate lines. The increased gate lines can be implemented using a GOA circuit designed on the side in gate-less models, thereby saving source IC costs. Figure 2 The diagram shows the commonly used DRD architecture with subpixels arranged in long and short segments; where G represents scan lines and D represents data lines. To further reduce costs, panel manufacturers also offer TRD architecture products (tri-gate, such as...) that are cheaper than 2G1D. Figure 3 (As shown); Compared to the normal 1G1D, the TRD reduces the number of data lines to 1 / 3 of the 1G1D and increases the number of gate lines to 3 times that of the 1G1D. Similarly, the increased number of gate lines can be achieved by designing the gate drive circuit (GOA) on the side in the gate-less model, further reducing the cost of the data drive chip (source).

[0041] refer to Figure 4 As shown, as a first embodiment of this application, a display panel 100 is disclosed. The display panel 100 includes multiple rows of pixels 110, which are driven by data signals output from the data output channel on the data driver chip 200. The characteristic feature is that each row of pixels 110 is divided into multiple pixel groups 120, and each pixel group 120 includes a first pixel 121, a second pixel 122, a third pixel 123, and a fourth pixel 124; the first pixel 121 and the second pixel 122 are connected to the Nth scan line 130, and the third pixel 123 and the fourth pixel 124 are connected to the Nth scan line 130. Pixel 124 is connected to the (N+1)th row scan line 130; the first pixel 121 is connected to the Mth column data line 140 and the third pixel 123 is connected to the (M+2)th column data line 140, which are connected to the Sth data channel 210 on the data driver chip 200; the second pixel 122 is connected to the (M+1)th column data line 140 and the fourth pixel 124 is connected to the (M+3)th column data line 140, which are connected to the (S+1)th data channel 210 on the data driver chip 200; where N, M, and T are natural numbers greater than or equal to 1.

[0042] This application is actually an architecture combining DRD and TRD, source The COF (Chip-on-Foil) is reduced to 1 / 6, and the gate lines are increased to 6 times. A row of pixels 110 is divided into multiple pixel groups 120. Each pixel group 120 includes four pixels 110: a first pixel 121, a second pixel 122, a third pixel 123, and a fourth pixel 124. The first pixel 121 and the second pixel 122 are connected to the Nth scan line 130, and the third pixel 123 and the fourth pixel 124 are connected to the N+1th scan line 130. The Mth column data line 140 connected to the first pixel 121 and the M+2th column data line 140 connected to the third pixel 123 are connected to the Sth data channel 210 on the data driver chip 200. The M+1th column data line 140 connected to the second pixel 122 and the M+3th column data line 140 connected to the fourth pixel 124 are connected to the S+1th data channel 210 on the data driver chip 200. Taking UHD (3840*2160 resolution) as an example, assuming a 960ch source... COF: The 1G1D architecture requires 3840*3 / 960=12 source COFs, the 2G1D architecture requires 3840*3 / 2 / 960=6 source COFs, and the TRD architecture requires 3840*3 / 3 / 960=4 source COFs; combining DRD and TRD produces... Figure 4 The in-plane architecture shown, taking UHD as an example, only requires 3840*3 / 3 / 2 / 960=2 source COFs. The new DRD TRD architecture further saves the cost of source COF. Moreover, the data drive signals from the same data channel 210 enter two pixels 110 controlled by different scan lines 130 respectively, avoiding data drive signal disorder. This prevents the display panel 100 from having different brightness of positive and negative polarity pixels 110 due to the asymmetry of positive and negative polarity when the common voltage VCOM is under non-optimal conditions, thus preventing the formation of head-shaking patterns.

[0043] like Figure 5 As shown, the second embodiment of this application is a further refinement and improvement of the first embodiment described above. (Refer to...) Figure 5 and Figure 6As shown, along the extension direction of the scan line 130, the first pixel 121, the second pixel 122, the third pixel 123, and the fourth pixel 124 are arranged sequentially. The Mth column data line 140 connected to the first pixel 121 and the M+2th column data line 140 connected to the third pixel 123 are arranged on the same layer. The M+1th column data line 140 connected to the second pixel 122 and the M+3th column data line 140 connected to the fourth pixel 124 are arranged on the same layer. The M-column data line 140 and the M+1-column data line 140 connected to the second pixel 122 are disposed on different layers; the M-column data line 140 is connected to the S-th data channel 210 through a first fan-out trace 151, and the M+2-column data line 140 is connected to the S+1-th data channel 210 through a second fan-out trace 152; wherein, the length of the first fan-out trace 151 is less than the length of the second fan-out trace 152, and the cross-sectional area of ​​the first fan-out trace 151 is less than that of the S+1-th data channel 210. The cross-sectional area of ​​the two outgoing traces 152, the resistance of the first outgoing trace 151 and the resistance of the second outgoing trace 152 are equal; taking the first column of pixels 110 to the fourth column of pixels 110 as an example, the first row of pixels 110 are red pixels 110, the second row of pixels 110 are green pixels 110, the third row of pixels 110 are blue pixels 110, the first pixel 121, the second pixel 122, the third pixel 123 and the fourth pixel 124 are all red pixels 110, the first row of the first column of pixels 110 That is, the first pixel 121 connects the first column data line 140D1 and the first row scan line 130G1; the first row, second column pixel 110, i.e., the second pixel 122, connects the second column data line 140D2 and the first row scan line 130G1; the first row, third column pixel 110, i.e., the third pixel 123, connects the third column data line 140D3 and the second row scan line 130G2; the first row, fourth column pixel 110, i.e., the fourth pixel 124, connects the fourth column data line 140D4 and the second row scan line 130G2.

[0044] In this embodiment, the four pixels 110 in the pixel group 120 are arranged sequentially, with odd-numbered columns of pixels 110 connected to the same data channel 210, and even-numbered columns of pixels 110 connected to the same data channel 210. To avoid crossing lines, the odd-numbered and even-numbered columns of data lines 140 are arranged in layers. The M-th column data line 140 connected to the first pixel 121 and the M+2-th column data line 140 connected to the third pixel 123 are arranged in the same layer. The M+1-th column data line 140 connected to the second pixel 122 and the M+3-th column data line 140 connected to the fourth pixel 124 are arranged in the same layer. The data lines 140 are set on the same layer, while the M-th column data line 140 connected to the first pixel 121 and the M+1-th column data line 140 connected to the second pixel 122 are set on different layers. This avoids the need for the traces from the S-th data channel 210 to bypass the data line 140 connected to the S+1-th data channel 210 when they are set on the same layer, which would increase the width of the fan-out area 150. In addition, considering that the traces in the fan-out area 150 will affect the transmission of data signals, in order to avoid different values ​​of data signal loss, the resistance values ​​of the first fan-out trace 151 and the second fan-out trace 152 are made equal.

[0045] The first pixel 121 and the third pixel 123 have the same polarity, the second pixel 122 and the fourth pixel 124 have the same polarity, and the first pixel 121 and the second pixel 122 have different polarities. When VCOM is not optimal, the display panel 100 will also have different brightness levels for positive and negative pixels 110 due to the asymmetry of the positive and negative polarities of the pixels 110. For example, when VCOM is large, all positive pixels 110 in columns D1D3D5D7 will be darker, and all negative pixels 110 in columns D2D4D6D8 will be brighter. However, because the positive and negative polarities alternate, the head-shaking pattern during column inversion is slightly reduced, thus improving the head-shaking pattern phenomenon.

[0046] Furthermore, such as Figure 6 As shown, considering that the data line 140 is set in two layers, the thickness of the corresponding display panel 100 will also increase. In addition, the number of data channels 210 is relatively large. If they are arranged horizontally, the length of multiple data chips will increase, which will affect the aesthetics. Therefore, the data channels 210 are set in layers corresponding to the data lines 140 of different layers. Specifically, the Sth data channel 210 and the S+1th data channel 210 are stacked on the data driver chip 200. The Sth data channel 210 is set on the S+1th data channel 210. The Sth data channel 210 and the Mth column data line 140 have the same height. The S+1th data channel 210 and the M+1th column data line 140 have the same height.

[0047] like Figure 7As shown, in the third embodiment of this application, unlike the above embodiments, as another DRDTRD architecture, between two adjacent scan lines 130, the first pixel 121, the second pixel 122, the third pixel 123, and the fourth pixel 124 are arranged in two rows and two columns. Along the extension direction of the data line 140, the first pixel 121 and the third pixel 123 are arranged sequentially, and the second pixel 122 and the fourth pixel 124 are arranged sequentially. Along the extension direction of the scan line 130, the first pixel 121, the second pixel 122, the third pixel 123, and the fourth pixel 124 are arranged sequentially. Two pixels 122 are arranged in sequence, the third pixel 123 and the fourth pixel 124 are arranged in sequence, the (M+2)th column data line 140 is disposed between the Mth column data line 140 and the (M+1)th column data line 140, and the (M+1)th column data line 140 is disposed between the (M+2)th column data line 140 and the (M+3)th column data line 140; the Mth column data line 140, the (M+1)th column data line 140, the (M+2)th column data line 140 and the (M+3)th column data line 140 are disposed on the same layer.

[0048] Furthermore, the DRD TRD architecture in this embodiment can also improve color shift. The first pixel 121 and the second pixel 122 are main pixels 110, and the third pixel 123 and the fourth pixel 124 are auxiliary pixels 110. The light transmittance of the first pixel 121 is greater than that of the third pixel 123, and the light transmittance of the second pixel 122 is greater than that of the fourth pixel 124. When the pixels 110 in the pixel group 120 emit light, the contrast between the main pixels 110 and the auxiliary pixels 110, which are staggered and have different brightness levels, is large. This can solve the problem of color shift that occurs in the display panel 100 using the pixel 110 structure at large viewing angles, thereby improving its display effect. Meanwhile, for a single pixel 110 unit, the four sub-pixels 110 are arranged in two rows and two columns, which makes the sub-pixels 110 driven by the same data voltage more concentrated, thereby improving their display effect. In addition, the first common line 161 corresponding to the first pixel 121 and the second pixel 122 receives the first common level, and the second common line 162 corresponding to the third pixel 123 and the fourth pixel 124 receives the second common level. When the gray levels of the first pixel 121 and the third pixel 123 are the same, the voltages of the first common level and the second common level are different. By controlling the main pixel 110 and the auxiliary pixel 110 independently, the brightness of the corresponding main / auxiliary pixel 110 can be changed by controlling the high and low switching of the common level of the common line, without the need to process the data signal. Even when the data signals of the main pixel 110 and the auxiliary pixel 110 are the same and are at the same gray level, the difference in the common level signal can automatically realize the difference in brightness between the main pixel 110 and the auxiliary pixel 110, further improving color shift.

[0049] like Figure 8As shown, this fourth embodiment of the present application is a further refinement and improvement of any of the above embodiments. The display panel 100 includes a refresh rate adjustment circuit 170 and a gate driving circuit 180. The gate driving circuit 180 includes a first gate driving unit and a second gate driving unit. The first gate driving unit is connected to the input terminal of the Nth row of scan lines 130, and the second gate driving unit is connected to the input terminal of the N+1th row of scan lines 130. The refresh rate adjustment module controls the gate driving signals of the first gate driving unit and the second gate driving unit to be output simultaneously or time-divisionally to the input terminals of the Nth row of scan lines 130 and the N+1th row of scan lines 130, so as to realize the display of different refresh rates. The refresh rate adjustment circuit 170 is set before the gate driving circuit 180. A row of pixels 110 in the two rows of scan lines 130 can be displayed simultaneously or time-divisionally. When displayed simultaneously, it is equivalent to reducing the scanning time of a frame by half, thereby improving the refresh rate.

[0050] Furthermore, the display panel 100 also includes a first compensation circuit 191, a second compensation circuit 192, and a screen detection module 220. The input terminal of the first compensation circuit 191 is connected between the first gate driver and the input terminal of the Nth scan line 130, and the output terminal is connected to the screen detection module 220. The input terminal of the second compensation circuit 192 is connected between the second gate driver and the input terminal of the (N+1)th scan line 130, and the output terminal is connected to the screen detection module 220. The screen detection module 220 generates a corresponding first compensation voltage and a second compensation voltage according to the brightness level and inputs them to the first compensation circuit 191 and the second compensation circuit 192, respectively. The magnitudes of the first compensation voltage and the second compensation voltage are different.

[0051] When the refresh rate is doubled, i.e., in frequency multiplication mode, the first compensation circuit 191 and the second compensation circuit 192 are turned on. The first compensation voltage and the second compensation voltage corresponding to the two scan lines 130 with the same scan signal are different. By using negative compensation through the first compensation voltage and the second compensation voltage, i.e., pulling down the voltage in the gate drive signal, different scan signal waveforms are generated and output to the scan line 130. Since the two scan signal waveforms are different, the turn-on voltage of the thin film crystal of the sub-pixel 110 is different, so that the gate opening degree of the thin film transistor corresponding to the two adjacent rows of pixels 110 is different, so that the two rows of pixels 110 that are turned on at the same time have different charging rates, thereby producing different display effects to optimize the jaggedness of the screen edges and avoid obvious and strong jaggedness of the screen edges.

[0052] like Figure 9 As shown, as a fifth embodiment of this application, a driving method is disclosed. The driving method is used to drive the display panel as described in any of the above embodiments. The driving method includes:

[0053] S1: Generate corresponding gate drive signals and output them to the first pixel and the second pixel respectively, which are connected to the Nth row of scan lines; the third pixel and the fourth pixel are connected to the N+1th row of scan lines.

[0054] S2: Generate the corresponding data driving signal and output it to the Mth column data line connected to the first pixel and the M+2th column data line connected to the third pixel through the corresponding Sth data channel 210 respectively. The corresponding S+1th data channel is simultaneously output to the M+1th column data line connected to the second pixel and the M+3th column data line connected to the fourth pixel.

[0055] Where N, M, and T are natural numbers greater than or equal to 1.

[0056] refer to Figure 4 and Figure 9 As shown, in the pixel 110 architecture of this embodiment, the first pixel 121 and the second pixel 122 are connected to the Nth row of scan lines 130, and the third pixel 123 and the fourth pixel 124 are connected to the N+1th row of scan lines 130. The Mth column data line 140 connected to the first pixel 121 and the M+2th column data line 140 connected to the third pixel 123 are connected to the Sth data channel 210 on the data driver chip 200, and the M+1th column data line 140 connected to the second pixel 122 and the M+3th column data line 140 connected to the fourth pixel 124 are connected to the S+1th data channel 210 on the data driver chip 200. In fact, the number of gate lines is increased by 6 times, and the data driver chip 200 only needs one-third of the display panel 100 of the DRD architecture. When the display panel 100 is displaying normally, each gate driving unit generates a corresponding gate driving signal and outputs it to the corresponding scan line 130. When the scan line 130 is turned on, the corresponding data driver chip 200 outputs a data driving signal to the corresponding pixel 110 for charging and display.

[0057] like Figure 10 As shown, the sixth embodiment of this application is a further refinement and improvement of the fifth embodiment described above. (Refer to...) Figure 7 and Figure 10As shown, the first pixel 121, the second pixel 122, the third pixel 123, and the fourth pixel 124 are arranged in two rows and two columns. Along the extension direction of the data line 140, the first pixel 121 and the third pixel 123 are arranged sequentially, and the second pixel 122 and the fourth pixel 124 are arranged sequentially. Along the extension direction of the scan line 130, the first pixel 121 and the second pixel 122 are arranged sequentially, and the third pixel 123 and the fourth pixel 124 are arranged sequentially. The first common line 161 corresponding to the first pixel 121 and the second pixel 122 receives a first common level, and the second common line 162 corresponding to the third pixel 123 and the fourth pixel 124 receives a second common level. The driving method further includes the following steps:

[0058] S3: Detect the grayscale values ​​of the first pixel and the third pixel, and determine whether the grayscale values ​​are the same. If they are the same, output the first common level and the second common level with different voltage values ​​to the first common line and the second common line respectively. If they are different, output the first common level and the second common level with the same voltage values ​​to the first common line and the second common line respectively.

[0059] In this embodiment, considering that the first pixel 121 and the second pixel 122 in the pixel group 120 are main pixels 110, and the third pixel 123 and the fourth pixel 124 are auxiliary pixels 110, dividing the main pixels 110 and auxiliary pixels 110 can improve color shift. However, when the common level is not good, there will also be differences in brightness, which will affect the display. Therefore, common level lines are set for the main pixels 110 and auxiliary pixels 110 respectively, and the same or different common levels can be input to the corresponding common level lines respectively, thereby improving the difference in brightness and improving the display effect.

[0060] like Figure 11 As shown, the seventh embodiment of this application is a further refinement and improvement of the fifth or sixth embodiment described above. (Refer to...) Figure 8 and Figure 11 As shown, the display panel includes a refresh rate adjustment circuit 170, a gate driving circuit 180, a first compensation circuit 191, a second compensation circuit 192, and a screen detection module 220. Step S1 includes:

[0061] S11: Detect the next frame of the image and generate a first compensation voltage and a second compensation voltage according to the brightness to compensate the gate drive signals of the first gate drive unit and the second gate drive unit.

[0062] S12: Detect the display mode of the next frame. If it is a frequency multiplication display, control the gate drive signals of the first gate drive unit and the second gate drive unit to be simultaneously output to the input terminal of the Nth scan line and the input terminal of the N+1th scan line. If it is a normal display, control the gate drive signals of the first gate drive unit and the second gate drive unit to be output to the input terminal of the Nth scan line and the input terminal of the N+1th scan line in a time-division manner.

[0063] This embodiment mainly focuses on improvements made to the display panel of the DRD TRD architecture under different display modes. In both normal mode and frequency multiplication mode, the brightness of the next frame is detected, and the gate drive signal is compensated according to the brightness. If the brightness is insufficient, the voltage of the gate drive signal is positively compensated. If the brightness needs to be reduced, the voltage of the gate drive signal is negatively compensated, that is, the voltage of the gate drive signal is lowered. At the same time, in frequency multiplication mode, it is necessary to control the waveform and input time of the first gate drive signal and the second gate drive signal, and input the two gate drive signals at the same time to realize frequency multiplication display.

[0064] It should be noted that the limitations on the steps involved in this solution, without affecting the implementation of the specific solution, are not considered as limiting the order of the steps. That is, the steps listed first can be performed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the protection scope of this application. The inventive concept of this application can form many embodiments, but due to space limitations in the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. The combination of embodiments or technical features will enhance the original technical effect.

[0065] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A display panel comprising a plurality of rows of pixels, driven by data signals received from data output channels on a data driver chip, characterized in that, Each row of pixels is divided into multiple pixel groups, and each pixel group includes a first pixel, a second pixel, a third pixel, and a fourth pixel; the first pixel and the second pixel are connected to the Nth row of scan lines, and the third pixel and the fourth pixel are connected to the N+1th row of scan lines; the Mth column of data lines connected to the first pixel and the M+2th column of data lines connected to the third pixel are connected to the Sth data channel on the data driver chip, and the M+1th column of data lines connected to the second pixel and the M+3th column of data lines connected to the fourth pixel are connected to the S+1th data channel on the data driver chip; Where N, M, and T are natural numbers greater than or equal to 1; The first pixel and the third pixel have the same polarity, the second pixel and the fourth pixel have the same polarity, the first pixel and the second pixel have different polarities, the Mth column data line connected to the first pixel and the M+2th column data line connected to the third pixel are set on the same layer, the M+1th column data line connected to the second pixel and the M+3th column data line connected to the fourth pixel are set on the same layer, and the Mth column data line connected to the first pixel and the M+1th column data line connected to the second pixel are set on different layers; the Mth column data line is connected to the Sth data channel through a first fan-out line, and the M+2th column data line is connected to the S+1th data channel through a second fan-out line; the Mth column data line connects to the Mth column pixel of each row, the M+1th column data line connects to the M+1th column pixel of each row, the M+2th column data line connects to the M+2th column pixel of each row, and the M+3th column data line connects to the M+3th column pixel of each row, opening a complete row of pixels through two rows of scan lines.

2. The display panel of claim 1, wherein, Along the extension direction of the scan line, the first pixel, the second pixel, the third pixel, and the fourth pixel are arranged sequentially; Wherein, the length of the first fan-out routing line is less than the length of the second fan-out routing line, the cross-sectional area of ​​the first fan-out routing line is less than the cross-sectional area of ​​the second fan-out routing line, and the resistance value of the first fan-out routing line is equal to the resistance value of the second fan-out routing line.

3. The display panel as described in claim 2, characterized in that, The Sth data channel and the (S+1)th data channel are stacked on the data driver chip, and the Sth data channel is disposed on the (S+1)th data channel; the Sth data channel and the Mth column data line have the same height, and the (S+1)th data channel and the (M+1)th column data line have the same height.

4. The display panel as described in claim 1, characterized in that, Between two adjacent rows of scan lines, the first pixel, the second pixel, the third pixel, and the fourth pixel are arranged in two rows and two columns. Along the extension direction of the data lines, the first pixel and the third pixel are arranged in sequence, and the second pixel and the third pixel are arranged in sequence. The (M+2)th column data line is located between the Mth column data line and the (M+1)th column data line, and the (M+1)th column data line is located between the (M+2)th column data line and the (M+3)th column data line. The Mth column data line, the (M+1)th column data line, the (M+2)th column data line, and the (M+3)th column data line are arranged on the same layer.

5. The display panel as described in claim 4, characterized in that, The first pixel and the second pixel are primary pixels, and the third pixel and the fourth pixel are secondary pixels. The transmittance of the first pixel is greater than that of the third pixel, and the transmittance of the second pixel is greater than that of the fourth pixel. The first common line corresponding to the first pixel and the second pixel receives a first common voltage level, and the second common line corresponding to the third pixel and the fourth pixel receives a second common voltage level. When the gray levels of the first pixel and the third pixel are the same, the voltages of the first common voltage level and the second common voltage level are different.

6. The display panel as described in claim 4, characterized in that, The display panel includes a refresh rate adjustment circuit and a gate drive circuit. The gate drive circuit includes a first gate drive unit and a second gate drive unit. The first gate drive unit is connected to the input terminal of the Nth scan line, and the second gate drive unit is connected to the input terminal of the (N+1)th scan line. The refresh rate adjustment circuit controls the gate drive signals of the first gate drive unit and the second gate drive unit to be output simultaneously or time-divisionally to the input terminals of the Nth scan line and the (N+1)th scan line to achieve different refresh rates.

7. The display panel as described in claim 6, characterized in that, The display panel further includes a first compensation circuit, a second compensation circuit, and a screen detection module. The input terminal of the first compensation circuit is connected between the first gate driver and the input terminal of the Nth row of scan lines, and the output terminal is connected to the screen detection module. The input terminal of the second compensation circuit is connected between the second gate driver and the input terminal of the N+1th row of scan lines, and the output terminal is connected to the screen detection module. The image detection module generates a first compensation voltage and a second compensation voltage based on the brightness level, which are then input to the first compensation circuit and the second compensation circuit, respectively. The magnitudes of the first compensation voltage and the second compensation voltage are different.

8. A driving method, characterized in that, The driving method for driving the display panel as described in any one of claims 1-7 includes: The corresponding gate drive signals are generated and output to the first pixel and the second pixel respectively, which are connected to the Nth row of scan lines. The third pixel and the fourth pixel are connected to the N+1th row of scan lines. The corresponding data driving signals are generated and output to the Mth column data line connected to the first pixel and the M+2th column data line connected to the third pixel through the corresponding Sth data channel, respectively. The corresponding S+1th data channel is simultaneously output to the M+1th column data line connected to the second pixel and the M+3th column data line connected to the fourth pixel. Where N, M, and T are natural numbers greater than or equal to 1.

9. The driving method as described in claim 8, characterized in that, The first pixel, second pixel, third pixel, and fourth pixel are arranged in two rows and two columns. Along the extension direction of the data line, the first pixel and third pixel are arranged sequentially, and the second pixel and fourth pixel are arranged sequentially. Along the extension direction of the scan line, the first pixel and second pixel are arranged sequentially, and the third pixel and fourth pixel are arranged sequentially. The first common line corresponding to the first pixel and second pixel receives a first common voltage level, and the second common line corresponding to the third pixel and fourth pixel receives a second common voltage level. The driving method further includes the following steps: The grayscale values ​​of the first pixel and the third pixel are detected, and it is determined whether the grayscale values ​​are the same. If they are the same, the first common level and the second common level with different voltage values ​​are output to the first common line and the second common line respectively. If they are different, the first common level and the second common level with the same voltage value are output to the first common line and the second common line respectively.

10. The driving method as described in claim 8, characterized in that, The display panel includes a refresh rate adjustment circuit, a gate driving circuit, a first compensation circuit, a second compensation circuit, and a screen detection module. The step of generating corresponding gate driving signals and outputting them to the first pixel and the second pixel to connect to the Nth row of scan lines, and connecting the third pixel and the fourth pixel to the N+1th row of scan lines, includes: The system detects the next frame of the image and generates a first compensation voltage and a second compensation voltage based on the brightness level to compensate the gate drive signals of the first gate drive unit and the second gate drive unit. The display mode of the next frame is detected. If it is a frequency multiplication display, the gate drive signals of the first gate drive unit and the second gate drive unit are simultaneously output to the input terminals of the Nth and N+1th scan lines. If it is a normal display, the gate drive signals of the first and second gate drive units are output to the input terminals of the Nth and N+1th scan lines in a time-division manner.

Images