Transistor and preparation method thereof, driving substrate and display device

Abstract

The invention provides a transistor and a preparation method thereof, a driving substrate and a display device.The transistor comprises a substrate, a semiconductor assembly, a grid assembly, a first electrode and a second electrode, and the semiconductor assembly, the grid assembly, the first electrode and the second electrode are located on the substrate. The orthographic projection of each channel region on the substrate is at least partially overlapped with the orthographic projection of the gate component on the substrate, so that each channel region can generate carriers under the regulation and control of the gate component to conduct the first pole and the second pole; therefore, each channel region can generate a current value between the first electrode and the second electrode, and at least two channel regions can generate at least two current values between the first electrode and the second electrode, so that the current value of the transistor can be remarkably improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a transistor and a method for manufacturing the same, a driving substrate and a display device. Background Art

[0002] Transistors are the core components of display devices. Each pixel in the display device relies on transistors for switching and driving. The active layer is an important structure in the transistor. It is a semiconductor material that can generate carriers and conduct under the regulation of the gate. Summary of the invention

[0003] In view of this, the purpose of the present application is to provide a transistor and a manufacturing method thereof, a driving substrate and a display device.

[0004] Based on the above-mentioned purpose, the first aspect of the present application provides a transistor, including: a substrate, and a semiconductor component, a gate component, a first pole and a second pole located on the substrate, the semiconductor component is connected to both the first pole and the second pole, the semiconductor component includes at least two channel regions, and the orthographic projection of each of the channel regions on the substrate at least partially overlaps with the orthographic projection of the gate component on the substrate.

[0005] Optionally, the gate assembly includes at least one gate, each of the gates corresponds to at least one of the channel regions, and an orthographic projection of the channel region on the substrate at least partially overlaps with an orthographic projection of the corresponding gate on the substrate.

[0006] Optionally, the semiconductor component includes a first active layer and a second active layer, the first active layer is located on the substrate, the second active layer is located on a side of the first active layer away from the substrate, the first active layer includes a first channel region, the second active layer includes a second channel region, and the orthographic projection of the first channel region on the substrate and the orthographic projection of the second channel region on the substrate both at least partially overlap with the orthographic projection of the gate component on the substrate.

[0007] Optionally, the first channel region is located on a side of the first active layer facing away from the substrate, and the second channel region is located on a side of the second active layer close to the substrate.

[0008] Optionally, the gate assembly includes a first gate, which is insulated and arranged between the first active layer and the second active layer, and the orthographic projection of the first channel region on the base substrate and the orthographic projection of the second channel region on the base substrate both at least partially overlap with the orthographic projection of the first gate on the base substrate.

[0009] Optionally, the gate assembly includes a first gate and a second gate, the first gate is insulated and arranged between the first active layer and the second active layer, the second gate is insulated and arranged on a side of the first active layer close to the base substrate, the orthographic projection of the first channel region on the base substrate at least partially overlaps with the orthographic projection of the second gate on the base substrate, and the orthographic projection of the second channel region on the base substrate at least partially overlaps with the orthographic projection of the first gate on the base substrate.

[0010] Optionally, the first active layer further includes a first polar region and a second polar region, the second active layer further includes a third polar region and a fourth polar region, the first polar region is connected to both the first polar region and the third polar region, and the second polar region is connected to both the second polar region and the fourth polar region.

[0011] Optionally, the semiconductor component includes a third active layer, the third active layer includes a third channel region and a fourth channel region arranged relatively to each other, and the orthographic projection of the third channel region on the substrate and the orthographic projection of the fourth channel region on the substrate both at least partially overlap with the orthographic projection of the gate component on the substrate.

[0012] Optionally, the third channel region is located on a side of the third active layer away from the substrate, and the fourth channel region is located on a side of the third active layer close to the substrate.

[0013] Optionally, the gate assembly includes a third gate and a fourth gate, the third gate is insulated and arranged on a side of the third active layer facing away from the substrate, the fourth gate is insulated and arranged on a side of the third active layer close to the substrate, the orthographic projection of the third channel region on the substrate at least partially overlaps with the orthographic projection of the third gate on the substrate, and the orthographic projection of the fourth channel region on the substrate at least partially overlaps with the orthographic projection of the fourth gate on the substrate.

[0014] Optionally, the third active layer further includes a fifth polar region and a sixth polar region, the first polar region is connected to the fifth polar region, and the second polar region is connected to the sixth polar region.

[0015] A second aspect of the present application provides a method for manufacturing a transistor, comprising:

[0016] Providing a substrate;

[0017] A semiconductor component, a gate component, a first pole and a second pole are manufactured on the substrate, wherein the semiconductor component is connected to both the first pole and the second pole, and the semiconductor component includes at least two channel regions, and the orthographic projection of each of the channel regions on the substrate at least partially overlaps with the orthographic projection of the gate component on the substrate.

[0018] A third aspect of the present application provides a driving substrate, comprising the transistor described in any one of the first aspect above, or a transistor prepared by the preparation method described in the second aspect above.

[0019] A fourth aspect of the present application provides a display device, comprising the driving substrate described in the third aspect.

[0020] From the above description, it can be seen that the transistor and its preparation method, driving substrate and display device provided by the present application, the transistor includes a substrate and a semiconductor component, a gate component, a first pole and a second pole located on the substrate, the semiconductor component includes at least two channel regions, and the positive projection of each channel region on the substrate substrate at least partially overlaps with the positive projection of the gate component on the substrate substrate. In this way, each channel region can generate carriers under the regulation of the gate component to conduct the first pole and the second pole, so that each channel region can generate a current value between the first pole and the second pole, and at least two channel regions can generate at least two current values ​​between the first pole and the second pole. Compared with the existing transistor with only one channel region, the transistor of the present application significantly improves the transistor current value due to the increase in the number of channel regions, so that the transistor of the present application can meet the requirements of the existing display device for the transistor current value, and thus the transistor of the present application can directly replace the existing thin film transistor as a driving element for driving the pixels of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 A schematic diagram of a first structure of a transistor according to an embodiment of the present application;

[0023] Figure 2 A second structural schematic diagram of a transistor according to an embodiment of the present application;

[0024] Figure 3 A third structural schematic diagram of a transistor according to an embodiment of the present application;

[0025] Figure 4 A fourth structural schematic diagram of a transistor according to an embodiment of the present application;

[0026] Figure 5 A fifth structural schematic diagram of a transistor according to an embodiment of the present application;

[0027] Figure 6 This is a sixth structural schematic diagram of the transistor according to an embodiment of the present application.

[0028] In the figure: 1. substrate; 2. semiconductor component; 21. first active layer; 211. first channel region; 212. first pole region; 213. second pole region; 22. second active layer; 221. second channel region; 222. third pole region; 223. fourth pole region; 23. third active layer; 231. third channel region; 232. fourth channel region; 233. sixth pole region; 234. fifth pole region; 3. first pole; 31. first part; 32. second part; 4. second pole; 41. third part; 42. fourth part; 5. first insulating layer; 6. second insulating layer; 7. gate component; 71. first gate; 72. second gate; 73. third gate; 74. fourth gate; 8. third insulating layer; 9. fourth insulating layer. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0030] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0031] In existing display devices, the most widely used transistor is a thin film transistor (TFT), which is generally used as a driving element of a pixel in the industry.

[0032] TFT is formed by sputtering and chemical deposition on non-single crystal wafers such as glass or plastic substrates (of course, it can also be on wafers) to form various films necessary for manufacturing circuits, and large-scale semiconductor integrated circuits (LSICs) are manufactured by processing the films. The use of non-single crystal substrates can greatly reduce costs, and is an extension of traditional large-scale integrated circuits to large areas, multi-functions, and low costs.

[0033] In the process of using TFT as a driving element, the inventors found that the traditional TFT as a driving element of a display device still has some shortcomings, such as a slightly higher saturation voltage, a slightly lower gain coefficient, and a small size effect.

[0034] Based on this, the inventors thought that source-gate transistors (SGTs) have many advantages over current thin-film transistors, such as low saturation voltage, high gain coefficient, no small size effect, etc., and have great advantages in the semiconductor chip and display industries.

[0035] A source-gate transistor is a triode consisting of a source, a gate, and a drain. The source and drain are PN structures, usually made of different types of semiconductor materials, and the gate is a metal electrode used to control the source and drain currents.

[0036] The source-gate transistor achieves carrier flow regulation by the source by introducing Schottky potential at the source of the thin film transistor, changing the transmission mechanism of the traditional TFT where the carrier flow is regulated by the channel. Compared with the traditional TFT, SGT has the advantages of high gain, high output impedance, low power consumption, high bias stress stability, and insensitivity to short channel effects. In addition, SGT has a higher tolerance for active layer materials, and inferior and low-performance semiconductors can also be used as active layers. These advantages make SGT promising for use in the semiconductor chip and display industries.

[0037] However, since there is a Schottky contact between the source and the semiconductor, the transistor current value is small, so it cannot directly replace the existing thin film transistor.

[0038] Based on this, how to increase the current value of the source-gate transistor so that it can directly replace the thin film transistor as a driving element for driving the pixels of the display device is an urgent problem to be solved.

[0039] Based on this, see Figure 1 The present application provides a transistor, comprising: a substrate 1, and a semiconductor component 2, a gate component 7, a first pole 3 and a second pole 4 located on the substrate 1, the semiconductor component 2 is connected to both the first pole 3 and the second pole 4, the semiconductor component 2 comprises at least two channel regions, and the orthographic projection of each of the channel regions on the substrate 1 at least partially overlaps with the orthographic projection of the gate component 7 on the substrate 1.

[0040] Specifically, the substrate 1 can support and protect various components of the transistor. The substrate 1 can be formed of glass, quartz, ceramic or a flexible plastic material. For example, when the substrate 1 is formed of a plastic material, it can be formed of polyimide (PI). The substrate 1 can be flexible, stretchable, foldable, bendable and / or rollable.

[0041] The semiconductor component 2 is located on the substrate 1 , and the semiconductor component 2 may be made of amorphous or polycrystalline semiconductor materials, oxide semiconductors or organic semiconductor materials.

[0042] The semiconductor component 2 includes at least two channel regions. Exemplarily, the semiconductor component 2 may include two channel regions, or may include three or more channel regions.

[0043] The channel region is a region not doped with impurities. The semiconductor component 2 also includes a region doped with impurities for connecting the first electrode 3 and the second electrode 4 .

[0044] The first electrode 3 and the second electrode 4 are two electrodes in the transistor except the gate electrode. For example, the first electrode 3 can be a source electrode and the second electrode 4 can be a drain electrode; or the first electrode 3 can be a drain electrode and the second electrode 4 can be a source electrode. Accordingly, in the semiconductor component 2, the region connected to the source electrode can be called a source region, and the region connected to the drain electrode can be called a drain region.

[0045] In the present application, the semiconductor component 2 includes at least two channel regions, and the orthographic projection of each channel region on the substrate 1 at least partially overlaps with the orthographic projection of the gate component 7 on the substrate 1. In this way, each channel region can generate carriers under the control of the gate component 7 to conduct the first pole 3 and the second pole 4, so that each channel region can generate a current between the first pole 3 and the second pole 4, and at least two channel regions can generate at least two currents between the first pole 3 and the second pole 4. Compared with the existing transistor with only one channel region, the transistor of the present application significantly improves the transistor current value due to the increase in the number of channel regions, so that the transistor of the present application can meet the requirements of the existing display device for the transistor current size, and thus the transistor of the present application can directly replace the existing thin film transistor as a driving element for driving the pixels of the display device.

[0046] In some embodiments, the gate assembly 7 includes at least one gate, each of the gates corresponds to at least one of the channel regions, and the orthographic projection of the channel region on the substrate 1 at least partially overlaps with the orthographic projection of the corresponding gate on the substrate 1 .

[0047] Specifically, the gate component 7 includes at least one gate. Exemplarily, the gate component 7 may include one gate, two gates or multiple gates.

[0048] The semiconductor component 2 includes at least two channel regions. Exemplarily, the semiconductor component 2 may include two channel regions, or may include three or more channel regions.

[0049] Each of the gates corresponds to at least one of the channel regions. Exemplarily, one gate may correspond to one channel region, so that the channel region generates carriers under the regulation of the corresponding gate to conduct the first pole 3 and the second pole 4; one gate may also correspond to two channel regions, so that the two channel regions can simultaneously generate carriers under the regulation of the corresponding gate to conduct the first pole 3 and the second pole 4.

[0050] In this embodiment, the number of channel regions and the number of gates are not limited, as long as each of the channel regions can be controlled by the corresponding gate. Obviously, the more channel regions there are in the transistor, the greater the current generated under the control of the gate. Therefore, the specific number of channel regions and the specific number of gates are selected according to the actual demand for current value and the manufacturing process.

[0051] In the present application, each of the gates corresponds to at least one of the channel regions, that is, instead of one gate corresponding to one channel region, one gate may correspond to two channel regions. In this way, while increasing the number of channel regions to improve the current value, the number of gates can also be reduced to simplify the manufacturing process and save manufacturing costs.

[0052] In some embodiments, see Figure 1 As shown, the semiconductor component 2 includes a first active layer 21 and a second active layer 22, the first active layer 21 is located on the substrate 1, and the second active layer 22 is located on the side of the first active layer 21 away from the substrate 1, the first active layer 21 includes a first channel region 211, and the second active layer 22 includes a second channel region 221, and the orthographic projection of the first channel region 211 on the substrate 1 and the orthographic projection of the second channel region 221 on the substrate 1 both at least partially overlap with the orthographic projection of the gate component 7 on the substrate 1.

[0053] Specifically, the first active layer 21 includes a first channel region 211, and the second active layer 22 includes a second channel region 221. The orthographic projection of the first channel region 211 on the substrate 1 and the orthographic projection of the second channel region 221 on the substrate 1 both at least partially overlap with the orthographic projection of the gate component 7 on the substrate 1. In this way, the first channel region 211 and the second channel region 221 can simultaneously generate carriers under the regulation of the gate component 7 to turn on the first pole 3 and the second pole 4, thereby increasing the current value of the transistor.

[0054] Furthermore, when two active layers are provided in the transistor and a channel region is provided on each active layer, how to drive the two channel regions simultaneously to increase the current value is a problem that needs to be solved.

[0055] Based on this, in some embodiments, continue to see Figure 1 The gate assembly 7 includes a first gate 71, which is insulated and arranged between the first active layer 21 and the second active layer 22, and the orthographic projection of the first channel region 211 on the base substrate 1 and the orthographic projection of the second channel region 221 on the base substrate 1 both at least partially overlap with the orthographic projection of the first gate 71 on the base substrate 1.

[0056] Specifically, the first gate 71 is insulated and arranged between the first active layer 21 and the second active layer 22, and the orthographic projection of the first channel region 211 on the base substrate 1 and the orthographic projection of the second channel region 221 on the base substrate 1 both at least partially overlap with the orthographic projection of the first gate 71 on the base substrate 1. In this way, the first active layer 21 and the second active layer 22 can share a first gate 71, and the first gate 71 can simultaneously regulate the first channel region 211 and the second channel region 221 to increase the current value of the transistor.

[0057] Further, in order to realize that the first gate 71 is insulated and arranged between the first active layer 21 and the second active layer 22, the transistor further includes a second insulating layer 6 and a third insulating layer 8. The first active layer 21 is located on the base substrate 1, the third insulating layer 8 covers the first active layer 21 and the base substrate 1, the first gate 71 is located on the third insulating layer 8, the second insulating layer 6 covers the first gate 71 and the third insulating layer 8, and the second active layer 22 is located on the second insulating layer 6. In this way, by arranging the second insulating layer 6 and the third insulating layer 8, the insulation arrangement between the first active layer 21, the first gate 71 and the second active layer 22 is realized.

[0058] In the present application, the first active layer 21 and the second active layer 22 can share a first gate 71, and the first gate 71 can simultaneously regulate the first channel region 211 and the second channel region 221, thereby increasing the current value of the transistor. At the same time, the two active layers share one gate, which can also reduce the number of gates to simplify the manufacturing process and save manufacturing costs.

[0059] In some embodiments, see Figure 1 The first channel region 211 is located on the side of the first active layer 21 away from the substrate 1, and the second channel region 221 is located on the side of the second active layer 22 close to the substrate 1. In this way, the first channel region 211 and the second channel region 221 are both arranged close to the first gate 71, which facilitates the first gate 71 to regulate the first channel region 211 and the second channel region 221.

[0060] In some embodiments, see Figure 2 The gate assembly 7 includes a first gate 71 and a second gate 72, the first gate 71 is insulated and arranged between the first active layer 21 and the second active layer 22, the second gate 72 is insulated and arranged on a side of the first active layer 21 close to the base substrate 1, the orthographic projection of the first channel region 211 on the base substrate 1 at least partially overlaps with the orthographic projection of the second gate 72 on the base substrate 1, and the orthographic projection of the second channel region 221 on the base substrate 1 at least partially overlaps with the orthographic projection of the first gate 71 on the base substrate 1.

[0061] Specifically, the orthographic projection of the first channel region 211 on the base substrate 1 at least partially overlaps with the orthographic projection of the second gate 72 on the base substrate 1 , that is, the first channel region 211 is regulated by the second gate 72 .

[0062] The orthographic projection of the second channel region 221 on the base substrate 1 at least partially overlaps with the orthographic projection of the first gate 71 on the base substrate 1 , that is, the second channel region 221 is regulated by the first gate 71 .

[0063] That is, in this embodiment, each active layer is provided with a channel region, each of the channel regions corresponds to a gate, and each channel region is driven by its corresponding gate. In this way, in actual application, by controlling the first gate 71 and the second gate 72 to simultaneously regulate the first channel region 211 and the second channel region 221, the current between the first pole 3 and the second pole 4 can be increased, thereby increasing the current value of the transistor.

[0064] Further, in order to realize that the first gate 71 is insulated and arranged between the first active layer 21 and the second active layer 22, and the second gate 72 is insulated and arranged on the side of the first active layer 21 close to the base substrate 1, the transistor further includes a second insulating layer 6, a third insulating layer 8 and a fourth insulating layer 9. The second gate 72 is arranged on the base substrate 1, the fourth insulating layer 9 covers the second gate 72 and the base substrate 1, the first active layer 21 is arranged on the fourth insulating layer 9, the third insulating layer 8 covers the first active layer 21 and the fourth insulating layer 9, the first gate 71 is located on the third insulating layer 8, the second insulating layer 6 covers the first gate 71 and the third insulating layer 8, and the second active layer 22 is located on the second insulating layer 6. In this way, by arranging the second insulating layer 6, the third insulating layer 8 and the fourth insulating layer 9, the insulation arrangement between the second gate 72, the first active layer 21, the first gate 71 and the second active layer 22 is realized.

[0065] In the present application, each active layer is provided with a channel region, each of the channel regions corresponds to a gate, and each channel region is driven by its corresponding gate. Thus, in practical applications, by controlling the first gate 71 and the second gate 72 to simultaneously regulate the first channel region 211 and the second channel region 221, the current between the first pole 3 and the second pole 4 can be increased, thereby increasing the current value of the transistor.

[0066] In some embodiments, see Figure 3 and Figure 4 As shown, the first active layer 21 also includes a first polar region 212 and a second polar region 213 , the second active layer 22 also includes a third polar region 222 and a fourth polar region 223 , the first pole 3 is connected to both the first polar region 212 and the third polar region 222 , and the second pole 4 is connected to both the second polar region 213 and the fourth polar region 223 .

[0067] Specifically, when the first electrode 3 is a source electrode and the second electrode 4 is a drain electrode, the first electrode region 212 and the third electrode region 222 are both source regions, and the second electrode region 213 and the fourth electrode region 223 are both drain regions, and vice versa.

[0068] When the first pole 3 is connected to the first pole region 212 and the third pole region 213, it can be directly connected or connected through a via. When the second pole 4 is connected to the second pole region 213 and the fourth pole region 223, it can be directly connected or connected through a via.

[0069] It is worth noting that each polar region of each active layer is arranged on the side of the channel region of the active layer away from the corresponding gate, that is, no polar region is arranged between the channel region and the corresponding gate, otherwise the polar region will affect the regulation of the channel region by the gate. Therefore, due to the different positions of the gate, the position of the polar region on the active layer may also be different. For example, Figure 3 As shown, the first pole region 212 is disposed on a side of the first channel region 211 away from the first gate 71; Figure 4 As shown, the first pole region 212 is disposed on a side of the first channel region 211 away from the second gate 72 .

[0070] There are many ways to connect the first electrode 3 and the second electrode 4 with the first active layer 21 and the second active layer 22 .

[0071] For example, see Figure 3 As shown, the first pole 3 may include a first portion 31 and a second portion 32, and the first portion 31 and the second portion 32 are connected through a via. The first portion 31 is also connected to the third pole region 222 through a via, and the second portion 32 is directly connected to the first pole region 212. In this way, the first pole 3 can be connected to the third pole region 222 and the first pole region 212 at the same time.

[0072] Furthermore, the transistor further includes a first insulating layer 5, and the first insulating layer 5 covers the second active layer 22 and the second insulating layer 6. The first portion 31 is located on the first insulating layer 5, and a via hole is provided on the first insulating layer 5, and the first portion 31 is connected to the third polar region 222 on the second active layer 22 through the via hole.

[0073] The second portion 32 is disposed in the same layer as the first active layer 21, one end of the second portion 32 is connected to the first portion 31 via a via hole, and the other end of the second portion 32 is covered by the first active layer 21 (eg, Figure 3 As shown), so that the second portion 32 can be directly connected to the first polar region 212 of the first active layer 21.

[0074] Alternatively, the second portion 32 is disposed in the same layer as the first active layer 21, one end of the second portion 32 is connected to the first portion 31 via a via hole, and the other end of the second portion 32 covers the end of the first active layer 21 (eg, Figure 4 As shown), so that the second portion 32 can be directly connected to the first polar region 212 of the first active layer 21.

[0075] Correspondingly, the structure of the second pole 4 can be completely symmetrical with the structure of the first pole 3, that is, the connection relationship between the second pole 4 and the second polar region 213 and the fourth polar region 223 can be the same as the connection relationship between the first pole 3 and the third polar region 222 and the fourth polar region 223, which will not be repeated here.

[0076] In the present application, the first active layer 21 and the second active layer 22 are both connected to the first pole 3 and the second pole 4, and the first active layer 21 and the second active layer 22 are both provided with a channel region, so that two channel regions (i.e., the first channel region 211 and the second channel region 221) are provided between the first pole 3 and the second pole 4. In a specific implementation, compared with the setting of only one channel region, when the two channel regions are simultaneously regulated, double current can be generated to significantly increase the current value of the transistor.

[0077] In some embodiments, the semiconductor component 2 includes a third active layer 23, the third active layer 23 includes a third channel region 231 and a fourth channel region 232 that are relatively arranged, and the orthographic projection of the third channel region 231 on the substrate substrate 1 and the orthographic projection of the fourth channel region 232 on the substrate substrate 1 both at least partially overlap with the orthographic projection of the gate component 7 on the substrate substrate 1.

[0078] Specifically, the orthographic projection of the third channel region 231 on the substrate 1 and the orthographic projection of the fourth channel region 232 on the substrate 1 at least partially overlap with the orthographic projection of the gate component 7 on the substrate 1. In this way, one gate component 7 can simultaneously regulate the third channel region 231 and the fourth channel region 232, thereby increasing the current value of the transistor.

[0079] In the present application, the third channel region 231 and the fourth channel region 232 are relatively arranged on the same third active layer 23, and the third channel region 231 and the fourth channel region 232 can be simultaneously controlled by a gate component 7. In this way, the number of active layers can be reduced while increasing the transistor current value, thereby simplifying the preparation process and reducing the production cost.

[0080] In some embodiments, see Figure 5 As shown, the gate assembly 7 includes a third gate 73 and a fourth gate 74, the third gate 73 is insulated and arranged on the side of the third active layer 23 away from the substrate 1, and the fourth gate 74 is insulated and arranged on the side of the third active layer 23 close to the substrate 1, the orthographic projection of the third channel region 231 on the substrate 1 at least partially overlaps with the orthographic projection of the third gate 73 on the substrate 1, and the orthographic projection of the fourth channel region 232 on the substrate 1 at least partially overlaps with the orthographic projection of the fourth gate 74 on the substrate 1.

[0081] Specifically, the orthographic projection of the third channel region 231 on the substrate 1 at least partially overlaps with the orthographic projection of the third gate 73 on the substrate 1 , that is, the third channel region 231 is regulated by the third gate 73 .

[0082] The orthographic projection of the fourth channel region 232 on the substrate 1 at least partially overlaps with the orthographic projection of the fourth gate 74 on the substrate 1 , that is, the fourth channel region 232 is regulated by the fourth gate 74 .

[0083] That is, in this embodiment, the third active layer 23 is provided with two channel regions, each channel region corresponds to a gate, and each channel region is driven by its corresponding gate. In this way, in actual application, by controlling the third gate 73 and the fourth gate 74 to simultaneously regulate the third channel region 231 and the fourth channel region 232, the current between the first pole 3 and the second pole 4 can be increased, thereby increasing the current value of the transistor.

[0084] Further, in order to realize that the third gate 73 is insulated and arranged on the side of the third active layer 23 away from the base substrate 1, and the fourth gate 74 is insulated and arranged on the side of the third active layer 23 close to the base substrate 1, the transistor further includes a second insulating layer 6 and a third insulating layer 8. The fourth gate 74 is arranged on the base substrate 1, the third insulating layer 8 covers the fourth gate 74 and the base substrate 1, the third active layer 23 is arranged on the third insulating layer 8, the second insulating layer 6 covers the third active layer 23 and the third insulating layer 8, and the third gate 73 is located on the second insulating layer 6. In this way, by arranging the second insulating layer 6 and the third insulating layer 8, the insulation arrangement between the fourth gate 74, the third active layer 23 and the third gate 73 is realized.

[0085] In the present application, the third channel region 231 and the fourth channel region 232 are relatively arranged on the same third active layer 23, and the third channel region 231 and the fourth channel region 232 are respectively controlled by the third gate 73 and the fourth gate 74. In this way, the number of active layers can be reduced while increasing the transistor current value, thereby simplifying the preparation process and reducing the production cost.

[0086] In some embodiments, the third channel region 231 is located on a side of the third active layer 23 away from the base substrate 1, and the fourth channel region 232 is located on a side of the third active layer 23 close to the base substrate 1. In this way, the third channel region 231 is arranged close to the third gate 73, and the fourth channel region 232 is arranged close to the fourth gate, so that the third gate 73 and the fourth gate 74 can regulate the third channel region 231 and the fourth channel region 232 respectively.

[0087] In some embodiments, see Figure 6 As shown, the third active layer 23 further includes a fifth pole region 234 and a sixth pole region 233 , the first pole 3 is connected to the fifth pole region 234 , and the second pole 4 is connected to the sixth pole region 233 .

[0088] Specifically, when the first electrode 3 is a source electrode and the second electrode 4 is a drain electrode, the fifth electrode region 234 is a source region and the sixth electrode region 233 is a drain region, and vice versa.

[0089] The fifth electrode region 234 is located at a side of the fourth channel region 232 away from the fourth gate 74. When the first electrode 3 is connected to the fifth electrode region 234, it can be directly connected or connected through a via.

[0090] The sixth electrode region 233 is located on a side of the third channel region 231 away from the third gate 73. When the second electrode 4 is connected to the sixth electrode region 233, it can be directly connected or connected through a via.

[0091] There are many ways to connect the first electrode 3 and the second electrode 4 with the third active layer 23 .

[0092] For example, see Figure 6 As shown, the second pole 4 may include a third portion 41 and a fourth portion 42 , one end of the fourth portion 42 is connected to the third portion 41 , and the other end of the fourth portion 42 is covered by the third active layer 23 , so that the fourth portion 42 is directly connected to the sixth pole region 233 .

[0093] The first pole 3 is directly connected to the third active layer 23 through a via hole, so that the first pole 3 is connected to the fifth pole region 234 .

[0094] Furthermore, the transistor further includes a first insulating layer 5, and the first insulating layer 5 covers the third gate 73 and the second insulating layer 6. The third portion 41 and the first electrode 3 are arranged on the first insulating layer 5 with intervals, and the first insulating layer 5 is provided with two via holes, and the first electrode 3 is connected to the fifth electrode region 234 on the third active layer 23 through one of the via holes.

[0095] The fourth part 42 is arranged in the same layer as the third active layer 23, one end of the fourth part 42 is connected to the third part 41 through another via, and the other end of the fourth part 42 is covered by the third active layer 23, so that the third part 41 can be directly connected to the sixth polar region 233 of the third active layer 23.

[0096] In the present application, the third active layer 23 is connected to the first pole 3 and the second pole 4, and the third active layer 23 is provided with two channel regions, so that two channel regions (i.e., the first channel region 211 and the second channel region 221) are provided between the first pole 3 and the second pole 4. In a specific implementation, compared with the setting of only one channel region, when the two channel regions are simultaneously regulated, double current can be generated to significantly increase the current value of the transistor.

[0097] The present application also provides a method for preparing a transistor, comprising:

[0098] Step S100, providing a substrate 1;

[0099] Step S200, manufacturing a semiconductor component 2, a gate component 7, a first pole 3 and a second pole 4 on the base substrate 1, wherein the semiconductor component 2 is connected to both the first pole 3 and the second pole 4, and the semiconductor component 2 includes at least two channel regions, and the orthographic projection of each of the channel regions on the base substrate 1 at least partially overlaps with the orthographic projection of the gate component 7 on the base substrate 1.

[0100] Specifically, the transistor prepared in the present application includes a substrate 1 and a semiconductor component 2, a gate component 7, a first pole 3 and a second pole 4 located on the substrate 1. The semiconductor component 2 includes at least two channel regions, and the orthographic projection of each channel region on the substrate 1 at least partially overlaps with the orthographic projection of the gate component 7 on the substrate 1. In this way, each channel region can generate carriers under the regulation of the gate component 7 to conduct the first pole 3 and the second pole 4, so that each channel region can generate a current between the first pole 3 and the second pole 4, and at least two channel regions can generate at least two currents between the first pole 3 and the second pole 4. Compared with the existing transistor with only one channel region, the transistor of the present application significantly improves the transistor current value due to the increase in the number of channel regions, so that the transistor of the present application can meet the requirements of the existing display device for the transistor current size, and thus the transistor of the present application can directly replace the existing thin film transistor as a driving element for driving the pixels of the display device.

[0101] A third aspect of the present application provides a driving substrate, comprising the transistor described in any one of the first aspect above, or a transistor prepared by the preparation method described in the second aspect above.

[0102] Specifically, the driving substrate may include a plurality of transistors arranged in an array. When the driving substrate is used in a display device, each transistor corresponds to a pixel to drive the corresponding pixel to turn on or off.

[0103] Since the transistor of the present application can increase the current value compared to the existing transistor with only one channel region, the transistor of the present application can be used to replace the existing thin film transistor as a driving element for driving the pixels of the display device, so as to reduce the saturation voltage of the display device, improve the gain coefficient and bias stress stability, and reduce power consumption while meeting the current requirements.

[0104] A fourth aspect of the present application provides a display device, comprising the driving substrate described in the third aspect.

[0105] The display device can be a product with an image display function, for example, it can be: a monitor, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, a home appliance, an information query device (such as business query equipment and monitors of e-government, banks, hospitals, power and other departments).

[0106] The display device has the technical effects described in any of the above embodiments, which will not be elaborated here.

[0107] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0108] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0109] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the present application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the protection scope of the present application.

Claims

1. A transistor, characterized in that: include: A substrate, and a semiconductor component, a gate component, a first pole and a second pole located on the substrate, wherein the semiconductor component is connected to both the first pole and the second pole, and the semiconductor component includes at least two channel regions, and the orthographic projection of each of the channel regions on the substrate at least partially overlaps with the orthographic projection of the gate component on the substrate.

2. The transistor according to claim 1, characterized in that The gate assembly includes at least one gate, each of the gates corresponds to at least one channel region, and an orthographic projection of the channel region on the substrate at least partially overlaps with an orthographic projection of the corresponding gate on the substrate.

3. The transistor according to claim 2, characterized in that The semiconductor component includes a first active layer and a second active layer, the first active layer is located on the substrate, the second active layer is located on a side of the first active layer away from the substrate, the first active layer includes a first channel region, the second active layer includes a second channel region, and the orthographic projection of the first channel region on the substrate and the orthographic projection of the second channel region on the substrate both at least partially overlap with the orthographic projection of the gate component on the substrate.

4. The transistor according to claim 3, characterized in that The gate assembly includes a first gate, which is insulated and arranged between the first active layer and the second active layer, and the orthographic projection of the first channel region on the base substrate and the orthographic projection of the second channel region on the base substrate both at least partially overlap with the orthographic projection of the first gate on the base substrate.

5. The transistor according to claim 4, characterized in that The first channel region is located on a side of the first active layer away from the substrate, and the second channel region is located on a side of the second active layer close to the substrate.

6. The transistor according to claim 3, characterized in that The gate assembly includes a first gate and a second gate, the first gate is insulated and arranged between the first active layer and the second active layer, the second gate is insulated and arranged on a side of the first active layer close to the base substrate, the orthographic projection of the first channel region on the base substrate at least partially overlaps with the orthographic projection of the second gate on the base substrate, and the orthographic projection of the second channel region on the base substrate at least partially overlaps with the orthographic projection of the first gate on the base substrate.

7. The transistor according to any one of claims 3 to 6, characterized in that: The first active layer further includes a first polar region and a second polar region, the second active layer further includes a third polar region and a fourth polar region, the first polar region is connected to both the first polar region and the third polar region, and the second polar region is connected to both the second polar region and the fourth polar region.

8. The transistor according to claim 2, characterized in that The semiconductor component includes a third active layer, and the third active layer includes a third channel region and a fourth channel region that are relatively arranged. The orthographic projection of the third channel region on the substrate and the orthographic projection of the fourth channel region on the substrate both at least partially overlap with the orthographic projection of the gate component on the substrate.

9. The transistor according to claim 8, characterized in that The gate assembly includes a third gate and a fourth gate, the third gate is insulated and arranged on a side of the third active layer away from the substrate, the fourth gate is insulated and arranged on a side of the third active layer close to the substrate, the orthographic projection of the third channel region on the substrate at least partially overlaps with the orthographic projection of the third gate on the substrate, and the orthographic projection of the fourth channel region on the substrate at least partially overlaps with the orthographic projection of the fourth gate on the substrate.

10. The transistor according to claim 9, characterized in that The third channel region is located on a side of the third active layer away from the substrate, and the fourth channel region is located on a side of the third active layer close to the substrate.

11. The transistor according to any one of claims 8 to 10, characterized in that: The third active layer further includes a fifth polar region and a sixth polar region, the first polar region is connected to the fifth polar region, and the second polar region is connected to the sixth polar region.

12. A method for preparing a transistor, characterized in that: include: Providing a substrate; A semiconductor component, a gate component, a first pole and a second pole are manufactured on the substrate, wherein the semiconductor component is connected to both the first pole and the second pole, and the semiconductor component includes at least two channel regions, and the orthographic projection of each of the channel regions on the substrate at least partially overlaps with the orthographic projection of the gate component on the substrate.

13. A driving substrate, characterized in that: A transistor comprising the transistor described in any one of claims 1 to 11, or a transistor prepared by the preparation method described in claim 12.

14. A display device, characterized in that: Includes the drive substrate as claimed in claim 13.

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