A method, device, automotive chip and medium for improving diagnostic coverage

Abstract

The present invention provides a method, device, automotive chip and medium for improving diagnostic coverage, including: step S1: obtaining gate-level netlist data of an IP without a security mechanism or whose security level does not reach a preset value, and storing it in a gate-level netlist one; step S2: obtaining a register one without security mechanism protection in the gate-level netlist one, and storing it in a register list one; step S3: in the register list one, obtaining a register two that needs to be verified and a corresponding verification logic based on a preset condition, and storing them in a register list two; step S4: inserting a verification register and a corresponding verification logic into the register two, and storing them in a gate-level netlist two; step S5: judging whether the functions of the gate-level netlist one and the gate-level netlist two are consistent, and if not, updating the verification logic corresponding to the register two; step S6: obtaining the IP diagnostic coverage and IP area in the gate-level netlist two, and whether the preset coverage and the preset area are reached, and if not, returning to step S3.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a method for improving diagnostic coverage, a device for improving diagnostic coverage, an automobile chip and a computer-readable storage medium. Background Art

[0002] With the rapid development of electric vehicles, higher and higher requirements are being placed on the safety and reliability of vehicles, and automotive chips therefore need to have corresponding safety level requirements. In the layered decomposition of safety goals, each IP in the automotive-grade chip has a corresponding safety goal, and diagnostic coverage is one of the specific indicators.

[0003] In the prior art, for SoC design, if it is necessary to improve the diagnostic coverage of a certain IP, some existing IPs are usually used or purchased for integration to reduce the development cycle. In addition, for automotive-grade chips, while realizing the chip functions, it is also necessary to minimize the failures caused by random hardware failures during the operation of the chip, so various safety mechanisms need to be added to synchronously detect / control these hardware failures. Different from the test coverage in chip testing, the diagnostic coverage, as an important indicator in functional safety, means the proportion of the failure rate detected or controlled by the safety mechanism implemented by the chip in the failure rate of hardware elements. However, many existing IPs on the market do not have corresponding safety mechanisms or have low safety levels. Direct integration will inevitably lower the overall diagnostic coverage of the chip, which will affect the subsequent automotive certification. That is, the existing technology cannot improve the diagnostic coverage of the IP without changing the original function of the IP, so that the chip as a whole can achieve the diagnostic coverage target.

[0004] Therefore, it is necessary to provide a method for improving diagnostic coverage, a device for improving diagnostic coverage, an automotive chip and a computer-readable storage medium to effectively solve the above problems. Summary of the invention

[0005] The present invention provides a method for improving diagnostic coverage, a device for improving diagnostic coverage, an automobile chip and a computer-readable storage medium.

[0006] An embodiment of the present invention provides a method for improving diagnosis coverage, including:

[0007] Step S1: Obtain gate-level netlist data of IPs without security mechanisms or whose security levels do not reach a preset value, and store them in gate-level netlist 1;

[0008] Step S2: obtaining a register 1 that is not protected by a security mechanism in the gate-level netlist 1, and storing it in a register list 1;

[0009] Step S3: in the register list 1, based on the preset conditions, obtain the register 2 that needs to be verified and the corresponding verification logic, and store the register 2 in the register list 2;

[0010] Step S4: inserting a check register and the corresponding check logic into the second register, and storing them in the second gate-level netlist;

[0011] Step S5: determining whether the functions of the gate-level netlist 1 and the gate-level netlist 2 are consistent, and if not, updating the check logic corresponding to the register 2;

[0012] Step S6: Obtain the IP diagnostic coverage and IP area in the gate-level netlist 2, and determine whether the IP diagnostic coverage reaches a preset coverage and whether the IP area reaches a preset area. If at least one of the conditions is not met, return to step S3.

[0013] Preferably, in step S2, simulation error injection is performed by VC_Z01X software to extract the register one from the gate-level netlist one.

[0014] Preferably, the check logic includes parity check or ECC check or TMR check.

[0015] Preferably, obtaining the register 2 that needs to be verified and the corresponding verification logic based on the preset conditions includes:

[0016] When the step 3 is first executed, 50% of the registers 1 in the register list 1 are obtained as the registers 2, and the check logic of all the registers 2 is configured as the parity check.

[0017] Preferably, the step of obtaining the register 2 that needs to be verified and the corresponding verification logic based on the preset conditions further includes:

[0018] When the condition of step S6 is not met and the process returns to step S3, if the IP diagnostic coverage in the gate-level netlist two does not reach the preset coverage, the proportion of register one in the register list one as register two is increased or part or all of the check logic is adjusted to the ECC check; if the IP area in the gate-level netlist two does not reach the preset area, the proportion of register one in the register list one as register two is reduced.

[0019] Preferably, in step S6, simulation error injection is performed by using VC_Z01X software to obtain the IP diagnostic coverage in the gate-level netlist 2.

[0020] Preferably, it also includes:

[0021] Step S7: verify the corresponding register 2 based on the verification logic, and obtain the diagnosis result of the IP in the gate-level netlist 2 based on the verification result of the register 2.

[0022] Furthermore, a device for improving diagnostic coverage is provided, comprising:

[0023] The acquisition module is used to execute step S1: acquiring gate-level netlist data of IP without security mechanism or whose security level does not reach a preset value, and storing it in gate-level netlist 1; step S2: acquiring register 1 without security mechanism protection in the gate-level netlist 1, and storing it in register list 1;

[0024] The verification processing module is used to execute step S3: in the register list 1, based on the preset conditions, obtain the register 2 that needs to be verified and the corresponding verification logic, and store the register 2 in the register list 2; step S4: insert the verification register and the corresponding verification logic into the register 2, and store them in the gate-level netlist 2;

[0025] The detection module is used to execute step S5: determine whether the functions of the gate-level netlist one and the gate-level netlist two are consistent, and if not, update the verification logic corresponding to the register two; step S6: obtain the IP diagnostic coverage and IP area in the gate-level netlist two, and determine whether the IP diagnostic coverage reaches the preset coverage and whether the IP area reaches the preset area. If at least one of the conditions is not met, return to step S3.

[0026] Furthermore, an automotive chip is provided, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above-described methods when executing the computer program.

[0027] Furthermore, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above-mentioned methods are implemented.

[0028] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0029] The method for improving diagnostic coverage, the device for improving diagnostic coverage, the automotive chip and the computer-readable storage medium provided by the embodiments of the present invention can improve the diagnostic coverage of the IP without changing the original function of the IP, so that the overall chip can achieve the diagnostic coverage target. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are some embodiments of the present invention, not all embodiments. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.

[0031] Figure 1 A schematic flow chart of a method for improving diagnostic coverage provided by an embodiment of the present invention;

[0032] Figure 2 A structural diagram of a method for improving diagnostic coverage by inserting verification logic in a netlist provided by an embodiment of the present invention;

[0033] Figure 3 A schematic diagram of the structure of a register group and parity check logic in a practical application scenario provided by an embodiment of the present invention;

[0034] Figure 4 A schematic diagram of a module of a device for improving diagnostic coverage provided by an embodiment of the present invention.

[0035] Description of reference numerals:

[0036] 10-device for improving diagnostic coverage; 11-acquisition module; 12-verification processing module; 13-detection module. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0039] Based on the problems existing in the prior art, the embodiments of the present invention provide a new method for improving diagnostic coverage, a device for improving diagnostic coverage, an automotive chip and a computer-readable storage medium.

[0040] Figure 1 A flow chart of a method for improving diagnostic coverage provided by an embodiment of the present invention. Figure 1As shown, an embodiment of the present invention provides a method for improving diagnosis coverage, including:

[0041] Step S1: Obtain gate-level netlist data of an IP without a security mechanism or whose security level does not reach a preset value, and store it in gate-level netlist 1.

[0042] In the specific implementation, there is no need to have an in-depth understanding of the IP, and the tool can be used to directly synthesize it into a gate-level netlist 1, which is convenient for subsequent register extraction. In this implementation, the preset value of the security level can be set based on actual needs. For example, the security level of the automotive chip includes four levels. In this implementation, level 2 can be set as the preset value, that is, IP of level 1 and IP without security mechanism are stored in gate-level netlist 1, so that the corresponding verification logic can be configured later to improve the diagnostic coverage.

[0043] Step S2: Obtain register one without security mechanism protection in gate-level netlist one, and store it in register list one.

[0044] In a specific implementation, error injection simulation can be performed through dedicated software (such as VC_Z01X), and it can be known which registers in the gate-level netlist 1 are not protected by corresponding security mechanisms. For these registers, their diagnostic coverage needs to be improved, so they are extracted to form a register list 1 for subsequent operations.

[0045] VC Z01X is a high-performance fault injection and simulation solution for multiple purposes that meets the ISO 26262 automotive functional safety standard. It provides fault injection capabilities to ensure the effectiveness of chip or IP error detection and can provide corresponding safety quality analysis reports.

[0046] Step S3: In register list one, based on a preset condition, obtain register two that needs to be verified and the corresponding verification logic, and store register two in register list two.

[0047] In the specific implementation, inserting the verification logic will increase the area of ​​the IP, thus affecting the overall area of ​​the system-on-chip (SoC). At the same time, different verification logics (such as parity check, error correction code (ECC), triple modular redundancy (TMR), etc.) have different occupied areas and diagnostic coverage benefits. Therefore, the register list 2 and the verification scheme in this step can be flexibly adjusted according to the safety goal to achieve a balance between diagnostic coverage and chip area.

[0048] For example, in the initial selection, only 50% of the registers in register list one can be extracted as register two, and all register twos are configured as parity check logic, so as to use this as a solution with better area occupation for subsequent steps.

[0049] Step S4: inserting a check register and corresponding check logic into register 2, and storing them in gate-level netlist 2.

[0050] In a specific implementation, the registers 2 in the register list 2 obtained in step S3 are grouped. After the grouping is completed, the corresponding check logic is inserted into each register group and stored in the gate-level netlist 2. Taking the insertion of parity check logic as an example, the relationship between the register group and the corresponding check logic is detailed in Figure 3 .

[0051] During the grouping process, only registers with the same clock source can be divided into the same register group. Otherwise, it will cause cross-clock synchronization errors in the chip and errors in the verification function.

[0052] Step S5: determine whether the functions of gate-level netlist 1 and gate-level netlist 2 are consistent, and if not, update the check logic corresponding to register 2.

[0053] In a specific implementation, a formal verification tool (such as VC Formal) can be used to detect the functional consistency of gate-level netlist 1 and gate-level netlist 2. If the verification result shows that the functions of gate-level netlist 1 and gate-level netlist 2 are consistent, step S6 is executed, otherwise step S51 is executed to update the verification logic corresponding to register 2 until the functions of gate-level netlist 1 and gate-level netlist 2 are consistent. Step S5 can ensure that the verification logic added by this solution does not affect the original function of the IP. The tool is used to ensure that after the verification logic is inserted, the function of the IP remains consistent with the original one, ensuring the correctness of the IP function.

[0054] Step S6: Obtain IP diagnostic coverage and IP area in gate-level netlist 2, and determine whether the IP diagnostic coverage reaches a preset coverage and whether the IP area reaches a preset area. If at least one of the conditions is not met, return to step S3.

[0055] In the specific implementation, the error injection software, such as VC_Z01X software, can be used to perform error injection simulation on the circuit again to obtain the IP diagnostic coverage in the gate-level netlist 2, that is, to obtain the diagnostic coverage data of the IP after inserting the parity check logic. In addition, the area of ​​the IP can also be obtained by using relevant software.

[0056] The two data obtained are compared with the set safety target and area target. If both meet the standards, the process of this solution is terminated. If not, return to step S3 to adjust register list 2, and repeat steps S3-S6 until the targets are met.

[0057] In some embodiments, when the condition in step S6 is not met and the process returns to step S3, if the IP diagnostic coverage in gate-level netlist 2 does not reach the preset coverage, the proportion of register 1 in register list 1 as register 2 is increased or part or all of the verification logic is adjusted to a solution with higher diagnostic coverage gain (such as ECC); if the IP area in gate-level netlist 2 does not reach the preset area, the proportion of register 1 in register list 1 as register 2 is reduced.

[0058] In a specific implementation, a step value may be set each time the proportion of register 1 in register list 1 as register 2 is increased, for example, 1%, 2%, 3%, 4%, 5%, 10%, etc. may be increased each time based on an initial value of 50%. The check logic of register 2 may also be changed to ECC check, etc. When the proportion of register 1 in register list 1 as register 2 is reduced, the proportion may be reduced by step values ​​such as 1%, 2%, 3%, 4%, 5%, 10%, etc.

[0059] For example, the structure of the IP after the verification logic is inserted in this solution is as follows Figure 2 shown. Figure 2 The upper half of is the original logic of the IP, and this part should not be affected during the parity check logic insertion process. In the process of step S3 and step S4, the register two in the structure is grouped.

[0060] Figure 2 The lower half of is the verification logic inserted in this solution. For each register group obtained in step S4, there is a corresponding verification logic corresponding to it. The specific corresponding relationship is as follows: Figure 3 In the functional consistency test of step S5, the objects of comparison are the gate-level netlist 1 and the gate-level netlist 2. Figure 2 The functional logic part of the IP is shown.

[0061] In some embodiments, the method for improving diagnostic coverage further includes: Step S7: verifying the corresponding register 2 based on the verification logic, and obtaining the diagnostic result of the IP in the gate-level netlist 2 based on the verification result of the register 2.

[0062] Specifically, Figure 2 and Figure 3As shown, each verification logic will have a compare error output. After combining the outputs of all verification logics with the logical "OR", the verification error signal of the IP is obtained. When the signal is high, it means that a random hardware failure has occurred inside the IP during the operation of the chip, thereby obtaining the IP diagnostic result.

[0063] Specifically, for each register group (DFF n- DFF n+7 ), there is a set of data input (D n –D n+7 ) and clock (CLK), and each register group also has a set of data output (Q n –Q n+7 ). The process implemented in this solution verifies the path from data input to data output, thereby improving the diagnostic coverage of IP.

[0064] Register group such as Figure 3 As shown in Register group n, the corresponding verification logic is as follows Figure 3 As shown in ParityLogic n (taking parity check as an example). Input the data of the register group (D n –D n+7 ) and data output (Q n –Q n+7 ) are XORed respectively to obtain D xor and Q xor , D xor After checking the register (DFFparity), Q is obtained. p_xor ,It should be noted that the clock of the check register should come from the clock (CLK) of the register group.

[0065] Q xor and Q p_xor By performing an XOR operation, a compare error signal (Compare Error) can be obtained. When the signal is high, it means that a random hardware failure has occurred in the register group or the check logic.

[0066] In summary, the method for improving diagnostic coverage provided by the embodiment of the present invention can significantly improve the diagnostic coverage of existing IP by inserting verification logic in the gate-level netlist. It can also avoid repeated development of functional IP, reduce development costs, and improve development efficiency. By continuously optimizing between diagnostic coverage and area cost, the area cost caused by functional safety can be minimized.

[0067] Furthermore, the present application also provides a device for improving the diagnostic coverage, such as Figure 4As shown, the device 10 for improving diagnostic coverage includes: an acquisition module 11, a verification processing module 12 and a detection module 13.

[0068] The acquisition module 11 is used to execute step S1: acquiring gate-level netlist data of IP without security mechanism or whose security level does not reach the preset value, and storing it in gate-level netlist 1; step S2: acquiring register 1 without security mechanism protection in the gate-level netlist 1, and storing it in register list 1;

[0069] The verification processing module 12 is used to execute step S3: in the register list 1, based on the preset conditions, obtain the register 2 that needs to be verified and the corresponding verification logic, and store the register 2 in the register list 2; step S4: insert the verification register and the corresponding verification logic into the register 2, and store them in the gate-level netlist 2;

[0070] The detection module 13 is used to execute step S5: determine whether the functions of the gate-level netlist 1 and the gate-level netlist 2 are consistent. If not, update the verification logic corresponding to the register 2; step S6: obtain the IP diagnostic coverage and IP area in the gate-level netlist 2, and determine whether the IP diagnostic coverage reaches the preset coverage and whether the IP area reaches the preset area. If at least one of the conditions is not met, return to step S3.

[0071] The device for improving diagnostic coverage provided in the present application can implement any embodiment of the method for improving diagnostic coverage described above.

[0072] Furthermore, the present application also provides an automotive chip, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the task scheduling method in any of the above embodiments when executing the computer program.

[0073] Furthermore, the present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the task scheduling method in any of the above embodiments are implemented.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for improving diagnostic coverage, characterized in that: include: Step S1: Obtain gate-level netlist data of IPs without security mechanisms or whose security levels do not reach a preset value, and store them in gate-level netlist 1; Step S2: Perform simulation error injection through VC_Z01X software to obtain register 1 without security mechanism protection in the gate-level netlist 1, and store it in register list 1; Step S3: in the register list 1, based on the preset conditions, obtain the register 2 that needs to be verified and the corresponding verification logic, and store the register 2 in the register list 2; Step S4: grouping the registers 2 in the register list 2, and the registers 2 with the same clock source are grouped into the same register group. After grouping, each register group has a corresponding check logic corresponding to it; inserting a check register and the corresponding check logic into the register 2 of each register group, and storing them in the gate-level netlist 2; Step S5: determining whether the IP function logics of the gate-level netlist 1 and the gate-level netlist 2 are consistent, and if not, updating the verification logic corresponding to the register 2 until the functions of the gate-level netlist 1 and the gate-level netlist 2 are consistent, and then executing step 6; Step S6: Obtain the IP diagnostic coverage and IP area in the gate-level netlist 2, and determine whether the IP diagnostic coverage reaches a preset coverage and whether the IP area reaches a preset area. If at least one of the conditions is not met, return to step S3 to adjust the register list 2, and repeat steps S3-S6 until the diagnostic coverage target is met; Step S7: verifying the corresponding register 2 based on the verification logic; each register group corresponds to a group of data input and a group of data output, and verifying the path from the data input to the data output; The data input and data output of the register group are XORed to obtain Dxor and Qxor respectively, Dxor is passed through the check register to obtain Qp_xor, Qxor and Qp_xor are XORed to obtain a comparison error signal, and the diagnosis result of the IP in the gate-level netlist 2 is obtained.

2. The method for improving diagnostic coverage according to claim 1, characterized in that: The check logic includes parity check, ECC check or TMR check.

3. The method for improving diagnostic coverage according to claim 2, characterized in that: The register 2 that needs to be checked and the corresponding checking logic obtained based on the preset conditions include: When the step S3 is first executed, 50% of the registers 1 in the register list 1 are obtained as the registers 2, and the check logic of all the registers 2 is configured as the parity check.

4. The method for improving diagnostic coverage according to claim 3, characterized in that: The second register that needs to be checked and the corresponding check logic are obtained based on the preset conditions, and further includes: When the condition of step S6 is not met and the process returns to step S3, if the IP diagnostic coverage in the gate-level netlist two does not reach the preset coverage, the proportion of register one in the register list one as register two is increased or part or all of the check logic is adjusted to the ECC check; if the IP area in the gate-level netlist two does not reach the preset area, the proportion of register one in the register list one as register two is reduced.

5. The method for improving diagnostic coverage according to claim 1, characterized in that: In the step S6, simulation error injection is performed by using VC_Z01X software to obtain the IP diagnosis coverage in the gate-level netlist 2.

6. A device for improving diagnostic coverage, characterized in that: include: An acquisition module, used to execute step S1: acquiring gate-level netlist data of an IP without a security mechanism or whose security level does not reach a preset value, and storing it in a gate-level netlist 1; Step S2: Perform simulation error injection through VC_Z01X software to obtain register 1 without security mechanism protection in the gate-level netlist 1, and store it in register list 1; The verification processing module is used to execute step S3: in the register list 1, based on the preset conditions, obtain the register 2 that needs to be verified and the corresponding verification logic, and store the register 2 in the register list 2 c; step S4: group the registers 2 in the register list 2, and the registers 2 with the same clock source are divided into the same register group. After the grouping is completed, each register group has a corresponding verification logic corresponding to it; insert the verification register and the corresponding verification logic into the register 2 of each register group, and store them in the gate-level netlist 2; step S7: verify the corresponding register 2 based on the verification logic; each register group corresponds to a group of data input and a group of data output, and the path from the data input to the data output is verified; Performing XOR operation on the data input and data output of the register group to obtain Dxor and Qxor respectively, performing XOR operation on Dxor through the check register to obtain Qp_xor, performing XOR operation on Qxor and Qp_xor to obtain a comparison error signal, and obtaining the diagnosis result of the IP in the gate-level netlist 2; The detection module is used to execute step S5: determine whether the IP functional logics of the gate-level netlist one and the gate-level netlist two are consistent. If not, update the verification logic corresponding to the register two until the functions of the gate-level netlist one and the gate-level netlist two are consistent, and then execute step 6; step S6: obtain the IP diagnostic coverage and IP area in the gate-level netlist two, and determine whether the IP diagnostic coverage reaches the preset coverage and whether the IP area reaches the preset area. If at least one of the conditions is not met, return to step S3 to adjust the register list two, and repeat steps S3-S6 until the diagnostic coverage target is met.

7. An automotive chip, comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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