Array substrate, display device and manufacturing method

Abstract

The invention discloses an array substrate, a display device and a manufacturing method. The array substrate of one embodiment comprises a plurality of data lines which are arranged in an array along a first direction, wherein each data line extends along a second direction intersected with the first direction; the grid lines are located in the display area and arranged in the second direction, each grid line extends in the first direction, and the grid lines and the data lines are arranged in an insulated mode; the pixel group is located in a pixel region defined by intersection of two adjacent data lines and two adjacent grid lines; wherein the pattern shapes of the orthographic projections of the grid line parts, located in different pixel areas, of the same grid line on the substrate of the array substrate are the same, the length of the grid line in the second direction is the width of the grid line, and the length of the grid line in the second direction is the width of the grid line at the positions, corresponding to the same pattern shape, of the grid line parts in the different pixel areas. The first grid line width of the grid line part in the edge area of the display area is smaller than the second grid line width of the grid line part in the central area of the display area.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more specifically, to an array substrate, a display device, and a manufacturing method thereof. Background Art

[0002] In the design of related display products, such as Figure 1 This is a schematic diagram of Single Gate pixel arrangement, such as Figure 1 As shown, the data lines D1 - D7 and the gate lines G1 - G3 intersect to form pixel regions, and only one pixel 30 ′ is defined in each pixel region. Figure 2 for Figure 1 The schematic diagram of the COF (Chip On Film) binding structure corresponding to the pixel arrangement schematic diagram is as follows: Figure 2 As shown, a fan-out area is designed between the data driving module 50 and the display panel. A plurality of binding parts 51 are arranged in the fan-out area to realize signal transmission. The binding parts 51 are arranged on the long side of the display panel and are relatively large in number.

[0003] With the demand for lower production costs, Dual Gate products were designed. The pixel arrangement of Dual Gate products is as follows: Figure 3 As shown, Figure 4 As shown, it can be seen that the number of binding parts 51 used by Dual Gate is reduced to half of the number of binding parts 51 used by Single Gate.

[0004] However, in the manufacturing process of the Dual Gate product, a capacitance delay (RC delay) effect will occur in the driving circuit of the array substrate, thereby affecting the uniformity of the in-plane charging rate of the display area. Summary of the invention

[0005] An object of the present invention is to provide an array substrate, a display device and a manufacturing method to solve at least one of the problems existing in the prior art.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] A first aspect of the present invention provides an array substrate, the array substrate comprising:

[0008] A plurality of data lines arranged in an array along a first direction in the display area, each data line extending along a second direction intersecting the first direction;

[0009] a plurality of gate lines arranged along the second direction in the display area, each gate line extending along the first direction, and the gate lines being insulated from the data lines; and

[0010] A pixel group is located in a pixel area defined by the intersection of two adjacent data lines and two adjacent gate lines;

[0011] in,

[0012] The orthographic projection patterns of the gate line portions of the same gate line located in different pixel regions on the substrate of the array substrate are the same.

[0013] The length of the gate line in the second direction is the gate line width,

[0014] At positions where gate line portions in different pixel regions correspond to the same pattern shape, a first gate line width of a gate line portion located in an edge region of the display region is smaller than a second gate line width of a gate line portion located in a central region of the display region.

[0015] Furthermore, each of the pixel groups includes a first pixel and a second pixel arranged along the first direction, and each pixel corresponds to a pixel electrode.

[0016] Two pixel groups adjacent to each other in the first direction share the same data line as a boundary of the pixel area, and two pixel electrodes of the first pixel and the second pixel are driven by the same data line;

[0017] Two gate lines are arranged between two adjacent pixel groups in the second direction, and a first pixel and a second pixel in the same pixel group are respectively driven by the two gate lines defining the pixel area.

[0018] Furthermore, the first pixel and the second pixel in the same pixel group have different colors.

[0019] In two adjacent pixel groups in the first direction, the color of the first pixel in one pixel group is different from the color of the first pixel in the other pixel group, and the color of the second pixel in one pixel group is different from the color of the second pixel in the other pixel group.

[0020] Furthermore, the array substrate further includes:

[0021] a first driving electrode electrically connected to each pixel electrode,

[0022] a second driving electrode corresponding to the first driving electrode, the second driving electrode being connected to the data line; and

[0023] A plurality of ground lines are arrayed in the first direction, each ground line is located between a first pixel and a second pixel in the same pixel group, and is extended along the second direction.

[0024] Furthermore, the orthographic projection of the gate line portion on the substrate includes:

[0025] A first overlapping projection overlapping with an orthographic projection of the data line on the substrate;

[0026] a second overlapping projection overlapping with the orthographic projection of the ground line on the substrate;

[0027] a third overlapping projection overlapping with the orthographic projection of the first driving electrode or the second driving electrode on the substrate;

[0028] a first gap projection located between the first overlapping projection and the second overlapping projection and not overlapping with the orthographic projection of the pixel electrode on the substrate; and

[0029] a second gap projection located between the second overlapping projection and the third overlapping projection and not overlapping with the orthographic projection of the pixel electrode on the substrate;

[0030] The width difference between the first gate line width and the second gate line width is set at one or more of the first overlapping projection, the second overlapping projection, the first gap projection or the second gap projection.

[0031] Furthermore, the edge area of ​​the display area includes multiple gate line portions of the same gate line, and in the direction from the edge area of ​​the display area to the central area of ​​the display area, the first gate line width of the multiple gate line portions of the same gate line gradually increases.

[0032] Furthermore, in the first direction, in the same gate line, the number of the gate line portions located in the edge region of the display area is 1 / 4 to 1 / 2 of the total number of the gate line portions in the display area.

[0033] Furthermore, the width difference between the second gate line width and the first gate line width is 1.5 to 3 micrometers.

[0034] Furthermore, the minimum value of the first gate line width is greater than or equal to 7 micrometers.

[0035] Further, a distance between a boundary of an orthographic projection of the pixel electrode on the substrate parallel to the second direction and a boundary of an orthographic projection of the ground line on the substrate parallel to the second direction is a first distance,

[0036] The distance between the boundary of the orthographic projection of the pixel electrode on the substrate parallel to the second direction and the boundary of the orthographic projection of the data line on the substrate parallel to the second direction is the second distance,

[0037] The first distance is smaller than the second distance.

[0038] Furthermore, the array substrate further includes:

[0039] A data driving module, used for outputting data signals;

[0040] A plurality of metal connection lines located in the fan-out area, one end of each of the metal connection lines being connected to the output end of the data driving module and the other end being connected to the data line of the display area;

[0041] The first connection line width of the metal connection line corresponding to the data line in the edge area of ​​the display area is greater than the second connection line width of the metal connection line corresponding to the data line in the center area of ​​the display area.

[0042] Furthermore, in the first direction, the number of metal connection lines corresponding to the data lines in the edge region of the display area is 1 / 4 to 1 / 2 of the total number of metal connection lines in the fan-out region.

[0043] A second aspect of the present invention provides a display device, comprising the array substrate described in the first aspect of the present invention.

[0044] A third aspect of the present invention provides a method for manufacturing the array substrate according to the first aspect of the present invention, the method comprising:

[0045] A plurality of data lines arranged in an array along a first direction are formed on the substrate at positions corresponding to the display area, and each data line extends along a second direction intersecting the first direction;

[0046] A plurality of gate lines arranged along the second direction and insulated from the data lines are formed on the substrate at positions corresponding to the display area, each gate line extending along the first direction, gate line portions of the same gate line located in different pixel areas have the same pattern shape of the orthographic projection on the substrate of the array substrate, the length of the gate line in the second direction is the gate line width, and at positions of the gate line portions in different pixel areas corresponding to the same pattern shape, a first gate line width of the gate line portion located in the edge area of ​​the display area is smaller than a second gate line width of the gate line portion located in the center area of ​​the display area;

[0047] A pixel group is formed in a pixel area defined by the intersection of two adjacent data lines and two adjacent gate lines.

[0048] The beneficial effects of the present invention are as follows:

[0049] In an embodiment of the present invention, the gate line width of the same gate line in different pixel areas is designed so that the gate line width of the gate line portion in the edge area of ​​the display area is smaller than the gate line width in the central area of ​​the display area. Through this setting, the impedance difference between the edge area of ​​the display area and the central area of ​​the display area can be improved, and the delay effect can be reduced, thereby improving the uniformity of the charging rate in the surface of the display product. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0051] Figure 1A schematic diagram showing pixel arrangement of a single-gate product of the related art;

[0052] Figure 2 A schematic diagram showing a driving structure of a single-gate display product of related art;

[0053] Figure 3 A schematic diagram showing pixel arrangement of a dual-gate product of the related art;

[0054] Figure 4 A schematic diagram showing a driving structure of a dual-gate product of related art;

[0055] Figure 5 A schematic structural diagram showing an orthographic projection of a gate line on a substrate according to an embodiment of the present invention;

[0056] Figure 6 A schematic diagram showing a structure of different gate line width designs according to an embodiment of the present invention;

[0057] Figure 7 and Figure 8 A schematic diagram showing the structure of pixel arrangement and wiring design according to different embodiments of the present invention;

[0058] Fig. 9 A schematic diagram showing the structure of a wiring design within a pixel group according to an embodiment of the present invention;

[0059] Fig.10 A schematic diagram showing the layout of data lines and ground lines according to an embodiment of the present invention;

[0060] Fig.11 A schematic diagram showing a layout of an array substrate according to an embodiment of the present invention;

[0061] Fig.12 A schematic diagram showing the width of a gate line portion in an edge region of a display area according to an embodiment of the present invention;

[0062] Fig.13 A schematic diagram showing the width of a gate line portion in a central area of ​​a display area according to an embodiment of the present invention;

[0063] Fig.14 A schematic diagram showing the distance between the ground line and the pixel electrode according to an embodiment of the present invention;

[0064] Fig.15 A schematic diagram showing the distance between a data line and a pixel electrode according to an embodiment of the present invention;

[0065] Fig.16 A schematic diagram showing the width design of the metal connection line in the fan-out region according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0066] In order to explain the present invention more clearly, the present invention is further described below in conjunction with embodiments and drawings. Similar components in the drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the content specifically described below is illustrative rather than restrictive, and the protection scope of the present invention should not be limited thereto.

[0067] The delay effect of the driving circuit of the array substrate will cause the problem of uneven charging rate and uneven color display in the plane. In the process of driving the array substrate to display, each metal wiring has a certain impedance, so the data signal voltage is bound to have a certain delay distortion during its transmission, resulting in the potential on the pixel electrode of the pixel unit not being able to fully reach the potential of the data signal voltage output by the data driving module 50.

[0068] Therefore, due to the delay effect of metal routing, the charging rates of pixels in different areas of the display area will be different, resulting in different pixel display brightness, contrast, and color mixing effects in different areas, thereby affecting the display effect and electrical performance of the display product.

[0069] In view of this, the present invention provides an array substrate, a manufacturing method thereof, and a display device.

[0070] like Figure 5 ~such as Fig. 9 As shown, the first embodiment of the present invention provides an array substrate, the array substrate comprising:

[0071] A plurality of data lines 10 are sequentially arranged along a first direction in the display area AA, and each data line 10 extends along a second direction intersecting the first direction. For example, the first direction of the embodiment of the present invention is Figure 6 The second direction is Figure 6 In one specific example, Figure 7 The end of the data line 10 is shown connected to Figure 6 The binding portion 51 located in the fan-out region corresponds one-to-one with the metal connection line 60 of the binding portion 51 to achieve signal transmission with the data driving module 50 .

[0072] a plurality of gate lines 20 arranged in sequence along the second direction in the display area AA, each gate line 20 extending along the first direction, and the gate lines 20 being insulated from the data lines 10; and

[0073] The pixel group 30 is located in a pixel area defined by the intersection of two adjacent data lines 10 and two adjacent gate lines 20 .

[0074] In an embodiment of the present invention, each of the gate lines 20 includes a plurality of gate line portions 21 located in different pixel areas. The gate line portion 21 is defined as a routing portion of the gate line 20 in different pixel areas. Since the gate line 20 is designed horizontally in a first direction, i.e., the row direction, and the data line 10 is designed vertically in a second direction, i.e., the column direction, the data line 10 and the gate line 20 intersect to form a pixel area defining a pixel group 30. The data line 10 decomposes a gate line 20 into a plurality of gate line portions 21, i.e., the area of ​​the gate line 20 corresponding to the boundary of the pixel area parallel to the first direction is the gate line portion 21.

[0075] In the solution of this embodiment, Figure 5 As shown, the gate line portions 21 of the same gate line 20 located in different pixel regions have the same or approximately the same pattern shapes of the orthographic projections on the substrate of the array substrate. Considering the routing design of the display area AA, Figure 5 The special-shaped structural design of the gate line portion 21 in a pixel area is shown. The shapes of the gate line portions 21 of the same gate line 20 located in the remaining pixel areas are the same or similar. For example, the shapes of multiple gate line portions 21 in the central area of ​​the display area are the same. Due to the gate line width design of the embodiment of the present invention, the shape of the gate line portion 21 in the edge area of ​​the display area and the shape of the gate line portion 21 in the central area of ​​the display area are similar.

[0076] It is worth noting that the orthographic projection patterns of the present embodiment that have the same shape refer to the orthographic projection patterns of different pixel areas of the same gate line 20, such as Figure 5 As shown, the grid lines 20 located in different rows have different orthographic projections, for example, Figure 5 As shown, two adjacent rows of gate lines 20 are arranged in the gap between the boundaries of two adjacent pixel regions 30 in the second direction (the pixel region 30a located above and not completely shown and the pixel region 30b adjacent to the pixel region 30), for example Figure 5 As shown in the figure, a row of gate lines 20a near one side of the pixel area 30a, and a second row of gate lines 20b near one side of the pixel area 30b, in the first direction, the first row of gate lines 20a and the second row of gate lines 20b are decomposed into a first row of gate line portions 21a (dotted area in the figure) and a second row of gate line portions 21b (dotted area in the figure) at a position corresponding to the pixel area 30a or the pixel area 30b, and the orthographic projections of the two gate line portions at this position, i.e., the orthographic projections of the first row of gate line portions 21a and the second row of gate line portions 21b are Figure 5 The symmetry point X shown is a central symmetric design.

[0077] Further, the two gate line portions on both sides of the same pixel area are symmetrically designed with the axis along the first direction of the pixel area. In a specific example, in the second direction, the two sides of the pixel area 30b are respectively provided with two rows of gate lines, i.e. the second row of gate lines 20b and the third row of gate lines 20c. Similarly, in the first direction, the third row of gate lines 20c is decomposed into the gate line portion 21c (dashed line area in the figure) of the third row at the position corresponding to the pixel area 30a, the gate line portion 21a of the first row and the gate line portion 21c of the third row on both sides of the same pixel area 30b are symmetrically designed with the axis parallel to the first direction of the pixel area 30b, the gate line portion 21a of the first row and the gate line portion 21c of the third row are axisymmetrically designed, and the above-mentioned setting can maximize the space utilization rate of routing.

[0078] like Figure 6 , Fig.12 as well as Fig.13 As shown, the length of the gate line 20 in the second direction is the gate line width. Figure 5 As shown in the structure of the gate line 20, the gate line 20 has different shapes in the structure along the first direction. Therefore, the gate line width described in the embodiment of the present invention is the length of the gate line in the second direction, that is, the length of the structure of the gate line 20 at different positions in the second direction is defined by the gate line width.

[0079] The embodiment of the present invention designs the gate line width. At the same distance L between the gate line portions 21 in different pixel areas and the boundary of the data line 10, the first gate line width d1 of the gate line portion 21 located in the edge area of ​​the display area is smaller than the second gate line width d2 of the gate line portion 21 located in the center area of ​​the display area.

[0080] like Figure 6 As shown, the width of the gate line portion 21 located in the edge area of ​​the display area in the second direction of the embodiment of the present invention is defined as the first gate line width d1, that is, Fig.12 As shown in FIG. 1 , the gate line portion 21 at the edge of the display area is designed as a special-shaped structure, and the width mark at each location is the first gate line width, and the first gate line width d1 of the gate line portion 21 at different locations can be different values. Based on the same principle, the second gate line width d2 is the width mark of the gate line portion 21 located in the center area of ​​the display area in the second direction, such as Fig.13 As shown, the second gate line width d2 of the gate line portion 21 at different positions may have different values.

[0081] The embodiment of the present invention is described at the position where the gate line portion 21 in different pixel regions is at the same distance L from the boundary of the data line 10.

[0082] Fig.12 The corresponding position of 211 Fig.13 The vertical distance between the position corresponding to 211 and the data line 10 is L1. Fig.12 The position corresponding to 212 and Fig.13 The vertical distance between the position corresponding to 212 and the data line 10 is L2. Fig.12 The position corresponding to 213 and Fig.13 The vertical distance between the position corresponding to 213 and the data line 10 is L3. Fig.12 The position corresponding to 214 and Fig.13 The vertical distance between the position corresponding to 214 and the data line 10 is L4. Fig.12 The position corresponding to 215 and Fig.13 The vertical distance between the position corresponding to 215 and the data line 10 is L5, and at the position where the different gate line portions 21 have the same vertical distance with the data line 10 on the same side, the first gate line width d1 is smaller than the second gate line width d2. Therefore, in this embodiment, there are multiple gate line portions 21 in different pixel areas, but the positions where the boundary distance L between them and the data line 10 on the same side is the same are the same.

[0083] In an embodiment of the present invention, each signal line of the display area is designed. For example, the gate line width of the same gate line 20 in different pixel areas is designed so that the gate line width of the gate line portion 21 in the edge area AA01 of the display area is smaller than the gate line width in the central area AA02 of the display area. Through this setting, the impedance difference between the edge area AA01 of the display area and the central area AA02 of the display area can be improved, the delay effect can be reduced, and the uniformity of the charging rate in the surface of the display product can be improved.

[0084] In an optional embodiment, if Figures 5 to 9 As shown, each pixel group 30 includes a first pixel 31 and a second pixel 32 arranged along the first direction, and each pixel corresponds to a pixel electrode 33.

[0085] Two pixel groups 30 adjacent to each other in the first direction share the same data line 10 as the boundary of the pixel area, and two pixel electrodes 33 of the first pixel 31 and the second pixel 32 are driven by the same data line 10;

[0086] Two gate lines 20 are arranged between two adjacent pixel groups 30 in the second direction, and a first pixel 31 and a second pixel 32 in the same pixel group 30 are driven by the two gate lines 20 defining the pixel area, respectively.

[0087] The wiring layout design of the embodiment of the present invention enables two pixels in each pixel group 30 to share one data line 10, and each row of pixel groups 30 corresponds to two gates. Through this setting, the number of data lines 10 (the number of binding parts 51) is halved, which can reduce the cost of the data driving module connected to the data line 10.

[0088] In the embodiment of the present invention, the two pixel electrodes 33 of the first pixel 31 and the second pixel 32 are driven by the same data line 10, which can be as follows: Figure 7 The two pixel electrodes 33 of the first pixel 31 and the second pixel 32 of the different pixel groups 30 shown are driven by the same data line 10, for example Figure 7 As shown, the second pixel 32 of the first pixel group 30a and the first pixel 31 of the second pixel group 30b in the first row are driven by the same data line 10 , and the second pixel 32 of the second pixel group 30b and the first pixel 31 of the third pixel group 30c are driven by the same data line 10 .

[0089] In another embodiment, Figure 8 As shown, the two pixel electrodes 33 of the first pixel 31 and the second pixel 32 are driven by the same data line 10. Alternatively, the first pixel 31 and the second pixel 32 in the same pixel group 30 may be driven by the same data line 10. For example, Figure 8 As shown, the first pixel 31 and the second pixel 32 in each pixel group 30 of the first row are driven by the same data line 10. Those skilled in the art design the wiring according to actual applications, which will not be repeated here.

[0090] In an optional embodiment, if Figure 7 and Figure 8 As shown, the colors of the first pixel 31 and the second pixel 32 in the same pixel group 30 are different.

[0091] In two adjacent pixel groups 30 in the first direction, the color of the first pixel 31 in one pixel group 30 is different from the color of the first pixel 31 in the other pixel group 30, and the color of the second pixel 32 in one pixel group 30 is different from the color of the second pixel 32 in the other pixel group 30.

[0092] Since the pixel group 30 of the embodiment of the present invention is set to two pixels, and the pixel colors for realizing light emission need to be red, green and blue, the embodiment of the present invention designs the arrangement of pixels of different colors in the pixel group 30, that is, among the four pixels of two adjacent pixel groups 30, the colors of three pixels are different, there is a pixel of the same color, and the distance between the two pixels of the same color among the four pixels is the farthest. In an example, Figure 7 As shown, the color arrangement of the first pixel group 30a and the second pixel group 30b located in the first row is: the first pixel 31 of the first pixel group 30a is red, the second pixel 32 of the first pixel group 30a is green, the first pixel 31 of the second pixel group 30b is blue, and the second pixel 32 of the second pixel group 30b is red, thereby forming a complete light-emitting unit.

[0093] Based on the arrangement of the pixel group 30 and the wiring arrangement of the display area AA in the above embodiment of the present invention, the embodiment of the present invention further designs the width of the gate line portion 21 on the basis of the above design.

[0094] like Fig.12 The structure of a gate line portion 21 is shown. In the first direction, it is located at the edge of the display area. Each gate line portion can be Fig.12 In this structure, at the same position of each gate line portion 21, the first gate line width d1 is the same.

[0095] In an optional embodiment, the display area edge area AA01 includes multiple gate line portions 21 of the same gate line 20, and in the direction from the display area edge area AA01 to the display area center area AA02, the first gate line width d1 of the multiple gate line portions 21 of the same gate line 20 at the same position gradually increases.

[0096] It can be understood that the first gate line width d1 of the multiple gate line portions 21 at the same position of the embodiment of the present invention gradually increases, which is the setting of the multiple gate line portions 21 of the same gate line 20, that is, different from designing the multiple gate line portions 21 in the edge area of ​​the display area in the first direction in a structurally repeated manner, in this embodiment, the first gate line width d1 of the multiple gate line portions 21 at the same position is designed to increase toward the center area of ​​the display area.

[0097] It is worth noting that the increase in the first gate line width described in the embodiment of the present invention is for the same position of different gate line parts. In a specific example, for Fig.12 In the dotted area corresponding to 212 shown in FIG. 1 , in the direction from the edge to the center of the display area AA, the first gate line width d1 of the plurality of gate line portions 21 located in the edge area AA01 of the display area at the position is set to 7.2 microns, 8.2 microns and 9.2 microns in sequence. Fig.12 In the dotted area corresponding to 214 shown, in the direction from the edge to the center of the display area AA, the first gate line width d1 of the multiple gate line portions 21 located in the edge area AA01 of the display area at this position is set to 19.7 microns, 20.7 microns and 21.7 microns respectively, realizing a gradually increasing design of the first gate line width d1 of the multiple gate line portions at the same position, so as to improve the charging rate uniformity in the direction from the edge area AA01 of the display area to the center area AA02 of the display area.

[0098] Based on the above design, although the first gate line width of the gate line portion 21 located in the edge area AA01 of the display area at the same position is a gradually increasing design, for the same position, the maximum value of the first gate line width d1 of the gate line portion 21 located in the edge area AA01 of the display area is still smaller than the second gate line width d2 of the gate line portion 21 located in the central area AA02 of the display area.

[0099] That is, still Fig.12 Taking the dotted line area corresponding to 212 as an example, the maximum value of the first gate line width of the gate line portion 21 located in the edge area AA01 of the display area is 9.2 microns, which is less than Fig.13 The second gate line width of the gate line portion 21 located in the central area AA02 of the display area is shown to be 10.2 micrometers, so as to improve the uniformity of the charging rate in the direction from the edge area AA01 of the display area to the central area AA02 of the display area.

[0100] In an optional embodiment, in the first direction, in the same gate line 20, the number of the gate line portions 21 located in the edge area AA01 of the display area is 1 / 4 to 1 / 2 of the total number of data lines 10 connected to the metal connecting lines 60 of the binding portion 50 located at the edge.

[0101] like Figure 6 As shown, a plurality of binding parts 51 are sequentially arranged along the first direction in the fan-out area, and each of the binding parts 51 includes a plurality of metal connecting wires 60, one end of each of the metal connecting wires 60 is connected to the output end of the data driving module 50, and the other end is connected to the data line 10 of the display area AA, that is, the plurality of metal connecting wires 60 of a binding part 51 are respectively connected to the plurality of data lines 10 one by one, and a horizontally arranged gate line 20 is decomposed into a plurality of gate line parts 21 by the plurality of vertically arranged data lines 10. Therefore, the embodiment of the present invention designs the gate line part 21 according to the number of data lines 10, and the data lines of display products of different sizes have different structures. Therefore, the present embodiment takes the number of data lines 10 connected to the binding part 51 located at the edge as the design basis, and limits the edge area AA01 of the display area, the number of data lines located in the edge area of ​​the display area, and the number of gate line parts, so that the scheme of the embodiment of the present invention has wide applicability.

[0102] In a specific example, if Figure 6As shown, the embodiment of the present invention is provided with 6 binding parts 51. The scheme for designing the width of the gate line part 21 of the embodiment is designed for the area of ​​the data line 10 connected to the first binding part 51 and the sixth binding part 51. The embodiment designs the number of gate line parts 21 located in the edge area AA01 of the display area. For example, the binding part 50 located at the edge includes 960 metal connecting lines 60, and the number of data lines corresponding to the metal connecting lines 60 located in the edge area AA01 of the display area is also 960. Under this structure, the number of gate line parts 20 designed for width is 240 to 480, for example, preferably 1 / 3, that is, 320. The edge area AA01 of the display area of ​​the embodiment can be as follows Figure 6 The left edge as shown or Figure 6 One or both right edges shown are designed according to the actual application.

[0103] In an optional embodiment, the width difference between the second gate line width d2 and the first gate line width d1 is 1.5 to 3 microns. Through this setting, the overall charging rate uniformity of the display area AA can be guaranteed on the basis of ensuring the process accuracy. In a specific example, if the second gate line width d2 is 10 microns, the first gate line width d1 can be set at 7 to 8.5 microns.

[0104] Furthermore, the embodiment of the present invention designs the minimum value of the first gate line width d1 and sets the minimum value of the first gate line width d1 to be greater than or equal to 7 micrometers, thereby effectively ensuring the in-plane uniformity of the charging rate while ensuring the process.

[0105] In an optional embodiment, if Fig. 9 and Fig.10 As shown, the array substrate further includes:

[0106] The first driving electrode 34 is electrically connected to each pixel electrode 33.

[0107] a second driving electrode 35 corresponding to the first driving electrode 34 , the second driving electrode 35 being connected to the data line 10 ; and

[0108] A plurality of ground lines 40 are arranged in an array in the first direction. Each ground line 40 is located between a first pixel 31 and a second pixel 32 of a same pixel group 30 and extends along the second direction.

[0109] In an embodiment of the present invention, the first driving electrode 34 may be a source or a drain, and the second driving electrode 35 may be a drain or a source. When the gate line 20 is connected to the gate driving signal and the first driving electrode 34 and the second driving electrode 35 are turned on, the data line 10 transmits the data signal output by the data driving module. The data signal is transmitted to the pixel electrode 33 through the turned-on first driving electrode 34 and the second driving electrode 35, thereby realizing the lighting of the first pixel 31 and the second pixel 32.

[0110] The ground line 40 of the embodiment of the present invention is used to access the VCOM signal, that is, the ground sensing signal, and a ground line 40 is provided in each pixel group 30, that is, the ground line 40 extends longitudinally like the data line 10. In this embodiment, the ground line 40 and the data line 10 are made of the same material, thereby improving the process efficiency.

[0111] Fig.10 The structure of the orthographic projection of the data line 10 , the first driving electrode 34 , the second driving electrode 35 , and the ground line 40 on the substrate according to one embodiment of the present invention is shown. Figure 5 FIG. 2 shows a schematic structural diagram of a gate line 20 according to an embodiment of the present invention. Figure 5 The grid lines 20 and Fig.10 The layout structure of the overlapping orthographic projections formed by the various routing lines is as follows Fig.11 shown.

[0112] like Fig.11 As shown, in an optional embodiment, the orthographic projection of the gate line portion 21 on the substrate includes:

[0113] A first overlapping projection 211 overlapping with the orthographic projection of the data line 10 on the substrate;

[0114] A second overlapping projection 212 overlapping with the orthographic projection of the ground line 40 on the substrate;

[0115] a third overlapping projection 213 overlapping with the orthographic projection of the first driving electrode 34 or the second driving electrode 35 on the substrate;

[0116] a first gap projection 214 located between the first overlapping projection 211 and the second overlapping projection 212 and not overlapping with the orthographic projection of the pixel electrode 33 on the substrate; and

[0117] A second gap projection 215 located between the second overlapping projection 212 and the third overlapping projection 213 and not overlapping with the orthographic projection of the pixel electrode 33 on the substrate;

[0118] The width difference between the first gate line width d1 and the second gate line width d2 is set at one or more of the first overlapping projection 211 , the second overlapping projection 212 , the first gap projection 214 , or the second gap projection 215 .

[0119] Based on the above embodiments, the positive projection of the gate line portion 21 in a pixel area is an irregular structure, and the laterally extended gate line portion 21 forms different overlapping projections with other wirings, and the gate line width of the embodiment of the present invention has different design schemes at different positions of the gate line portion 21.

[0120] For example, Fig.12 The structure design of the overlapping projection of the edge area AA01 of the display area is shown. Fig.13 The structural design of the overlapping projections of the central area AA02 of the display area is shown, and different gate line width designs are provided at the same positions of the gate line portions 21 of the two areas.

[0121] It is worth mentioning that Fig.12 and Fig.13 The screenshot location is Fig.11 The pixel areas on both sides of the data line 10.

[0122] In a specific example, at the second overlapping projection 212 formed by the gate line portion 21 and the ground line 40, the width of the gate line portion 21 at this position can be designed differently. For example, the width of the gate line portion 21 at the edge area AA01 of the display area at this position is set to 7.2 microns. Fig.13 As shown, at the same second overlapping projection 212 position of the gate line portion 21 located in the central area AA02 of the display area, the width of the gate line portion 21 at this position is set to 10.2 micrometers.

[0123] In another example, at the first overlapping projection 211 overlapping with the orthographic projection of the data line 10 on the substrate, the width of the gate line portion 21 at this position can be designed differently. For example, the width of the gate line portion 21 at the edge area AA01 of the display area at this position is set to 7.2 microns. Fig.13 As shown, at the same first overlapping projection 211 position of the gate line portion 21 located in the central area AA02 of the display area, the width of the gate line portion 21 at this position is set to 10.2 micrometers.

[0124] At the position of the first gap projection 214 located between the first overlapping projection 211 and the second overlapping projection 212 and not overlapping with the orthographic projection of the pixel electrode 33 on the substrate, the width of the gate line portion 21 at this position can be designed differently. For example, the width of the gate line portion 21 at this position located in the edge area AA01 of the display area is set to 19.7 microns. Fig.13As shown, at the same projection position of the gate line portion 21 located in the central area AA02 of the display area, the width of the gate line portion 21 at this position is set to 22.7 micrometers.

[0125] At the position of the second gap projection 215 between the second overlapping projection 212 and the third overlapping projection 213, which does not overlap with the orthographic projection of the pixel electrode 33 on the substrate, the width of the gate line portion 21 at this position can be designed differently. For example, the width of the gate line portion 21 at the position located in the edge area AA01 of the display area is set to 8.2 microns. Fig.13 As shown, at the same first overlapping projection 211 position of the gate line portion 21 located in the central area AA02 of the display area, the width of the gate line portion 21 at this position is set to 11.2 micrometers.

[0126] Based on the above-mentioned embodiments of the present invention, differentiated gate line widths can be set at one or more of the first overlapping projection 211, the second overlapping projection 212, the first gap projection 214 or the second gap projection 215. That is to say, the gate line width of the embodiment of the present invention is not set at the position of the third overlapping projection 213 to protect the design requirements of the gate line portion 21 and the first driving electrode 34 or the second driving electrode 35 at this position to ensure circuit performance.

[0127] The design of the above-mentioned embodiment of the present invention can effectively improve the overall uniformity of the pixel charging rate of the array substrate, thereby improving the display performance of the array substrate.

[0128] Furthermore, in both bright and dark backlight states, the presence or absence of light has the same effect on the active layer conductor characteristics of the Dual Gate product, causing a delay effect in the voltage connected to each metal trace, resulting in light and dark stripes on the display product, known as waterfall, which also affects the display effect. In addition, because the signal lines in the display product affect each other due to capacitive coupling, signal transmission abnormalities are caused, and there is a risk of V-Crosstalk (crosstalk) defects.

[0129] Therefore, in an optional embodiment, if Fig.14 and Fig.15 As shown, the distance between the boundary of the pixel electrode 33 on the substrate parallel to the second direction and the boundary of the ground line 40 on the substrate parallel to the second direction is a first distance d3, and the distance between the boundary of the pixel electrode 33 on the substrate parallel to the second direction and the boundary of the data line 10 on the substrate parallel to the second direction is a second distance d4, and the first distance d3 is smaller than the second distance d4.

[0130] In the embodiment of the present invention, the first distance d3 between the pixel electrode 33 and the ground line 40 and the second distance d4 between the pixel electrode 33 and the data line 10 are designed to be different, and the first distance d3 is smaller than the second distance d4, thereby improving the problems of Waterfall and V-Crosstalk.

[0131] In a specific example, the first distance d3 is 3.5 microns, and the second distance d4 is 6 microns. Compared with the design scheme in the related art in which the first distance d3 and the second distance d4 are the same, both being 5 microns, the first distance d3 is reduced, reducing the routing area to improve the influence of light, thereby improving the poor Waterfall. The second distance d4 is increased, thereby reducing the pixel capacitance between the data line 10 on the left and right sides of the pixel electrode 33 and the pixel electrode 33, thereby improving the poor V-Crosstalk.

[0132] In an optional embodiment, if Fig.16 As shown, the array substrate further includes:

[0133] A data driving module 50, configured to output a data signal;

[0134] A plurality of binding parts 51 arranged in sequence in a first direction in the fan-out region, the binding parts 51 comprising a plurality of metal connecting wires 60, one end of each of the metal connecting wires 60 being connected to the output end of the data driving module 50, and the other end being connected to the data line 10 of the display area AA;

[0135] The first connection line width of the metal connection line 60 corresponding to the data line 10 in the display area edge region AA01 is greater than the second connection line width of the metal connection line 60 corresponding to the data line 10 in the display area center region AA02.

[0136] The embodiment of the present invention designs the width of the metal connecting line 60 obtained at different positions so that in the direction from the edge area AA01 of the display area to the center area AA02 of the display area, the first connecting line width of the metal connecting line 60 is greater than the second connecting line width, that is, the width in the edge area is large and the width in the center area is small. In a specific example, the first connecting line width is 8.9 microns and the second connecting line width is 6.9 microns. This setting can effectively reduce the impedance difference between the data lines 10 on both sides and the middle data line 10 in the entire display area AA, thereby improving display uniformity.

[0137] In an optional embodiment, in the first direction, the number of metal connection lines 60 corresponding to the data lines 10 in the edge area AA01 of the display area is 1 / 4 to 1 / 2 of the total number of metal connection lines 60 in the binding part 51 located at the edge. Exemplarily, the binding part 50 located at the edge includes 960 metal connection lines 60. Under this structure, the number of metal connection lines 60 designed for width is 240 to 480, for example, preferably 1 / 3, that is, 320.

[0138] That is to say, based on the fact that the width of the gate line portion 21 in the aforementioned embodiment of the present invention is also designed, the number of metal connecting lines 60 is set to be consistent with the number of the gate line portions 21 with designed width, further ensuring the uniformity of the overall in-plane charging rate of the display area AA.

[0139] Based on the array substrate of the aforementioned embodiment, an embodiment of the present invention provides a method for manufacturing the array substrate of the aforementioned embodiment, the method comprising:

[0140] A plurality of data lines 10 arranged in an array along a first direction are formed on the substrate at positions corresponding to the display area AA, and each data line 10 extends along a second direction intersecting the first direction;

[0141] A plurality of gate lines 20 arranged along the second direction and insulated from the data line 10 are formed on the substrate at positions corresponding to the display area AA, each gate line 20 extends along the first direction, gate line portions 21 of the same gate line 20 located in different pixel areas have the same pattern shape of the orthographic projection on the substrate of the array substrate, the length of the gate line 20 in the second direction is the gate line width, and at positions of the gate line portions 21 in different pixel areas corresponding to the same pattern shape, the first gate line width d1 of the gate line portion 21 located in the edge area AA01 of the display area is smaller than the second gate line width d2 of the gate line portion 21 located in the central area AA02 of the display area;

[0142] A pixel group 30 is formed in a pixel area defined by the intersection of two adjacent data lines 10 and two adjacent gate lines 20 .

[0143] The manufacturing method of the present invention does not add complicated process flow. The array substrate formed by the manufacturing method of the embodiment of the present invention forms different gate line widths corresponding to different pixel areas, so that the gate line width of the gate line portion 21 in the edge area AA01 of the display area is smaller than the gate line width in the central area AA02 of the display area. Through this setting, the impedance difference between the edge area AA01 of the display area and the central area AA02 of the display area can be improved, the delay effect can be reduced, and the uniformity of the charging rate in the surface of the display product can be improved.

[0144] Another embodiment of the present invention provides a display device, characterized in that the display device includes the array substrate of the first embodiment of the present invention. The display device can be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc., which is not limited in this embodiment.

[0145] In the description of the present invention, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0146] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not limitations on the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the embodiments here. All obvious changes or modifications derived from the technical solution of the present invention are still within the protection scope of the present invention.

Claims

1. An array substrate, characterized in that: The array substrate comprises: A plurality of data lines arranged in sequence along a first direction in the display area, each data line extending along a second direction intersecting the first direction; a plurality of gate lines arranged in sequence along the second direction in the display area, each gate line extending along the first direction, and the gate lines being insulated from the data lines; and A pixel group is located in a pixel area defined by the intersection of two adjacent data lines and two adjacent gate lines; in, Each of the gate lines includes a plurality of gate line portions located in different pixel regions. The length of the gate line in the second direction is the gate line width, At positions where the gate line portions of different pixel regions have the same vertical distance from the corresponding data lines on the same side, the first gate line width of the gate line portion located in the edge area of ​​the display area is smaller than the second gate line width of the gate line portion located in the center area of ​​the display area.

2. The array substrate according to claim 1, characterized in that: Each of the pixel groups includes a first pixel and a second pixel arranged along the first direction, and each pixel corresponds to a pixel electrode. Two pixel groups adjacent to each other in the first direction share the same data line as a boundary of the pixel area, and two pixel electrodes of the first pixel and the second pixel are driven by the same data line; Two gate lines are arranged between two adjacent pixel groups in the second direction, and a first pixel and a second pixel in the same pixel group are respectively driven by the two gate lines defining the pixel area.

3. The array substrate according to claim 2, characterized in that: The first pixel and the second pixel in the same pixel group have different colors. In two adjacent pixel groups in the first direction, the color of the first pixel in one pixel group is different from the color of the first pixel in the other pixel group, and the color of the second pixel in one pixel group is different from the color of the second pixel in the other pixel group.

4. The array substrate according to claim 3, characterized in that: The array substrate further includes: a first driving electrode electrically connected to each pixel electrode, a second driving electrode corresponding to the first driving electrode, the second driving electrode being connected to the data line; and A plurality of grounding lines are sequentially arranged along the first direction, each grounding line is located between a first pixel and a second pixel of the same pixel group, and is extended along the second direction.

5. The array substrate according to claim 4, characterized in that: The orthographic projection of the gate line portion on the substrate includes: A first overlapping projection overlapping with an orthographic projection of the data line on the substrate; a second overlapping projection overlapping with the orthographic projection of the ground line on the substrate; a third overlapping projection overlapping with the orthographic projection of the first driving electrode or the second driving electrode on the substrate; a first gap projection located between the first overlapping projection and the second overlapping projection and not overlapping with the orthographic projection of the pixel electrode on the substrate; and a second gap projection located between the second overlapping projection and the third overlapping projection and not overlapping with the orthographic projection of the pixel electrode on the substrate; The width difference between the first gate line width and the second gate line width is set at one or more of the first overlapping projection, the second overlapping projection, the first gap projection or the second gap projection.

6. The array substrate according to any one of claims 1 to 5, characterized in that: The edge area of ​​the display area includes multiple gate line parts of the same gate line, and in the direction from the edge area of ​​the display area to the central area of ​​the display area, the first gate line width of the multiple gate line parts of the same gate line at the same position gradually increases.

7. The array substrate according to claim 6, characterized in that: The width difference between the second gate line width and the first gate line width is 1.5 to 3 micrometers.

8. The array substrate according to claim 6, characterized in that: The minimum value of the first gate line width is greater than or equal to 7 micrometers.

9. The array substrate according to claim 6, characterized in that: The distance between the boundary of the orthographic projection of the pixel electrode on the substrate parallel to the second direction and the boundary of the orthographic projection of the ground line on the substrate parallel to the second direction is a first distance, The distance between the boundary of the orthographic projection of the pixel electrode on the substrate parallel to the second direction and the boundary of the orthographic projection of the data line on the substrate parallel to the second direction is the second distance, The first distance is smaller than the second distance.

10. The array substrate according to claim 1, characterized in that: The array substrate further includes: A data driving module, used for outputting data signals; A plurality of binding parts arranged sequentially in a first direction in the fan-out region, the binding parts comprising a plurality of metal connecting lines, one end of each of the metal connecting lines being connected to an output end of the data driving module and the other end being connected to a data line of the display region; The first connection line width of the metal connection line connected to the data line located in the edge area of ​​the display area is greater than the second connection line width of the metal connection line connected to the data line located in the center area of ​​the display area.

11. The array substrate according to claim 10, characterized in that: In the first direction, the number of metal connection lines connected to the data lines located in the edge area of ​​the display area is 1 / 4 to 1 / 2 of the total number of metal connection lines in the binding portion located at the edge.

12. The array substrate according to claim 10, characterized in that: In the first direction, In the same gate line, the number of the gate line parts located in the edge area of ​​the display area is 1 / 4 to 1 / 2 of the total number of data lines connected to the metal connecting lines of the binding parts located at the edge.

13. A method for manufacturing the array substrate according to any one of claims 1 to 12, characterized in that: The method comprises: A plurality of data lines arranged in an array along a first direction are formed on the substrate at positions corresponding to the display area, and each data line extends along a second direction intersecting the first direction; A plurality of gate lines arranged along the second direction and insulated from the data lines are formed on the substrate at positions corresponding to the display area, each gate line extends along the first direction, gate line portions of the same gate line located in different pixel areas have the same pattern shape of the orthographic projection on the substrate of the array substrate, the length of the gate line in the second direction is the gate line width, and at a position having the same vertical distance as the data line on the same side, a first gate line width of the gate line portion located in the edge area of ​​the display area is smaller than a second gate line width of the gate line portion located in the center area of ​​the display area; A pixel group is formed in a pixel area defined by the intersection of two adjacent data lines and two adjacent gate lines.

14. A display device, characterized in that: The display device comprises the array substrate according to any one of claims 1 to 12.

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