A pixel driving circuit and a writing method for field sequential display

Abstract

The application discloses a pixel driving circuit and a writing method for field sequential display, comprising pixel units arranged in multiple rows and multiple columns, the pixel units comprising a driving module and a reset module, the reset module comprising a third transistor and a first reference signal line; the connection mode of the third transistor is configured such that the gate of the third transistor is coupled with the second source / drain electrode or the gate of the third transistor is coupled with the first source / drain electrode; the first source / drain electrode of the third transistor is coupled to the driving module, and the second source / drain electrode of the third transistor is coupled to the first reference signal line; the third transistor; the third transistor; the third transistor; the third transistor; the third transistor; and the third transistor. The application has the beneficial effects that: the gate and the source / drain electrode of the third transistor are connected to save the reset signal line, reduce the number of signal lines used, and reduce the number of metal layers in the layout preparation, thereby reducing the difficulty of layout preparation.

Description

Technical Field

[0001] This invention relates to the field of pixel display technology, and in particular to a pixel driving circuit and writing method for field sequence display. Background Technology

[0002] Field sequential or color sequential display driving technology leverages the persistence of vision to directly mix RGB three-color light sources, achieving full-color display effects. It eliminates the need for color filters, improving light source utilization and reducing power consumption. The backlight can only be turned on after all image data has been written and the liquid crystal has reached a stable state; otherwise, image distortion will occur. Therefore, a significant time must be allowed for the liquid crystal to deflect before the backlight is activated. This makes it difficult to achieve high brightness and high frequency display over an average time, while also increasing the requirements for backlight brightness specifications and lifespan, thus raising costs.

[0003] To achieve stable high refresh rate and high brightness, this invention proposes a pixel driving circuit and writing method for field sequence display. Summary of the Invention

[0004] The purpose of this invention is to provide a pixel driving circuit and writing method for field sequence display, thereby reducing the voltage variation range of the data signal line.

[0005] The present invention aims to achieve a pixel driving circuit and writing method for field sequence display through the following technical solution, including pixel units arranged in multiple rows and columns, wherein the pixel unit includes a driving module and a reset module, and the reset module includes a third transistor and a first reference signal line;

[0006] The connection method of the third transistor is configured such that the gate of the third transistor is coupled to the second source and drain, or the gate of the third transistor is coupled to the first source and drain.

[0007] The first source-drain of the third transistor is coupled to the driving module, and the second source-drain of the third transistor is coupled to the first reference signal line.

[0008] Furthermore, the driving module includes a second transistor and a pixel electrode. The gate of the second transistor is coupled to a transfer signal line. The first source and drain of the second transistor are coupled to the second source and drain of the first transistor. The second source and drain of the second transistor are coupled to one end of the pixel electrode. The second source and drain of the second transistor are also coupled to the first source and drain of the third transistor.

[0009] Furthermore, the pixel unit also includes a pre-storage module; the pre-storage module includes a first transistor and a pre-storage capacitor, the first source and drain of the first transistor are coupled to a data signal line, the gate of the first transistor is coupled to a row gate signal line, and the second source and drain of the first transistor are coupled to one end of the pre-storage capacitor.

[0010] Furthermore, the other end of the pre-storage capacitor of the pixel unit located in the odd-numbered column and the other end of the pixel electrode are both coupled to the second common signal line;

[0011] The other end of the pre-storage capacitor of the pixel unit located in the even-numbered column and the other end of the pixel electrode are both coupled to the first common signal line;

[0012] A first AC drive signal is input to the pixel units located in even-numbered columns through the first common signal line, and a second AC drive signal is input to the pixel units located in odd-numbered columns through the second common signal line, wherein the first AC drive signal and the second AC drive signal have the same frequency and opposite polarity.

[0013] Furthermore, the driving module also includes a holding capacitor coupled to the second source and drain of the second transistor; the other end of the holding capacitor is coupled to the second reference signal line.

[0014] Furthermore, when preparing the layout of the pixel unit, the layout includes a light-shielding layer, an active layer, a source / drain layer, an intermediate metal layer, a transparent conductive layer, and a color conductive layer;

[0015] The light-shielding layer is disposed on the glass substrate, a first insulating layer is disposed on the light-shielding layer, and an active layer is disposed on the first insulating layer. The active layer constitutes the gate of the first transistor and the gate of the second transistor. Row gate signal lines and transfer signal lines are also formed on the light-shielding layer.

[0016] A second insulating layer is disposed on the active layer, and a source / drain layer is disposed on the second insulating layer. The source / drain layer is connected to the active layer through a via. The source / drain layer and the active layer constitute the channel region, the first terminal, and the second terminal of the first transistor. At the same time, the source / drain layer and the active layer also constitute the channel region, the first terminal, and the second terminal of the second transistor. Furthermore, the source / drain layer and the active layer constitute the channel region, the first terminal, and the second terminal of the third transistor. The channel region of the third transistor is connected to the first terminal.

[0017] A third insulating layer is disposed on the source / drain layer, and an intermediate metal layer is disposed on the third insulating layer. The intermediate metal layer constitutes a first reference signal line and a data signal line. The overlapping portion of the intermediate metal layer and the source / drain layer forms a pre-storage capacitor.

[0018] A fourth insulating layer is disposed on the intermediate metal layer, and a transparent conductive layer is disposed on the fourth insulating layer. The transparent conductive layer constitutes a pixel electrode. The intermediate metal layer is connected to the color conductive layer through a conductive material, and the color conductive layer forms a common signal line.

[0019] Furthermore, the color conductive layer of the pixel units located in the odd-numbered columns forms a second common signal line; the color conductive layer of the pixel units located in the even-numbered columns forms a first common signal line.

[0020] The present invention also provides a method for writing pixel driving circuits for field-sequence display, comprising:

[0021] First programming stage:

[0022] By controlling the potential changes of the data signal line and the row gate signal line, the data signal line writes the data signal voltage to the pre-storage capacitor through the first transistor.

[0023] Second programming stage:

[0024] The potential change of the first reference signal line enables the first reference signal line to complete the reset of the pixel electrode and the holding capacitor through the third transistor;

[0025] Transfer phase:

[0026] By controlling the level changes of the transfer signal line, the first common signal line, and the second common signal line, the amount of charge transferred from the pre-storage capacitor to the pixel electrode is adjusted, thereby completing the writing of the preset data signal voltage to the pixel electrode.

[0027] The first common signal line outputs a first AC drive signal, and the second common signal line outputs a second AC drive signal, wherein the first AC drive signal and the second AC drive signal have the same frequency but opposite polarities.

[0028] The present invention has the following advantages:

[0029] This invention connects the gate of the third transistor to the first or second source-drain terminal, thereby forming a diode structure. This reduces the use of a reset signal line, and the first reference signal line connected to the second source-drain terminal now exhibits the same changing state in each cycle. Thus, the improvement in the third transistor structure can reduce the use of signal lines, increase the aperture ratio, and reduce the control difficulty of the first reference signal line.

[0030] This invention connects the gate of a third transistor to either the first or second source / drain. In conventional layout fabrication, a gate metal layer is first used to fabricate the gate of the third transistor, then an insulating layer is covered on this metal layer, and finally, the first and second source / drains of the third transistor are fabricated through another metal layer. Now, by directly connecting the channel region to the first or second end, it is equivalent to directly connecting the gate of the transistor to the first or second end through the channel region. This reduces the use of one gate metal layer and one insulating layer, thereby saving on the number of layers and processes required for layout fabrication.

[0031] This invention further replaces the DC-driven common signal line in the prior art with two AC signal lines connected to the odd and even columns respectively. The AC drive signal of the first common signal line has the same frequency but opposite polarity to the AC drive signal of the second common signal line. During the reset phase, the first reference signal line resets the pixel electrodes of both the odd and even columns to 0 or Vop_max. This allows the voltage difference across the pixel electrode to reach (-Vop_max, +Vop_max), thereby achieving the pixel voltage required by the pixel electrode when it is working in that frame. As a result, the voltage pre-written into the pre-storage capacitor of the data signal line can be reduced, thus reducing the range of data voltage variation of the data signal line. Attached Figure Description

[0032] Figure 1 This is a circuit diagram of Embodiment 1 of the present invention;

[0033] Figure 2 This is a schematic diagram of the layout of Embodiment 1 of the present invention;

[0034] Figure 3 This is a timing diagram of Embodiment 1 of the present invention;

[0035] Figure 4 This is a circuit diagram of Embodiment 2 of the present invention;

[0036] Figure 5 This is a schematic diagram of the layout of Embodiment 2 of the present invention;

[0037] Figure 6 This is a timing diagram of Embodiment 2 of the present invention;

[0038] In the picture:

[0039] 1-Light-shielding layer, 2-Active layer, 3-Source / drain layer, 4-Intermediate metal layer, 5-Transparent conductive layer, 6-Colored conductive layer. Detailed Implementation

[0040] The present invention will be further described below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the following description.

[0041] It should be noted that the orientation or positional relationship indicated by terms such as "left" and "right" is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use, or the orientation or positional relationship in which those skilled in the art would conventionally understand it. Such terms are only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0042] It should be noted that, unless otherwise specified, the embodiments and features and technical solutions in the present invention can be combined with each other. Example

[0043] In Embodiment 1, a pixel driving circuit for field sequence display is provided, including pixel units arranged in multiple rows and columns. The pixel unit includes a pre-storage module, a driving module, and a reset module. The reset module includes a third transistor T3 and a first reference signal line Vref1. The gate and the second source and drain of the third transistor T3 are both coupled to the first reference signal line Vref1.

[0044] The pre-storage module includes a first transistor T1 and a pre-storage capacitor Cs1. The first source and drain of the first transistor T1 are coupled to the data signal line Data, the gate of the first transistor T1 is coupled to the row gate signal line Scan, and the second source and drain of the first transistor T1 are coupled to one end of the pre-storage capacitor Cs1.

[0045] The driving module includes a second transistor T2, a holding capacitor Cs2, and a pixel electrode Clc. The gate of the second transistor T2 is coupled to the transfer signal line Tran. The first source and drain of the second transistor T2 are coupled to the second source and drain of the first transistor T1. The second source and drain of the second transistor T2 are coupled to the pixel electrode Clc and one end of the holding capacitor Cs2. The other end of the holding capacitor Cs2 is coupled to the second reference signal line Vref2.

[0046] The other end of the pre-storage capacitor Cs1 and the other end of the pixel electrode Clc of the pixel units located in the odd-numbered columns are both coupled to the second common signal line Vcom_even; the other end of the pre-storage capacitor Cs1 and the other end of the pixel electrode Clc of the pixel units located in the even-numbered columns are both coupled to the first common signal line Vcom_odd. A first AC drive signal is input to the pixel units located in the even-numbered columns through the first common signal line Vcom_odd, and a second AC drive signal is input to the pixel units located in the odd-numbered columns through the second common signal line Vcom_even. The first AC drive signal and the second AC drive signal have the same frequency and opposite polarities.

[0047] When preparing the layout of pixel units, such as Figure 2As shown, the layout includes a light-shielding layer 1, an active layer 2, a source / drain layer 3, an intermediate metal layer 4, a transparent conductive layer 5, and a colored conductive layer 6.

[0048] A light-shielding layer 1 is disposed on a glass substrate. A first insulating layer is disposed on the light-shielding layer 1. An active layer 2 is disposed on the first insulating layer. The active layer 2 constitutes the gate of the first transistor T1 and the gate of the second transistor T2. Row gate signal line Scan and transfer signal line Tran are also formed on the light-shielding layer 1.

[0049] A second insulating layer is disposed on the active layer 2, and a source / drain layer 3 is disposed on the second insulating layer. The source / drain layer 3 is connected to the active layer 2 through a via. The source / drain layer 3 and the active layer 2 constitute the channel region, the first end and the second end of the first transistor T1. At the same time, the source / drain layer 3 and the active layer 2 also constitute the channel region, the first end and the second end of the second transistor T2. Furthermore, the source / drain layer 3 and the active layer 2 constitute the channel region, the first end and the second end of the third transistor T3. The channel region of the third transistor T3 is connected to the first end.

[0050] A third insulating layer is disposed on the source / drain layer 3, and an intermediate metal layer 4 is disposed on the third insulating layer. The intermediate metal layer 4 constitutes the first reference signal line Vref1 and the data signal line Data. The overlapping portion of the intermediate metal layer 4 and the source / drain layer 3 forms a pre-storage capacitor Cs1. A fourth insulating layer is disposed on the intermediate metal layer 4, and a transparent conductive layer 5 is disposed on the fourth insulating layer. The transparent conductive layer 5 constitutes a pixel electrode Clc. The intermediate metal layer 4 is connected to the color conductive layer 6 through a conductive material, and the color conductive layer 6 forms a common signal line.

[0051] In some specific embodiments, the color conductive layer 6 of the pixel units located in odd-numbered columns forms a second common signal line Vcom_even; the color conductive layer 6 of the pixel units located in even-numbered columns forms a first common signal line Vcom_odd.

[0052] The present invention connects the gate of the third transistor T3 to the first source-drain or the second source-drain, so that the third transistor T3 forms a diode structure, thereby reducing the use of a reset signal line. Thus, the improvement of the third transistor T3 can reduce the use of signal lines and increase the aperture ratio.

[0053] Simultaneously, the gate of the third transistor T3 is connected to the second source and drain. During layout preparation, the channel region of the third transistor T3 is directly connected to the first or second end, which is equivalent to directly connecting the gate of the transistor to the first or second end through the channel region. This reduces the use of the gate metal layer for forming the third transistor T3, thereby saving on layout preparation processes.

[0054] During operation, the timing map is configured as follows for pixel units located in odd-numbered columns: Figure 3 As shown,

[0055] First programming stage:

[0056] By controlling the potential changes of the data signal line Data and the row gate signal line Scan, the data signal line Data writes the data signal voltage to the pre-storage capacitor Cs1 through the first transistor T1.

[0057] When the row gate signal line Scan jumps to a high level, the first transistor T1 turns on, causing the data signal line Data to write the data signal voltage of the (n+1)th frame into the pre-storage capacitor Cs1.

[0058] After the write operation is complete, the row gate signal line Scan switches to a low level, and the first transistor T1 is turned off.

[0059] Second programming stage:

[0060] Through the potential change of the first reference signal line Vref1, the level of the first reference signal line Vref1 jumps from 0 level to Vop_max level, the third transistor T3 is turned on, so that the first reference signal line Vref1 completes the reset of the pixel electrode Clc and the holding capacitor Cs2 through the third transistor T3. At this time, the potential of the pixel electrode Clc is reset to Vop_max, and Vop_max is the voltage corresponding to the maximum gray level.

[0061] Furthermore, the first reference signal line Vref1 has the same level change in the nth frame or the (n+1)th frame, which reduces the difficulty for the driver chip to control the first reference signal line Vref1.

[0062] Transfer phase:

[0063] By controlling the level changes of the transfer signal line Tran and the second common signal line Vcom_even, the amount of charge transferred from the pre-storage capacitor Cs1 to the pixel electrode Clc is increased, thus completing the writing of the preset data signal voltage to the pixel electrode Clc.

[0064] When the transfer signal line Tran jumps to a high level, the second transistor T2 turns on, causing the pre-storage capacitor Cs1 to transfer charge to the pixel electrode Clc through the second transistor T1.

[0065] When the transfer signal line Tran jumps to a low level, the second transistor T2 is turned off, and at the same time, the level of the second common signal line Vcom_even jumps to a low level. At this time, the potential of the lower stage board of the pixel electrode Clc is the same as that of the second common signal line Vcom_even. The pixel electrode Clc releases excess charge through the second common signal line Vcom_even until the voltage of the pixel electrode Clc reaches the preset data signal voltage.

[0066] In this embodiment, the voltage range required for the data signal line Data is calculated based on the principle of charge conservation. Taking an odd-numbered pixel unit as an example, the display time of the nth frame corresponds to writing the data signal voltage of the (n+1)th frame to the pre-storage capacitor Cs1, which requires writing a positive voltage. During the transfer stage, if the pixel voltage Vpixel of the pixel electrode Clc equals Vop_max, the pixel voltage Clc has been reset to Vop_max in the second programming stage. Therefore, based on the principle of charge conservation, the following formula can be obtained:

[0067] (Vcs1-(Vop_max))*Cs1=((Vop_max)- (Vop_max)) *(Cs2+Clc);

[0068] That is, Vcs1-Vop_max = 0, so Vcs1 = Vop_max;

[0069] In the formula:

[0070] Vcs1: The data signal voltage pre-written into the pre-stored capacitor Cs1;

[0071] Vop_max: Vpixel / Reset voltage;

[0072] Cs1: The capacitance value of the pre-stored capacitor Cs1;

[0073] Cs2: The capacitance value of the holding capacitor Cs2;

[0074] Clc: The capacitance value of the pixel electrode Clc.

[0075] During the transfer phase, if the pixel voltage Vpixel of the pixel electrode Clc is 0, the pixel voltage Clc has been reset to Vop_max in the second programming phase. Therefore, according to the principle of charge conservation, the following formula can be obtained:

[0076] (Vcs1-0)*Cs1=(0- (Vop_max))*(Cs2+Clc), Vcs1-0=0- (Vop_max), Vcs1=-Vop_max;

[0077] Therefore, in a positive polarity frame, the required voltage range for the data signal line Data is (-Vop_max, +Vop_max).

[0078] Similarly, in a negative polarity frame, the pixel voltage Vpixel of the pixel electrode Clc varies within the range of (-Vop_max, 0). Likewise, the pixel electrode Clc is reset to Vop_max during the reset phase. Based on the above steps, the voltage variation range of the data signal line Data can be calculated as (-Vop_max, +Vop_max).

[0079] Therefore, the voltage variation range of the data signal line Data during the entire operation is (-Vop_max, +Vop_max). In the prior art, the voltage variation range of the data signal line Data needs to be 4*Vop_max. This embodiment can reduce the voltage variation range by half. The reduction in the voltage range of the data signal line Data can further reduce the power consumption of the driver chip and the control row gate signal line output unit. Example

[0080] like Figure 4 and Figure 5 As shown, the present invention also provides a second embodiment, in which the gate of the third transistor T3 of the pixel unit is coupled to the first source and drain of the third transistor T3. At this time, during the layout preparation, the channel region of the third transistor T3 is connected to the first end.

[0081] During operation, the timing map is configured as follows for pixel units located in odd-numbered columns: Figure 6 As shown, the second programming stage:

[0082] The level of the first reference signal line Vref1 jumps from the Vopmanx level to 0 level. At this time, the first source-drain terminal of the third transistor T3 is at a high level, and the second source-drain terminal of the third transistor T3 is at a 0 level, thus forming a voltage difference across the two ends. The third transistor T3 is turned on, so that the first reference signal line Vref1 completes the reset of the pixel electrode Clc and the holding capacitor Cs2 through the third transistor T3. At this time, the potential of the pixel electrode Clc is reset to 0 level.

[0083] In this embodiment, the voltage range that the data signal line Data needs to output is calculated according to the principle of charge conservation. Taking the odd-numbered column of pixel units as an example, the display time of the nth frame corresponds to the writing of the data signal voltage of the (n+1)th frame to the pre-storage capacitor Cs1, that is, the writing of the positive polarity voltage.

[0084] During the transfer phase, when the pixel voltage Vpixel of the pixel electrode Clc equals Vop_max, the pixel voltage Clc has been reset to 0 level in the second programming phase. Therefore, based on the principle of charge conservation, the following formula can be derived:

[0085] (Vcs1-(Vop_max))*Cs1=((Vop_max)- (0)) *(Cs2+Clc);

[0086] That is, Vcs1-Vop_max-Vop_max =0, so Vcs1 = 2*Vop_max;

[0087] In the formula:

[0088] Vcs1: The data signal voltage pre-written into the pre-stored capacitor Cs1;

[0089] Vop_max: Vpixel;

[0090] Cs1: The capacitance value of the pre-stored capacitor Cs1;

[0091] Cs2: The capacitance value of the holding capacitor Cs2;

[0092] Clc: The capacitance value of the pixel electrode Clc.

[0093] When the pixel voltage Vpixel of the pixel electrode Clc is 0, the pixel voltage Clc has been reset to 0 in the second programming stage. Therefore, according to the principle of charge conservation, the following formula can be obtained:

[0094] (Vcs1-0)*Cs1=(0- (0))*(Cs2+Clc), Vcs1-0=0- (0), Vcs1=2*Vop_max;

[0095] Therefore, in a positive polarity frame, the required voltage range for the data signal line Data is (0, 2*Vop_max).

[0096] Similarly, in a negative polarity frame, the pixel voltage Vpixel of the pixel electrode Clc varies within the range of (0, 2*Vop_max). Likewise, the pixel electrode Clc is reset to 0 level during the reset phase. Based on the above steps, the voltage variation range of the data signal line Data can be calculated to be (0, 2*Vop_max), and the voltage variation range of the data signal line Data is 2*Vop_max. Example

[0097] The present invention also provides a third embodiment, which is a pixel driving circuit writing method for field sequence display, applied to the first and second embodiments, including the circuit obtained by modification of the first and second embodiments;

[0098] First programming stage:

[0099] By controlling the potential changes of the data signal line Data and the row gate signal line Scan, the data signal line Data writes the data signal voltage to the pre-storage capacitor Cs1 through the first transistor T1.

[0100] Second programming stage:

[0101] The potential change of the first reference signal line Vref1 enables the first reference signal line Vref1 to complete the reset of the pixel electrode Clc and the holding capacitor Cs2 through the third transistor T3.

[0102] Transfer phase:

[0103] By controlling the level changes of the transfer signal line Tran, the first common signal line Vcom_odd, and the second common signal line Vcom_even, the amount of charge transferred from the pre-storage capacitor Cs1 to the pixel electrode Clc is made so as to complete the writing of the preset data signal voltage to the pixel electrode Clc.

[0104] The first common signal line Vcom_odd outputs the first AC drive signal, and the second common signal line Vcom_even outputs the second AC drive signal, wherein the first AC drive signal and the second AC drive signal have the same frequency and opposite polarities.

[0105] By replacing the DC-driven common signal line in the existing technology with two AC signal lines connected to the odd and even columns respectively, and with the AC drive signal of the first common signal line Vcom_odd having the same frequency but opposite polarity to the AC drive signal of the second common signal line Vcom_even; in conjunction with the first reference signal line Vref1 resetting the pixel electrodes Clc of both the odd and even columns to 0 or Vop_max during the reset phase; this allows the voltage difference across the pixel electrode Clc to be between (-Vop_max, +Vop_max), thereby achieving the pixel voltage Vpixel required by the pixel electrode Clc when it is working in that frame; thus, the voltage pre-written into the pre-storage capacitor Cs1 of the data signal line Data can be reduced, reducing the range of data voltage variation of the data signal line Data.

[0106] The above embodiments only illustrate preferred implementation methods, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from this invention, and these all fall within the protection scope of this invention.

Claims

1. A pixel driving circuit for field-sequence display, characterized in that: It includes pixel units arranged in multiple rows and columns, each pixel unit including a driving module and a reset module, the reset module including a third transistor T3 and a first reference signal line Vref1; The connection method of the third transistor T3 is configured such that the gate of the third transistor T3 is coupled to the second source and drain, or the gate of the third transistor T3 is coupled to the first source and drain. The first source and drain of the third transistor T3 are coupled to the driving module, and the second source and drain of the third transistor T3 are coupled to the first reference signal line Vref1; When preparing the layout of the pixel unit, the layout includes a light-shielding layer (1), an active layer (2), a source / drain layer (3), an intermediate metal layer (4), a transparent conductive layer (5), and a color conductive layer (6). The light-shielding layer (1) is disposed on the glass substrate, a first insulating layer is disposed on the light-shielding layer (1), and an active layer (2) is disposed on the first insulating layer. The active layer (2) constitutes the gate of the first transistor T1 and the gate of the second transistor T2. Row gate signal line Scan and transfer signal line Tran are also formed on the light-shielding layer (1). A second insulating layer is provided on the active layer (2), and a source / drain layer (3) is provided on the second insulating layer. The source / drain layer (3) is connected to the active layer (2) through a via. The source / drain layer (3) and the active layer (2) constitute the channel region, first end and second end of the first transistor T1. At the same time, the source / drain layer (3) and the active layer (2) also constitute the channel region, first end and second end of the second transistor T2. Furthermore, the source / drain layer (3) and the active layer (2) constitute the channel region, first end and second end of the third transistor T3. The channel region of the third transistor (T3) is connected to the first end. A third insulating layer is provided on the source / drain layer (3), and an intermediate metal layer (4) is provided on the third insulating layer. The intermediate metal layer (4) constitutes the first reference signal line Vref1 and the data signal line Data. The overlapping portion of the intermediate metal layer (4) and the source / drain layer (3) forms a pre-storage capacitor Cs1. A fourth insulating layer is provided on the intermediate metal layer (4), and a transparent conductive layer (5) is provided on the fourth insulating layer. The transparent conductive layer (5) constitutes a pixel electrode (Clc). The intermediate metal layer (4) is connected to the color conductive layer (6) through a conductive material, and the color conductive layer (6) forms a common signal line.

2. The pixel driving circuit for field-sequence display according to claim 1, characterized in that, The driving module includes a second transistor T2 and a pixel electrode Clc. The gate of the second transistor T2 is coupled to the transfer signal line Tran. The second source and drain of the second transistor T2 are coupled to one end of the pixel electrode Clc. The second source and drain of the second transistor T2 are also coupled to the first source and drain of the third transistor T3.

3. A pixel driving circuit for field-sequence display according to claim 2, characterized in that, The pixel unit also includes a pre-storage module; The pre-storage module includes a first transistor T1 and a pre-storage capacitor Cs1. The first source and drain of the first transistor T1 are coupled to the data signal line Data. The gate of the first transistor T1 is coupled to the row gate signal line Scan. The second source and drain of the first transistor T1 are coupled to one end of the pre-storage capacitor Cs1. The second source and drain of the first transistor T1 are also coupled to the first source and drain of the second transistor T2.

4. A pixel driving circuit for field-sequence display according to claim 3, characterized in that, The other end of the pre-storage capacitor Cs1 of the pixel unit located in the odd column and the other end of the pixel electrode Clc are both coupled to the second common signal line Vcom_even; The other end of the pre-storage capacitor Cs1 of the pixel unit located in the even column and the other end of the pixel electrode Clc are both coupled to the first common signal line Vcom_odd; A first AC drive signal is input to the even-numbered pixel units via the first common signal line Vcom_odd, and a second AC drive signal is input to the odd-numbered pixel units via the second common signal line Vcom_even. The first AC drive signal and the second AC drive signal have the same frequency but opposite polarities.

5. A pixel driving circuit for field-sequence display according to claim 2, characterized in that, The driving module also includes a holding capacitor Cs2, which is coupled to the second source and drain of the second transistor T2; the other end of the holding capacitor Cs2 is coupled to the second reference signal line Vref2.

6. A pixel driving circuit for field-sequence display according to claim 5, characterized in that, The color conductive layer (6) of the pixel units located in odd-numbered columns forms a second common signal line Vcom_even; the color conductive layer (6) of the pixel units located in even-numbered columns forms a first common signal line Vcom_odd.

7. A pixel driving circuit writing method for field-sequence display, applied in any of the pixel driving circuits described in claims 1 to 6, characterized in that, include: First programming stage: By controlling the potential changes of the data signal line Data and the row gate signal line Scan, the data signal line Data writes the data signal voltage to the pre-storage capacitor Cs1 through the first transistor T1. Second programming stage: The potential change of the first reference signal line Vref1 enables the first reference signal line Vref1 to complete the reset of the pixel electrode Clc and the holding capacitor Cs2 through the third transistor T3. Transfer phase: By controlling the level changes of the transfer signal line Tran, the first common signal line Vcom_odd, and the second common signal line Vcom_even, the amount of charge transferred from the pre-storage capacitor Cs1 to the pixel electrode Clc is made so as to complete the writing of the preset data signal voltage to the pixel electrode Clc. The first common signal line Vcom_odd outputs a first AC drive signal, and the second common signal line Vcom_even outputs a second AC drive signal, wherein the first AC drive signal and the second AC drive signal have the same frequency but opposite polarities.

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