Launch driver

Abstract

A transmit driver comprising a plurality of stages is disclosed. Each of the plurality of stages includes a first circuit component configured to apply a first node voltage to a first node, a second circuit component configured to apply a second node voltage to a second node, and a fourth circuit component configured to apply a third node voltage to a third node. The second circuit part is configured to apply a second node voltage to the second node and is connected to the first circuit part through a third node, and the third circuit part is configured to apply a third node voltage of the third node or a voltage higher than the third node voltage to the fourth node based on the first node voltage and the second node voltage, the fourth circuit component is configured to generate a transmit signal based on the first node voltage and a fourth node voltage of the fourth node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0117136 filed in the Korean Intellectual Property Office on September 4, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to an emission driver and a display device. Background Art

[0004] With the development of information technology, the importance of display devices that provide information to users has increased, and the application of display devices such as liquid crystal display (LCD) devices and organic light-emitting display (OLED) devices has also increased.

[0005] The display device displays an image through a plurality of pixels. The display device may include an emission driver configured to supply an emission signal to determine emission timings of the plurality of pixels. Summary of the invention

[0006] The present disclosure may provide an emission driver and a display device including the emission driver, which are capable of supplying an emission signal having a uniform duty cycle.

[0007] The emission driver according to the embodiment includes a plurality of stages. Each of the plurality of stages includes: a first circuit component configured to apply a first node voltage to a first node; a second circuit component configured to apply a second node voltage to a second node and connected to the first circuit component through a third node; a third circuit component configured to apply a third node voltage of a third node or a voltage higher than the third node voltage to a fourth node based on the first node voltage and the second node voltage; and a fourth circuit component configured to generate an emission signal based on the first node voltage and the fourth node voltage of the fourth node.

[0008] The first circuit component and the second circuit component may have a circuit structure that is symmetrical about the third node.

[0009] The first circuit component and the second circuit component may receive the same input signal.

[0010] The third circuit component may include: a first transistor, the first transistor including a gate electrode connected to the first node, a first electrode connected to the third node, and a second electrode connected to the fourth node; and a second transistor, the second transistor including a gate electrode connected to the second node, a first electrode connected to the fourth node, and a second electrode configured to receive a first high voltage.

[0011] The third node voltage may be the first low voltage.

[0012] The fourth circuit component may include: a third transistor, the third transistor including a gate electrode connected to the first node, a first electrode configured to receive a second high voltage, and a second electrode connected to a first output terminal configured to output an emission signal; and a fourth transistor, the fourth transistor including a gate electrode connected to a fourth node, a first electrode connected to the first output terminal, and a second electrode configured to receive a second low voltage.

[0013] The first circuit component may include: a fifth transistor, the fifth transistor including a gate electrode connected to the first node, a first electrode configured to receive a clock signal, and a second electrode connected to the second output terminal; a first capacitor, the first capacitor including a first electrode connected to the first node and a second electrode connected to the second output terminal; a sixth transistor, the sixth transistor including a gate electrode connected to the fifth node, a first electrode connected to the second output terminal, and a second electrode connected to the third node; a second capacitor, the second capacitor including a first electrode connected to the fifth node and a second electrode connected to the third node; a seventh transistor, the seventh transistor including a gate electrode connected to the first input terminal, a first electrode configured to receive a first high voltage, and a second electrode connected to the first node; an eighth transistor, the eighth transistor including a gate electrode connected to the second input terminal, a first electrode configured to receive a first high voltage, and a second electrode connected to the fifth node; a ninth transistor, the ninth transistor including a gate electrode connected to the first node, a first electrode connected to the fifth node, and a second electrode connected to the third node; a 10-1 transistor a transistor, the 10-1 transistor including a gate electrode connected to a fifth node, a first electrode connected to a first node, and a second electrode; a 10-2 transistor, the 10-2 transistor including a gate electrode connected to a fifth node, a first electrode connected to a second electrode of the 10-1 transistor, and a second electrode connected to a third node; an 11-1 transistor, the 11-1 transistor including a gate electrode connected to a second input terminal, a first electrode connected to a first node, and a second electrode; an 11-2 transistor, the 11-2 transistor including a gate electrode connected to a second input terminal, a first electrode connected to a second electrode of the 11-1 transistor, and a second electrode connected to a third node; a 12-1 transistor, the 12-1 transistor including a gate electrode connected to a first node, a first electrode configured to receive a first high voltage, and a second electrode; and a 12-2 transistor, the 12-2 transistor including a gate electrode connected to a first node, a first electrode connected to a second electrode of the 12-1 transistor, and a second electrode connected to a second electrode of the 10-1 transistor and a second electrode of the 11-1 transistor.

[0014] The second circuit component may include: a thirteenth transistor, the thirteenth transistor includes a gate electrode connected to the second node, a first electrode configured to receive a clock signal, and a second electrode connected to the third output terminal; a third capacitor, the third capacitor includes a first electrode connected to the second node and a second electrode connected to the third output terminal; a fourteenth transistor, the fourteenth transistor includes a gate electrode connected to the sixth node, a first electrode connected to the third output terminal, and a second electrode connected to the third node; a fourth capacitor, the fourth capacitor includes a first electrode connected to the sixth node and a second electrode connected to the third node; a fifteenth transistor, the fifteenth transistor includes a gate electrode connected to the second input terminal, a first electrode configured to receive a first high voltage, and a second electrode connected to the second node; a sixteenth transistor, the sixteenth transistor includes a gate electrode connected to the first input terminal, a first electrode configured to receive the first high voltage, and a second electrode connected to the sixth node; a seventeenth transistor, the seventeenth transistor includes a gate electrode connected to the second node, a first electrode connected to the sixth node, and a second electrode connected to the third node; 18-1 transistor, the 18-1 transistor includes a gate electrode connected to a sixth node, a first electrode connected to a second node, and a second electrode; 18-2 transistor, the 18-2 transistor includes a gate electrode connected to the sixth node, a first electrode connected to the second electrode of the 18-1 transistor, and a second electrode connected to a third node; 19-1 transistor, the 19-1 transistor includes a gate electrode connected to a first input terminal, a first electrode connected to the second node, and a second electrode; 19-2 transistor, the 19-2 transistor includes a gate electrode connected to the first input terminal, a first electrode connected to the second electrode of the 19-1 transistor, and a second electrode connected to the third node; 20-1 transistor, the 20-1 transistor includes a gate electrode connected to the second node, a first electrode configured to receive a first high voltage, and a second electrode; and 20-2 transistor, the 20-2 transistor includes a gate electrode connected to the second node, a first electrode connected to the second electrode of the 20-1 transistor, and a second electrode connected to the second electrode of the 18-1 transistor and the second electrode of the 19-1 transistor.

[0015] The second output terminal may output a first low voltage or a clock signal.

[0016] The third output terminal may output the first low voltage or the clock signal, and the clock signal output by the second output terminal and the clock signal output by the third output terminal may not overlap with each other.

[0017] A display device according to an embodiment of the present disclosure includes a plurality of pixels and a plurality of stages, wherein the plurality of stages are configured to supply emission signals that determine the emission timing of the plurality of pixels. Each of the plurality of stages includes: a first circuit component, the first circuit component is configured to apply a first node voltage to a first node; a second circuit component, the second circuit component is configured to apply a second node voltage to a second node and is connected to the first circuit component through a third node; a third circuit component, the third circuit component is configured to apply a third node voltage of a third node or a voltage higher than the third node voltage to a fourth node based on the first node voltage and the second node voltage; and a fourth circuit component, the fourth circuit component is configured to generate an emission signal based on the first node voltage and the fourth node voltage of the fourth node.

[0018] The first circuit component and the second circuit component may have a circuit structure that is symmetrical about the third node.

[0019] The first circuit component and the second circuit component may receive the same input signal.

[0020] The third circuit component may include: a first transistor, the first transistor including a gate electrode connected to the first node, a first electrode connected to the third node, and a second electrode connected to the fourth node; and a second transistor, the second transistor including a gate electrode connected to the second node, a first electrode connected to the fourth node, and a second electrode configured to receive a first high voltage.

[0021] The third node voltage may be the first low voltage.

[0022] The fourth circuit component may include: a third transistor, the third transistor including a gate electrode connected to the first node, a first electrode configured to receive a second high voltage, and a second electrode connected to a first output terminal configured to output an emission signal; and a fourth transistor, the fourth transistor including a gate electrode connected to a fourth node, a first electrode connected to the first output terminal, and a second electrode configured to receive a second low voltage.

[0023] The first circuit component may include: a fifth transistor, the fifth transistor including a gate electrode connected to the first node, a first electrode configured to receive a clock signal, and a second electrode connected to the second output terminal; a first capacitor, the first capacitor including a first electrode connected to the first node and a second electrode connected to the second output terminal; a sixth transistor, the sixth transistor including a gate electrode connected to the fifth node, a first electrode connected to the second output terminal, and a second electrode connected to the third node; a second capacitor, the second capacitor including a first electrode connected to the fifth node and a second electrode connected to the third node; a seventh transistor, the seventh transistor including a gate electrode connected to the first input terminal, a first electrode configured to receive a first high voltage, and a second electrode connected to the first node; an eighth transistor, the eighth transistor including a gate electrode connected to the second input terminal, a first electrode configured to receive a first high voltage, and a second electrode connected to the fifth node; a ninth transistor, the ninth transistor including a gate electrode connected to the first node, a first electrode connected to the fifth node, and a second electrode connected to the third node; a 10-1 transistor a transistor, the 10-1 transistor including a gate electrode connected to a fifth node, a first electrode connected to a first node, and a second electrode; a 10-2 transistor, the 10-2 transistor including a gate electrode connected to a fifth node, a first electrode connected to a second electrode of the 10-1 transistor, and a second electrode connected to a third node; an 11-1 transistor, the 11-1 transistor including a gate electrode connected to a second input terminal, a first electrode connected to a first node, and a second electrode; an 11-2 transistor, the 11-2 transistor including a gate electrode connected to a second input terminal, a first electrode connected to a second electrode of the 11-1 transistor, and a second electrode connected to a third node; a 12-1 transistor, the 12-1 transistor including a gate electrode connected to a first node, a first electrode configured to receive a first high voltage, and a second electrode; and a 12-2 transistor, the 12-2 transistor including a gate electrode connected to a first node, a first electrode connected to a second electrode of the 12-1 transistor, and a second electrode connected to a second electrode of the 10-1 transistor and a second electrode of the 11-1 transistor.

[0024] The second circuit component may include: a thirteenth transistor, the thirteenth transistor includes a gate electrode connected to the second node, a first electrode configured to receive a clock signal, and a second electrode connected to the third output terminal; a third capacitor, the third capacitor includes a first electrode connected to the second node and a second electrode connected to the third output terminal; a fourteenth transistor, the fourteenth transistor includes a gate electrode connected to the sixth node, a first electrode connected to the third output terminal, and a second electrode connected to the third node; a fourth capacitor, the fourth capacitor includes a first electrode connected to the sixth node and a second electrode connected to the third node; a fifteenth transistor, the fifteenth transistor includes a gate electrode connected to the second input terminal, a first electrode configured to receive a first high voltage, and a second electrode connected to the second node; a sixteenth transistor, the sixteenth transistor includes a gate electrode connected to the first input terminal, a first electrode configured to receive the first high voltage, and a second electrode connected to the sixth node; a seventeenth transistor, the seventeenth transistor includes a gate electrode connected to the second node, a first electrode connected to the sixth node, and a second electrode connected to the third node; 18-1 transistor, the 18-1 transistor includes a gate electrode connected to a sixth node, a first electrode connected to a second node, and a second electrode; 18-2 transistor, the 18-2 transistor includes a gate electrode connected to the sixth node, a first electrode connected to the second electrode of the 18-1 transistor, and a second electrode connected to a third node; 19-1 transistor, the 19-1 transistor includes a gate electrode connected to a first input terminal, a first electrode connected to the second node, and a second electrode; 19-2 transistor, the 19-2 transistor includes a gate electrode connected to the first input terminal, a first electrode connected to the second electrode of the 19-1 transistor, and a second electrode connected to the third node; 20-1 transistor, the 20-1 transistor includes a gate electrode connected to the second node, a first electrode configured to receive a first high voltage, and a second electrode; and 20-2 transistor, the 20-2 transistor includes a gate electrode connected to the second node, a first electrode connected to the second electrode of the 20-1 transistor, and a second electrode connected to the second electrode of the 18-1 transistor and the second electrode of the 19-1 transistor.

[0025] The second output terminal may output a first low voltage or a clock signal.

[0026] The third output terminal may output the first low voltage or the clock signal, and the clock signal output by the second output terminal and the clock signal output by the third output terminal may not overlap with each other.

[0027] The emission driver and the display device including the emission driver according to the embodiments of the present disclosure may supply an emission signal having a uniform duty ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a view illustrating a display device according to an embodiment of the present disclosure.

[0029] Figure 2 is a view illustrating a pixel according to an embodiment of the present disclosure.

[0030] Figure 3 is a view illustrating a case where the display device is driven at a normal frequency.

[0031] Figure 4 is a view illustrating a case where a display device is driven at a low frequency.

[0032] Figure 5 and Figure 6 is a timing diagram illustrating a pixel driving method.

[0033] Figure 7 is a view illustrating a pixel according to another embodiment of the present disclosure.

[0034] Figure 8 is a view illustrating a transmit driver according to an embodiment of the present disclosure.

[0035] Fig. 9 It is a graphic driver Figure 8 The timing diagram of the transmit driver method is shown in FIG.

[0036] Fig.10 is a view illustrating a stage of a transmit driver according to an embodiment of the present disclosure.

[0037] Fig.11 It is a graphic Fig.10 A timing diagram of the operation of the stages shown in FIG. DETAILED DESCRIPTION

[0038] Hereinafter, with reference to the accompanying drawings, various embodiments of the present disclosure will be described in detail so that those skilled in the art to which the present disclosure belongs can easily put the present disclosure into practice. The present disclosure can be implemented in various different forms and is not limited to the embodiments described herein.

[0039] For the purpose of brevity of the present disclosure, parts not related to the description are omitted, and the same reference numerals will refer to the same or similar parts throughout the specification. Therefore, the reference numerals described above can also be used in other figures.

[0040] In addition, for ease of understanding, the sizes and thicknesses of corresponding elements in the drawings are arbitrarily illustrated, and the present disclosure is not limited to those shown in the drawings. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity of description.

[0041] In addition, the expression "same" used herein may mean "substantially the same". That is, when two objects are referred to as "same", a person of ordinary skill in the art will not see any significant differences between the two objects. Other expressions may also be expressions that omit "substantially".

[0042] Figure 1 is a view illustrating a display device according to an embodiment of the present disclosure.

[0043] refer to Figure 1 , a display device 10 according to an embodiment of the present disclosure includes a timing controller 11 , a data driver 12 , a scan driver 13 , a pixel part 14 , an initialization power supply 15 , and an emission driver 16 .

[0044] The timing controller 11 may receive frame information and control signals from an external processor. The timing controller 11 may convert the received frame information and control signals according to the specifications of the display device 10, and provide the converted frame information and control signals to the data driver 12, the scan driver 13, and the emission driver 16. For example, the timing controller 11 may provide the data driver 12 with grayscale values ​​and control signals for corresponding pixels of the pixel part 14. In addition, the timing controller 11 may provide control signals such as a clock signal and a clock start signal to the scan driver 13. In addition, the timing controller 11 may provide control signals such as a clock signal and an emission stop signal to the emission driver 16.

[0045] The data driver 12 may generate data voltages to be supplied to the data lines D1 to Dm (which may include data lines D1, D2, D3, Dj, and Dm) using grayscale values ​​and control signals received from the timing controller 11. Here, m may be an integer equal to or greater than 1.

[0046] The scan driver 13 may generate a first scan signal to be supplied to the first scan lines S11 to S1n (the first scan lines S11 to S1n may include the first scan lines S11, S12, S1i, and S1n) and a second scan signal to be supplied to the second scan lines S21 to S2n (the second scan lines S21 to S2n may include the second scan lines S21, S22, S2i, and S2n) by receiving a control signal such as a clock signal and a scan start signal from the timing controller 11. Here, n may be an integer equal to or greater than 1.

[0047] The emission driver 16 may generate emission signals to be provided to the emission lines E1 to En (the emission lines E1 to En may include emission lines E1 , E2 , Ei, and En) by receiving control signals such as a clock signal and an emission stop signal from the timing controller 11 .

[0048] The initialization power supply 15 may supply an initialization voltage to the initialization lines I1 to Im (the initialization lines I1 to Im may include initialization lines I1 , I2 , I3 , Ij, and Im).

[0049] The pixel part 14 includes a plurality of pixels. For example, the pixel PXij can be connected to corresponding lines including the data line Dj, the first scan line S1i, the second scan line S2i, the emission line Ei and the initialization line Ij. In addition, the pixel PXij can be connected to the first power line ELVDD and the second power line ELVSS.

[0050] Figure 2 is a view illustrating a pixel according to an embodiment of the present disclosure.

[0051] refer to Figure 2 , the pixel PXij according to an embodiment of the present disclosure may include transistors T1 , T2 , T3 , and T4 , a storage capacitor Cst, and a light emitting diode LD.

[0052] Although it is assumed in the following text that transistors T1 to T4 are implemented using N-type transistors (e.g., NMOS), a person of ordinary skill in the art to which the present disclosure pertains may implement transistors T1 to T4 using P-type transistors (e.g., PMOS), or a combination of N-type transistors and P-type transistors.

[0053] The first transistor T1 may have a gate electrode connected to the first node N1, one electrode connected to the second node N2, and the other electrode connected to one electrode of the fourth transistor T4. The first transistor T1 may be referred to as a driving transistor.

[0054] The second transistor T2 may have a gate electrode connected to the first scan line S1i, one electrode connected to the data line Dj, and the other electrode connected to the first node N1. The second transistor T2 may be referred to as a scan transistor, a switching transistor, or the like.

[0055] The third transistor T3 may have a gate electrode connected to the second scan line S2i, one electrode connected to the second node N2, and the other electrode connected to the initialization line Ij. The third transistor T3 may be referred to as an initialization transistor.

[0056] The fourth transistor T4 may have a gate electrode connected to the emission line Ei, one electrode connected to the other electrode of the first transistor T1, and the other electrode connected to the first power line ELVDD.

[0057] The storage capacitor Cst may have one electrode connected to the first node N1 and the other electrode connected to the second node N2 .

[0058] The light emitting diode LD may have an anode connected to the second node N2 and a cathode connected to the second power line ELVSS. The light emitting diode LD may be implemented as an organic light emitting diode (OLED), an inorganic light emitting diode, a quantum dot light emitting diode, or the like.

[0059] In addition, despite Figure 2 A single light emitting diode LD is illustrated in FIG. 1 , but the light emitting diode LD may be implemented as a plurality of micro light emitting diodes. For example, a plurality of micro light emitting diodes may be arranged in parallel with the same polarity or with different polarities.

[0060] Figure 3 is a view illustrating a case where a display device is driven at a normal frequency (or operating frequency).

[0061] When the display device 10 (for example, referring to Figure 1 ) is a normal frequency (normal frequency mode), a single cycle may include a plurality of scanning cycles WF1, WF2, WF3, ..., WF (p-1) and WFp. p may be an integer equal to or greater than 1. For example, when a single cycle is 1 second and the driving frequency is 60 Hz, p may be 60. Here, each scanning cycle of the scanning cycles WF1, WF2, WF3, ..., WF (p-1) and WFp may correspond to a frame cycle. For example, a single cycle may include 60 frame cycles.

[0062] During each scanning period of scanning periods WF1, WF2, WF3, ..., WF(p-1), and WFp, each of the plurality of pixels may be provided with a corresponding data voltage. For example, when p is 60, the data voltage of each of the plurality of pixels may be updated 60 times during a single period.

[0063] Figure 4 is a view illustrating a case where a display device is driven at a low frequency.

[0064] When the display device 10 (for example, referring to Figure 1 ) is a low frequency (low frequency mode), a single cycle may include a single scanning cycle WF1 and subsequent self-scanning cycles NWF1, NWF2, ..., NWF (p-2) and NWF (p-1). For example, when a single cycle may be 1 second and the driving frequency is 1 Hz, p may be 60. Here, the signal cycle may correspond to a single frame cycle.

[0065] During the scanning period WF1, each of the plurality of pixels may be provided with a corresponding data voltage. During the self-scanning period NWF1 to NWF(p-1), each of the plurality of pixels may not be provided with a data voltage. Therefore, when p is 60, the data voltage of each of the plurality of pixels may be updated once during a single period.

[0066] Figure 5 and Figure 6 is a timing diagram illustrating a pixel driving method.

[0067] refer to Figure 5 During the first period P1a of the scanning period WF171, a first scanning signal having a turn-on level (eg, a logic high level) may be applied to the first scanning line S1i, and a data voltage may be applied to the data line Dj (eg, reference voltage). Figure 2 ), and a second scan signal having a turn-on level may be applied to the second scan line S2i.

[0068] During the third period P3a of the scanning cycle WF171, an emission signal having an off level (e.g., a logic low level) may be applied to the emission line Ei. The third period P3a may be a period including the first period P1a. When an emission signal having an on level is applied to the emission line Ei, the light emitting diode LD (e.g., reference Figure 2 ) may generate light with brightness based on the data voltage. When an emission signal having an off level is applied to the emission line Ei, the light emitting diode LD may be in a non-emission state.

[0069] During the scanning period WF171, the first scanning signal with the on level may be sequentially supplied to the first scanning lines S1(i-1), S1i, and S1(i+1). In addition, the second scanning signal with the on level may be maintained in the second scanning lines S21 to S2n. In another embodiment, the second scanning signal with the on level may be sequentially supplied to the second scanning lines S21 to S2n. Here, the second scanning signal with the on level may be synchronized with the first scanning signal with the on level.

[0070] For example, refer to Figure 2, when the first scan signal with a turn-on level is applied to the first scan line S1i, the second transistor T2 of the pixel PXij is turned on, and the data voltage is applied to the first node N1. In addition, when the second scan signal with a turn-on level is applied to the second scan line S2i, the third transistor T3 of the pixel PXij is turned on, and the initialization voltage is applied to the second node N2. Therefore, the storage capacitor Cst can store the difference between the voltages of the first node N1 and the second node N2 therein. Here, since the emission signal with an off level is applied to the emission line Ei, the fourth transistor T4 can be in an off state, and the driving current does not flow from the first power line ELVDD to the second power line ELVSS. Therefore, the light emitting diode LD is in a non-emission state.

[0071] Next, an emission signal having a turn-on level is applied to the emission line Ei. The fourth transistor T4 is in a turn-on state, and a drive current can flow from the first power line ELVDD to the second power line ELVSS. Here, the amount of the drive current is adjusted by the first transistor T1 according to the voltage difference stored in the storage capacitor Cst. Therefore, the light emitting diode LD can generate light with a brightness proportional to the amount of the drive current. Here, the second transistor T2 is in an off state, and therefore the storage capacitor Cst, to which the first node N1 is floated, can maintain the stored voltage difference.

[0072] refer to Figure 6 During the second period P2a of the self-scanning period NWF171, the first scan signal having an off level may be applied to the first scan line S1i, and the second scan signal having an on level may be applied to the second scan line S2i. During the fourth period P4a of the self-scanning period NWF171, the emission signal having an off level may be applied to the emission line Ei. The second period P2a may be a period including the fourth period P4a.

[0073] The self-scan period NWF171 may be a period after the scan period WF171. During at least a portion of the scan period WF171 and the self-scan period NWF171, the light emitting diode LD may generate light at a brightness based on a data voltage supplied in the scan period WF171.

[0074] During the self scanning period NWF171, the first scan signal having an off level may be maintained on the first scan lines S1(i-1), S1i, and S1(i+1). In addition, the second scan signal having an on level may be maintained on the second scan lines S21 to S2n.

[0075] Figure 7 is a view illustrating a pixel according to another embodiment of the present disclosure.

[0076] exist Figure 7 In the pixel PXij' shown in Figure 2 Compared with the pixel PXij shown in FIG. 1 , the position of the fourth transistor T4′ is changed. The fourth transistor T4′ may be located between the second node N2 and the light emitting diode LD. Other configurations and driving methods of the pixel PXij′ are similar to those of FIG. Figure 2 The configuration and driving method of the pixel PXij shown in FIG. 1 are the same, and therefore a description thereof will be omitted.

[0077] Figure 8 is a view illustrating a transmit driver according to an embodiment of the present disclosure.

[0078] refer to Figure 8 , the emission driver 16 according to an embodiment of the present disclosure may include a plurality of stages ST1 , ST2 , ST3 , ST4 , . . . , and STn.

[0079] Each of stages ST1, ST2, ST3, ST4, ... and STn may include a first input terminal IN1, a second input terminal IN2, a first voltage terminal V1, a second voltage terminal V2, a third voltage terminal V3, a fourth voltage terminal V4, a clock terminal CK, a first output terminal OUT1, a second output terminal OUT2 and a third output terminal OUT3.

[0080] The emission driver 16 may be implemented as a shift register. The first stage ST1 may receive a first emission stop signal STV1 through a first input terminal IN1, and receive a second emission stop signal STV2 through a second input terminal IN2. In addition, based on the first emission stop signal STV1 and the second emission stop signal STV2, the first stage ST1 may output an emission signal having an off level through a first output terminal OUT1 connected to an emission line E1, output a first carry signal CRA1 through a second output terminal OUT2, and output a second carry signal CRB1 through a third output terminal OUT3. The second stage ST2 may receive a first carry signal CRA1 through a first input terminal IN1, and receive a second carry signal CRB1 through a second input terminal IN2. In addition, based on the first carry signal CRA1 and the second carry signal CRB1, the second stage ST2 may output an emission signal having an off level through a first output terminal OUT1 connected to an emission line E2, output a first carry signal CRA2 through a second output terminal OUT2, and output a second carry signal CRB2 through a third output terminal OUT3. In this way, as the first carry signals CRA2, CRA3, CRA4, ... and CRA(n-1) and the second carry signals CRB2, CRB3, CRB4, ... and CRB(n-1) are sequentially transmitted to the last nth stage STn through the third stage ST3 and the fourth stage ST4, the emission signal with the off level can be sequentially applied to the emission lines E3, E4, ... and En.

[0081] The odd-numbered stages ST1 and ST3 , etc. may receive the first clock signal CLK1 through the clock terminal CK. The even-numbered stages ST2 , ST4 , . . . , and STn may receive the second clock signal CLK2 through the clock terminal CK.

[0082] Stages ST1, ST2, ST3, ST4, ... and STn may receive a first high voltage VGH1 through a first voltage terminal V1, a second high voltage VGH2 through a second voltage terminal V2, a first low voltage VGL1 through a third voltage terminal V3, and a second low voltage VGL2 through a fourth voltage terminal V4. The first high voltage VGH1 and the second high voltage VGH2 may be set to be the same or different from each other. The first low voltage VGL1 and the second low voltage VGL2 may be set to be the same or different from each other.

[0083] Fig. 9 It is a graphic driver Figure 8 The timing diagram of the transmit driver method is shown in FIG.

[0084] The pulses (with a logic high level) of the first clock signal CLK1 and the second clock signal CLK2 may not overlap each other. The first clock signal CLK1 and the second clock signal CLK2 may be 180 degrees out of phase. For example, the second clock signal CLK2 may be an inversion signal of the first clock signal CLK1. The second emission stop signal STV2 may be an inversion signal of the first emission stop signal STV1.

[0085] When the first emission stop signal STV1 having an off level is supplied to the first stage ST1, the first stage ST1 may supply an emission signal having an off level to the emission line E1. Here, all pixels connected to the emission line E1 may be converted into a non-emission state. Thereafter, when the first emission stop signal STV1 having an on level is supplied to the first stage ST1, the first stage ST1 may supply an emission signal having an on level to the emission line E1. Here, all pixels connected to the emission line E1 may be converted into an emission state. The sum of a single non-emission state period and a single emission state period may be a single frame period 1FRAME.

[0086] As described above, as the carry signal is sequentially transmitted, the emission signal having the off level may be sequentially supplied to the emission lines E2, E3, and E4, . . . . . . . . . . . .

[0087] Fig.10 is a view illustrating a stage of a transmit driver according to an embodiment of the present disclosure. Fig.11 It is a graphic Fig.10 A timing diagram of the operation of the stages shown in FIG.

[0088] refer to Fig.10 , the stage STi may include a first circuit component 101 , a second circuit component 102 , a third circuit component 103 and a fourth circuit component 104 .

[0089] refer to Fig.10 and Fig.11 , the first circuit component 101 may apply the first node voltage N1V to the first node N1. The second circuit component 102 may apply the second node voltage N2V to the second node N2 and be connected to the first circuit component 101 through the third node N3. The first low voltage VGL1 may be applied to the third node N3.

[0090] refer to Fig.10, the first circuit component 101 and the second circuit component 102 may have a circuit structure symmetrical about the third node N3. For example, the second circuit component 102 may include the same number of transistors as the first circuit component 101 and the same number of capacitors as the first circuit component 101. The connection relationship between the elements of the second circuit component 102 may be the same as the connection relationship between the elements of the first circuit component 101. The first circuit component 101 and the second circuit component 102 may receive the same input signal (for example, the clock signal CLK, the first carry signal CRA(i-1), the second carry signal CRB(i-1), the first high voltage VGH1 and the first low voltage VGL1). For example, when the stage STi is an odd-numbered stage, the clock signal CLK may be the first clock signal CLK1 (for example, reference Figure 8 ). When the stage STi is an even-numbered stage, the clock signal CLK may be a second clock signal CLK2 (eg, reference Figure 8 ).

[0091] The third circuit part 103 may apply a third node voltage of the third node N3 or a voltage higher than the third node voltage to the fourth node N4 based on the first node voltage N1V and the second node voltage N2V.

[0092] The fourth circuit part 104 may generate an emission signal based on the first node voltage N1V and a fourth node voltage of the fourth node N4. The generated emission signal may be applied to the emission line Ei through the first output terminal OUT1.

[0093] The third circuit part 103 may include transistors TE1 and TE2. The first transistor TE1 may have a gate electrode connected to the first node N1, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. The second transistor TE2 may have a gate electrode connected to the second node N2, a first electrode connected to the fourth node N4, and a second electrode configured to receive the first high voltage VGH1.

[0094] The fourth circuit part 104 may include transistors TE3 and TE4. The third transistor TE3 may have a gate electrode connected to the first node N1, a first electrode configured to receive the second high voltage VGH2, and a second electrode connected to the first output terminal OUT1. The fourth transistor TE4 may have a gate electrode connected to the fourth node N4, a first electrode connected to the first output terminal OUT1, and a second electrode configured to receive the second low voltage VGL2.

[0095] The first circuit part 101 may include transistors TE5 to TE12b and capacitors C1 and C2. The fifth transistor TE5 may have a gate electrode connected to the first node N1, a first electrode configured to receive the clock signal CLK, and a second electrode connected to the second output terminal OUT2. The first capacitor C1 may have a first electrode connected to the first node N1 and a second electrode connected to the second output terminal OUT2.

[0096] The sixth transistor TE6 may have a gate electrode connected to the fifth node N5, a first electrode connected to the second output terminal OUT2, and a second electrode connected to the third node N3. The second capacitor C2 may have a first electrode connected to the fifth node N5 and a second electrode connected to the third node N3. The second output terminal OUT2 may output the first low voltage VGL1 or the clock signal CLK as the first carry signal CRAi.

[0097] The seventh transistor TE7 may have a gate electrode connected to the first input terminal IN1, a first electrode configured to receive the first high voltage VGH1, and a second electrode connected to the first node N1. The eighth transistor TE8 may have a gate electrode connected to the second input terminal IN2, a first electrode configured to receive the first high voltage VGH1, and a second electrode connected to the fifth node N5. The ninth transistor TE9 may have a gate electrode connected to the first node N1, a first electrode connected to the fifth node N5, and a second electrode connected to the third node N3.

[0098] The 10-1th transistor TE10a may have a gate electrode connected to the fifth node N5, a first electrode connected to the first node N1, and a second electrode. The 10-2th transistor TE10b may have a gate electrode connected to the fifth node N5, a first electrode connected to the second electrode of the 10-1th transistor TE10a, and a second electrode connected to the third node N3.

[0099] The 11-1th transistor TE11a may have a gate electrode connected to the second input terminal IN2, a first electrode connected to the first node N1, and a second electrode. The 11-2th transistor TE11b may have a gate electrode connected to the second input terminal IN2, a first electrode connected to the second electrode of the 11-1th transistor TE11a, and a second electrode connected to the third node N3.

[0100] The 12-1st transistor TE12a may have a gate electrode connected to the first node N1, a first electrode configured to receive the first high voltage VGH1, and a second electrode. The 12-2nd transistor TE12b may have a gate electrode connected to the first node N1, a first electrode connected to the second electrode of the 12-1st transistor TE12a, and a second electrode connected to the second electrode of the 10-1st transistor TE10a and the second electrode of the 11-1st transistor TE11a.

[0101] The second circuit part 102 may include transistors TE13 to TE20b and capacitors C3 and C4. The thirteenth transistor TE13 may have a gate electrode connected to the second node N2, a first electrode configured to receive the clock signal CLK, and a second electrode connected to the third output terminal OUT3. The third capacitor C3 may have a first electrode connected to the second node N2 and a second electrode connected to the third output terminal OUT3.

[0102] The fourteenth transistor TE14 may have a gate electrode connected to the sixth node N6, a first electrode connected to the third output terminal OUT3, and a second electrode connected to the third node N3. The fourth capacitor C4 may have a first electrode connected to the sixth node N6 and a second electrode connected to the third node N3. The third output terminal OUT3 may output the first low voltage VGL1 or the clock signal CLK as the second carry signal CRBi. The clock signal CLK outputted by the second output terminal OUT2 and the clock signal CLK outputted by the third output terminal OUT3 may not overlap in time.

[0103] The fifteenth transistor TE15 may have a gate electrode connected to the second input terminal IN2, a first electrode configured to receive the first high voltage VGH1, and a second electrode connected to the second node N2. The sixteenth transistor TE16 may have a gate electrode connected to the first input terminal IN1, a first electrode configured to receive the first high voltage VGH1, and a second electrode connected to the sixth node N6. The seventeenth transistor TE17 may have a gate electrode connected to the second node N2, a first electrode connected to the sixth node N6, and a second electrode connected to the third node N3.

[0104] The 18-1st transistor TE18a may have a gate electrode connected to the sixth node N6, a first electrode connected to the second node N2, and a second electrode. The 18-2nd transistor TE18b may have a gate electrode connected to the sixth node N6, a first electrode connected to the second electrode of the 18-1st transistor TE18a, and a second electrode connected to the third node N3.

[0105] The 19-1st transistor TE19a may have a gate electrode connected to the first input terminal IN1, a first electrode connected to the second node N2, and a second electrode. The 19-2nd transistor TE19b may have a gate electrode connected to the first input terminal IN1, a first electrode connected to the second electrode of the 19-1st transistor TE19a, and a second electrode connected to the third node N3.

[0106] The 20-1st transistor TE20a may have a gate electrode connected to the second node N2, a first electrode configured to receive the first high voltage VGH1, and a second electrode. The 20-2nd transistor TE20b may have a gate electrode connected to the second node N2, a first electrode connected to the second electrode of the 20-1st transistor TE20a, and a second electrode connected to the second electrode of the 18-1st transistor TE18a and the second electrode of the 19-1st transistor TE19a.

[0107] refer to Fig.11 , will describe Fig.10 The operation of the stage STi shown in . First, at time point t1a, the second carry signal CRB (i-1) received from the i-1 stage includes a clock signal that is inconsistent with the phase of the clock signal CLK. Here, the first carry signal CRA (i-1) received from the i-1 stage can correspond to the first low voltage VGL1. The eighth transistor TE8 can be turned on based on the second carry signal CRB (i-1), and the fifth node voltage N5V of the fifth node N5 can be the first high voltage VGH1. Here, since the fifth node voltage N5V is maintained by the second capacitor C2, even if the second carry signal CRB (i-1) has a low level, the fifth node voltage N5V can also maintain a high level, and therefore the eighth transistor TE8 is turned off. Therefore, the sixth transistor TE6 can be turned on, and the first low voltage VGL1 can be applied to the second output terminal OUT2 as the first carry signal CRAi.

[0108] When the fifth node voltage N5V has a high level, the 10-1st transistor TE10a and the 10-2nd transistor TE10b may be turned on, and the first low voltage VGL1 may be applied to the first node N1. In addition, in response to the second carry signal CRB(i-1), the 11-1st transistor TE11a and the 11-2nd transistor TE11b are turned on, and thus the first low voltage VGL1 may be applied to the first node N1. Therefore, the first node voltage N1V may have a low level.

[0109] In addition, based on the second carry signal CRB (i-1), the fifteenth transistor TE15 can be turned on, and the second node voltage N2V of the second node N2 can be the first high voltage VGH1. Here, the 20-1 transistor TE20a and the 20-2 transistor TE20b can be turned on, and thus the first high voltage VGH1 can be applied to the second electrode of the 18-1 transistor TE18a and the 19-1 transistor TE19a. Therefore, the leakage current through the 18-1 transistor TE18a and the 19-1 transistor TE19a can be prevented, and thus the voltage of the second node N2 can be maintained at a high level. When the second node voltage N2V has a high level, the thirteenth transistor TE13 can be turned on, and the clock signal CLK can be applied to the third output terminal OUT3 as the second carry signal CRBi. In addition, when the seventeenth transistor TE17 is turned on, the sixth node voltage N6V of the sixth node N6 can be the first low voltage VGL1.

[0110] In addition, the second transistor TE2 is turned on by the second node voltage N2V having a high level, and the first high voltage VGH1 is applied to the fourth node N4. Therefore, the difference between the gate voltage and the source voltage of the fourth transistor TE4 can be stably maintained, and the voltage of the first output terminal OUT1 can be quickly discharged to the second low voltage VGL2. That is, the emission signal on the emission line Ei can be quickly discharged to a low level. According to this embodiment, the voltage drop rate reduced by the parasitic capacitance between the fourth node N4 and the first output terminal OUT1 can be compensated. If the second transistor TE2 is not present, the duty cycle of the second carry signal CRBi and the emission signal may increase unintentionally and gradually as the next stage is advanced. According to this embodiment including the second transistor TE2, the display device 10 can supply an emission signal with a uniform duty cycle.

[0111] At time point t2a, the first carry signal CRA (i-1) received from the i-1th level includes a clock signal inconsistent with the phase of the clock signal CLK. Here, the second carry signal CRB (i-1) received from the i-1th level can correspond to the first low voltage VGL1. The sixteenth transistor TE16 can be turned on based on the first carry signal CRA (i-1), and the sixth node voltage N6V can be the first high voltage VGH1. Here, since the sixth node voltage N6V is maintained by the fourth capacitor C4, when the first carry signal CRA (i-1) has a low level, the sixth node voltage N6V can maintain a high level, and therefore the sixteenth transistor TE16 is turned off. Therefore, the fourteenth transistor TE14 can be turned on, and the first low voltage VGL1 can be applied to the third output terminal OUT3 as the second carry signal CRBi.

[0112] When the sixth node voltage N6V has a high level, the 18-1st transistor TE18a and the 18-2nd transistor TE18b may be turned on, and thus the first low voltage VGL1 may be applied to the second node N2. In addition, in response to the first carry signal CRA(i-1), the 19-1st transistor TE19a and the 19-2nd transistor TE19b may be turned on, and thus the first low voltage VGL1 may be applied to the second node N2. Therefore, the second node voltage N2V may have a low level.

[0113] In addition, the seventh transistor TE7 may be turned on based on the first carry signal CRA(i-1), and the first node voltage N1V of the first node N1 may be the first high voltage VGH1. Here, the 12-1st transistor TE12a and the 12-2nd transistor TE12b may be turned on, and thus the first high voltage VGH1 may be applied to the second electrode of the 10-1st transistor TE10a and the 11-1st transistor TE11a. Therefore, leakage current through the 10-1st transistor TE10a and the 11-1st transistor TE11a may be prevented, and thus the voltage of the first node N1 may be maintained at a high level. When the voltage of the first node N1 has a high level, the fifth transistor TE5 may be turned on, and the clock signal CLK may be applied to the second output terminal OUT2 as the first carry signal CRAi. In addition, when the ninth transistor TE9 is turned on, the fifth node voltage N5V of the fifth node N5 may be the first low voltage VGL1.

[0114] In addition, the first transistor TE1 and the third transistor TE3 can be turned on by the first node voltage N1V having a high level. The turned-on first transistor TE1 can turn off the fourth transistor TE4 by supplying the first low voltage VGL1 to the fourth node N4. The turned-on third transistor TE3 can apply the second high voltage VGH2 to the first output terminal OUT1 as an emission signal.

[0115] At time point t3a, the same driving method as that at time point t1a is repeated. Therefore, repeated description of the subsequent process will be omitted. The sum of the period P1 in which the emission signal has a low level and the period P2 in which the emission signal has a high level may correspond to a single frame period 1FRAME.

[0116] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the scope and spirit of the disclosure as set forth in the appended claims.

Claims

1. A transmit driver comprising a plurality of stages, wherein: Each of the plurality of stages comprises: a first circuit component configured to apply a first node voltage to a first node; a second circuit component configured to apply a second node voltage to a second node and connected to the first circuit component through a third node; a third circuit component configured to apply a third node voltage of the third node or a voltage higher than the third node voltage to a fourth node based on the first node voltage and the second node voltage; and A fourth circuit component is configured to generate a transmission signal based on the first node voltage and a fourth node voltage of the fourth node.

2. The transmit driver according to claim 1, wherein: The first circuit component and the second circuit component have a circuit structure that is symmetrical about the third node.

3. The transmit driver according to claim 2, wherein: The first circuit component and the second circuit component receive the same input signal.

4. The transmit driver according to claim 1, wherein: The third circuit component comprises: a first transistor including a gate electrode connected to the first node, a first electrode connected to the third node, and a second electrode connected to the fourth node; and A second transistor includes a gate electrode connected to the second node, a first electrode connected to the fourth node, and a second electrode configured to receive a first high voltage.

5. The transmit driver according to claim 4, wherein: The third node voltage is a first low voltage.

6. The transmit driver according to claim 5, wherein: The fourth circuit component comprises: a third transistor including a gate electrode connected to the first node, a first electrode configured to receive a second high voltage, and a second electrode connected to a first output terminal configured to output the emission signal; and A fourth transistor includes a gate electrode connected to the fourth node, a first electrode connected to the first output terminal, and a second electrode configured to receive a second low voltage.

7. The transmit driver according to claim 6, wherein: The first circuit component comprises: a fifth transistor including a gate electrode connected to the first node, a first electrode configured to receive a clock signal, and a second electrode connected to a second output terminal; a first capacitor including a first electrode connected to the first node and a second electrode connected to the second output terminal; a sixth transistor including a gate electrode connected to a fifth node, a first electrode connected to the second output terminal, and a second electrode connected to the third node; a second capacitor including a first electrode connected to the fifth node and a second electrode connected to the third node; a seventh transistor including a gate electrode connected to the first input terminal, a first electrode configured to receive the first high voltage, and a second electrode connected to the first node; an eighth transistor including a gate electrode connected to the second input terminal, a first electrode configured to receive the first high voltage, and a second electrode connected to the fifth node; a ninth transistor including a gate electrode connected to the first node, a first electrode connected to the fifth node, and a second electrode connected to the third node; a 10-1th transistor, the 10-1th transistor including a gate electrode connected to the fifth node, a first electrode connected to the first node, and a second electrode; a 10-2 transistor, the 10-2 transistor including a gate electrode connected to the fifth node, a first electrode connected to the second electrode of the 10-1 transistor, and a second electrode connected to the third node; an 11-1th transistor, the 11-1th transistor including a gate electrode connected to the second input terminal, a first electrode connected to the first node, and a second electrode; an 11-2th transistor, the 11-2th transistor including a gate electrode connected to the second input terminal, a first electrode connected to the second electrode of the 11-1th transistor, and a second electrode connected to the third node; a 12-1th transistor, the 12-1th transistor including a gate electrode connected to the first node, a first electrode configured to receive the first high voltage, and a second electrode; and A 12-2 transistor including a gate electrode connected to the first node, a first electrode connected to the second electrode of the 12-1 transistor, and a second electrode connected to the second electrode of the 10-1 transistor and the second electrode of the 11-1 transistor.

8. The transmit driver according to claim 7, wherein: The second circuit component comprises: a thirteenth transistor including a gate electrode connected to the second node, a first electrode configured to receive the clock signal, and a second electrode connected to a third output terminal; a third capacitor including a first electrode connected to the second node and a second electrode connected to the third output terminal; a fourteenth transistor including a gate electrode connected to the sixth node, a first electrode connected to the third output terminal, and a second electrode connected to the third node; a fourth capacitor including a first electrode connected to the sixth node and a second electrode connected to the third node; a fifteenth transistor including a gate electrode connected to the second input terminal, a first electrode configured to receive the first high voltage, and a second electrode connected to the second node; a sixteenth transistor including a gate electrode connected to the first input terminal, a first electrode configured to receive the first high voltage, and a second electrode connected to the sixth node; a seventeenth transistor including a gate electrode connected to the second node, a first electrode connected to the sixth node, and a second electrode connected to the third node; an 18-1 transistor, the 18-1 transistor including a gate electrode connected to the sixth node, a first electrode connected to the second node, and a second electrode; an 18-2 transistor, the 18-2 transistor including a gate electrode connected to the sixth node, a first electrode connected to the second electrode of the 18-1 transistor, and a second electrode connected to the third node; a 19-1th transistor, the 19-1th transistor including a gate electrode connected to the first input terminal, a first electrode connected to the second node, and a second electrode; a 19-2 transistor, the 19-2 transistor including a gate electrode connected to the first input terminal, a first electrode connected to the second electrode of the 19-1 transistor, and a second electrode connected to the third node; a 20-1th transistor, the 20-1th transistor including a gate electrode connected to the second node, a first electrode configured to receive the first high voltage, and a second electrode; and A 20-2 transistor including a gate electrode connected to the second node, a first electrode connected to the second electrode of the 20-1 transistor, and a second electrode connected to the second electrode of the 18-1 transistor and the second electrode of the 19-1 transistor.

9. The transmit driver according to claim 8, wherein: The second output terminal outputs the first low voltage or the clock signal.

10. The transmit driver according to claim 9, wherein: The third output terminal outputs the first low voltage or the clock signal, and The clock signal output by the second output terminal and the clock signal output by the third output terminal do not overlap with each other.

Images