Display device

Abstract

A display device is disclosed. The display device includes: a substrate; the light emitting diode is arranged on the substrate; a plurality of patterns disposed on the light emitting diodes and having a ring shape; and a capping layer on the plurality of patterns, in which the light emitting diode is a micro light emitting diode.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, for example, but not limited to, to a display device using a light emitting diode (LED). Background Art

[0002] As display devices used for displays of computer monitors, televisions, cellular phones, and the like, there are organic light emitting display (OLED) devices that are self-luminous devices, liquid crystal display (LCD) devices that require a separate light source, and the like.

[0003] The application range of the display device is diversified to personal digital assistants as well as monitors of televisions and computers, and display devices having a large display area and reduced volume and weight are being studied.

[0004] In addition, recently, a display device including a light emitting diode (LED) is attracting attention as a next-generation display device. Since LED is formed of an inorganic material rather than an organic material, it has excellent reliability, making its lifespan longer than that of a liquid crystal display device or an organic light emitting display device. In addition, LED has a fast light emission speed, excellent light emission efficiency, and strong impact resistance, so that it has excellent stability and can display images with high brightness.

[0005] The description provided in the description of the background technology section should not be assumed to be prior art simply because it is mentioned in the description of the background technology section or is associated with the description of the background technology section. The description of the background technology section may include information describing one or more aspects of the subject technology, and the description in this part does not limit the present invention. Summary of the invention

[0006] The inventors have recognized the requirements and limitations in terms of brightness of a display device. Therefore, an object to be achieved by the present disclosure is to provide a display device with increased front brightness.

[0007] Another object to be achieved by the present disclosure is to provide a display device that improves brightness deviation according to a viewing angle.

[0008] Another object of the present disclosure is to provide a display device that improves the mura phenomenon.

[0009] Another object to be achieved by the present disclosure is to provide a display device with high brightness.

[0010] The objects of the present disclosure are not limited to the above objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0011] According to one aspect of the present disclosure, a display device is provided, comprising: a substrate; a light emitting diode disposed on the substrate; a plurality of patterns disposed on the light emitting diode and having a ring shape; and a cover layer located on the plurality of patterns, wherein the light emitting diode is a micro light emitting diode (micro LED).

[0012] According to another aspect of the present disclosure, a display device is provided. The display device includes: a substrate; a plurality of transistors disposed on the substrate; a plurality of light-emitting diodes connected to and disposed on the plurality of transistors; a protective layer disposed on the plurality of light-emitting diodes; and a plurality of patterns disposed on the protective layer to correspond to the plurality of light-emitting diodes, wherein the plurality of light-emitting diodes are micro light-emitting diodes.

[0013] Additional details of example implementations are included in the detailed description and the accompanying drawings.

[0014] According to the present disclosure, a plurality of patterns are provided on a light emitting diode to improve light extraction efficiency.

[0015] According to the present disclosure, the shapes of a plurality of patterns are changed according to the brightness distribution of the light emitting diodes to minimize the brightness deviation according to the viewing angle.

[0016] According to the present disclosure, the shapes of a plurality of patterns are adjusted to improve the front brightness.

[0017] The effects according to the present disclosure are not limited to the above exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 2 is a cross-sectional view of a pixel region of a display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 3 is a plan view of a plurality of patterns of a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 4A and Figure 4B is a graph for explaining the effect of the display device according to the exemplary embodiment of the present disclosure;

[0023] Figure 5A , Figure 5B and Figure 5Cis a graph for explaining the effect of the display device according to the exemplary embodiment of the present disclosure;

[0024] Figure 6 is a cross-sectional view of a pixel region of a display device according to another exemplary embodiment of the present disclosure;

[0025] Figure 7 is a cross-sectional view of a pixel region of a display device according to still another exemplary embodiment of the present disclosure;

[0026] Figure 8 is a cross-sectional view of a pixel region of a display device according to still another exemplary embodiment of the present disclosure;

[0027] Fig. 9 is a plan view of a plurality of patterns of a display device according to still another exemplary embodiment of the present disclosure;

[0028] Fig. 10A and Fig. 10B is a schematic plan view of a display device according to yet another exemplary embodiment of the present disclosure;

[0029] Fig.11A and Fig. 11B is a graph for explaining an effect of a display device according to still another exemplary embodiment of the present disclosure; and

[0030] Fig.12 is a cross-sectional view of a pixel region of a display device according to still another exemplary embodiment of the present disclosure.

[0031] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The relative sizes and depictions of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0032] By referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will be clarified. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0033] The shapes, sizes, areas, ratios, angles, quantities, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. Throughout the specification, similar reference numerals generally represent similar elements. In addition, in the following description of the present disclosure, a detailed explanation of known related art may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "comprising", "having", "including", "containing", "constituting", "made of", "formed of", "composed of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". Unless otherwise expressly stated, the singular may also include the plural.

[0034] Even if not explicitly stated, the components are interpreted as including ordinary margins of error.

[0035] When terms such as "on," "over," "above," "below," "below," "beside," "below," "near," "near," "adjacent," "on the side of," and "close" are used to describe the positional relationship between two components, unless these terms are used with the terms "immediately" or "directly," one or more components may be located between the two components.

[0036] Spatially relative terms, such as "below," "below," "under," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatially relative terms may also include different orientations of elements in use or operation. For example, if the elements in the figures are inverted, elements described as being "below" or "below" other elements or features will be oriented as being "above" other elements or features. Therefore, the exemplary term "below" may include orientations below and above. Similarly, the exemplary terms "above" or "above" may include orientations "above" and "below."

[0037] When describing a temporal relationship, terms such as "after", "subsequently", "next", "following", "before", etc. may include any situation where two events are not consecutive, unless terms such as "immediately", "directly" or "directly" are explicitly used.

[0038] When an element or layer is “on” another element or layer, the other layer or element may be directly on the other element or layer or interposed therebetween.

[0039] Although the terms "first", "second", "A", "B", "a", and "b" etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below may be the second component in the technical concept of the present disclosure.

[0040] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used herein. Each of these terms is not used to limit the nature, order or sequence of the corresponding component, but is only used to distinguish the corresponding component from other parts. In the case of describing that a certain structural element or layer is "connected", "coupled", "bonded" or "joined" to another structural element or layer, it is generally interpreted that the other structural element or layer can be directly or indirectly "connected", "coupled", "bonded" or "joined" to the structural element or layer.

[0041] The term "at least one" should be understood to include any and all combinations of one or more associated listed items. For example, the meaning of "at least one of the first, second, and third items" means the combination of all items proposed from two or more of the first, second, and third items as well as the first, second, or third item.

[0042] The term "device" used herein may refer to a display device including a display panel and a driver for driving the display panel. Examples of display devices may include light emitting diodes (ED / LED), etc. In addition, examples of devices may include laptop computers, televisions, computer monitors, automotive devices, wearable devices, and automotive equipment devices, as well as complete electronic devices (or devices) or complete sets of devices (or devices) including ED / LED, etc. as complete products or final products, for example, mobile electronic devices such as smart phones or electronic tablets, but embodiments of the present disclosure are not limited thereto.

[0043] Throughout the specification, like reference numerals generally refer to like elements.

[0044] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the illustrated components.

[0045] The features of the various embodiments of the present disclosure may be partially or completely attached or combined with each other and may be technically interlocked and operated in various ways, and these embodiments may be implemented independently or in association with each other.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this article.

[0047] In aspects of the present disclosure, for ease of description, source electrodes and drain electrodes are distinguished from each other. However, source electrodes and drain electrodes may be used interchangeably. A source electrode may be a drain electrode, and a drain electrode may be a source electrode. In addition, a source electrode in any aspect of the present disclosure may be a drain electrode in another aspect of the present disclosure, and a drain electrode in any aspect of the present disclosure may be a source electrode in another aspect of the present disclosure.

[0048] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0049] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 2 is a cross-sectional view of a pixel region of a display device according to an exemplary embodiment of the present disclosure. Figure 3 is a plan view of a plurality of patterns of a display device according to an exemplary embodiment of the present disclosure.

[0050] exist Figure 1 In the embodiment, for the convenience of description, among the various components of the display device 100, only the display panel PN, the gate driver GD, the data driver DD and the timing controller TC are shown, but the components of the display device 100 of the present disclosure are not limited thereto. In addition, all components of each display device according to all embodiments of the present disclosure are operably connected and configured.

[0051] Reference Figure 1 , the display device 100 includes: a display panel PN including a plurality of sub-pixels SP; a gate driver GD and a data driver DD which supply various signals to the display panel PN; and a timing controller TC which controls the gate driver GD and the data driver DD.

[0052] The gate driver GD supplies a plurality of scan signals to the plurality of scan lines SL according to a plurality of gate control signals supplied from the timing controller TC. Figure 1, one gate driver GD is shown to be arranged to be spaced apart from one side of the display panel PN, but the number and arrangement of the gate drivers GD are not limited thereto. For example, two gate drivers GD may be respectively arranged on both sides of the display panel PN and spaced apart from the display panel PN. Alternatively, the gate driver GD may be mounted on the display panel PN. Thus, the structure in which the gate driver GD is directly mounted on the display panel PN is referred to as a gate-in-panel (GIP) structure, but is not limited thereto.

[0053] The data driver DD converts the image data input from the timing controller TC into a data voltage using a reference gamma voltage according to a plurality of data control signals supplied from the timing controller TC. The data driver DD may supply the converted data voltage to a plurality of data lines DL. The data driver DD may be configured with at least one data IC. In this case, as an example, the data IC of the data driver DD may be connected to the non-display area NA on the corresponding side of the display panel PN, or may be directly mounted on the non-display area NA. As an example, the data IC of the data driver DD may be mounted on a flexible circuit film and connected to the non-display area NA on the corresponding side of the display panel PN.

[0054] The timing controller TC aligns the image data input from the outside to supply the image data to the data driver DD. The timing controller TC can generate a gate control signal and a data control signal using a synchronization signal (e.g., a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal) input from the outside. Here, the horizontal synchronization signal is a signal indicating the time taken for one horizontal line of the display screen, and the vertical synchronization signal is a signal indicating the time taken for one frame of the display screen. The data enable signal may correspond to a signal indicating a period of supplying a data voltage to the pixel PX. The timing controller TC supplies the generated gate control signal and data control signal to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0055] The display panel PN is a configuration for displaying an image to a user, and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL intersect each other, and a plurality of sub-pixels SP are connected to the scan lines SL and the data lines DL, respectively. In addition, even though not shown in the figure, each of the plurality of sub-pixels SP is connected to a high potential power line, a low potential power line, and a reference line.

[0056] In the display panel PN, a display area AA and a non-display area NA disposed near, surrounding, or around the display area AA may be defined.

[0057] Display area AA is an area where an image is displayed in the display device 100. In display area AA, multiple pixel areas can be arranged in a matrix form along multiple row lines and column lines. Multiple pixel areas may include pixel areas that display different colors (e.g., red (R), green (G) and blue (B) or red (R), green (G), blue (B) and white). At this time, adjacent red (R), green (G) and blue (B) pixel areas or adjacent red (R), green (G), blue (B) and white pixel areas can be used as unit pixels for displaying color images.

[0058] In the display area AA, a plurality of sub-pixels SP constituting a plurality of pixels and a circuit for driving the plurality of sub-pixels SP may be provided. The plurality of sub-pixels SP are the minimum units constituting the display area AA, and n sub-pixels SP form one pixel. Each of the plurality of sub-pixels SP may emit light having a wavelength different from each other. The plurality of sub-pixels may include a first sub-pixel, a second sub-pixel, and a third sub-pixel emitting light of different colors from each other. For example, the plurality of sub-pixels SP may include a red sub-pixel SPR as a first sub-pixel, a green sub-pixel SPG as a second sub-pixel, and a blue sub-pixel SPB as a third sub-pixel. In addition, the plurality of sub-pixels SP may further include a white sub-pixel.

[0059] For example, a plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, wherein the red sub-pixel, the green sub-pixel, and the blue sub-pixel may be arranged in a repeated manner. Alternatively, a plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, wherein the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a repeated manner, or the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a quadrilateral type. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel may be arranged sequentially along the row direction, or the red sub-pixel, the blue sub-pixel, the green sub-pixel, and the white sub-pixel may be arranged sequentially along the row direction. However, in an embodiment of the present disclosure, the color type, arrangement type, and arrangement order of the sub-pixel are not limited, and may be configured in various forms according to the luminous characteristics, device life, and device specifications.

[0060] In addition, the sub-pixels may have different light-emitting areas according to the light-emitting characteristics. For example, a sub-pixel emitting light of a color different from the color of the blue sub-pixel may have a light-emitting area different from the light-emitting area of ​​the blue sub-pixel. For example, a red sub-pixel, a blue sub-pixel, and a green sub-pixel, or a red sub-pixel, a blue sub-pixel, a white sub-pixel, and a green sub-pixel may each have a different light-emitting area.

[0061] In each of the plurality of sub-pixels SP, a light emitting diode and a thin film transistor for driving the light emitting diode may be provided. Depending on the type of the display panel PN, the plurality of light emitting diodes may be defined in different ways. For example, when the display panel PN is an inorganic light emitting display panel, the light emitting diode may be a light emitting diode (LED) or a micro light emitting diode (micro LED), and when the display panel PN is an organic light emitting display panel, the light emitting element may be an organic light emitting diode (OLED), and the embodiments of the present disclosure are not limited thereto.

[0062] In the display area AA, a plurality of wirings for transmitting various signals to the plurality of sub-pixels SP are provided. For example, the plurality of wirings include a plurality of data lines DL for supplying a data voltage to each of the plurality of sub-pixels SP and a plurality of scan lines SL for supplying a scan signal to each of the plurality of sub-pixels SP. The plurality of scan lines SL extend in one direction in the display area AA to be connected to the plurality of sub-pixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the display area AA to be connected to the plurality of sub-pixels SP. In addition, in the display area AA, a low potential power line and a high potential power line may also be provided, but are not limited thereto.

[0063] The non-display area NA is an area where no image is displayed, so the non-display area NA may be defined as an area extending from the display area AA. In the non-display area NA, a link line, a pad electrode, or a driver IC such as a gate driver IC or a data driver IC that transmits a signal to the sub-pixel SP of the display area AA may be disposed.

[0064] In addition, drivers such as a gate driver GD, a data driver DD, and a timing controller TC may be connected to the display panel PN in various ways. For example, the gate driver GD may be installed in the non-display area NA in a gate-in-panel (GIP) manner, or may be installed between a plurality of sub-pixels SP in the display area AA in a gate-in-display area (GIA) manner. For example, the data driver DD and the timing controller TC are formed in a separate flexible film and a printed circuit board PCB, but are not limited thereto. The data driver DD and the timing controller TC are electrically connected to the display panel PN by bonding the flexible film and the printed circuit board PCB to pad electrodes formed in the non-display area NA of the display panel PN. For example, the data driver DD and the timing controller TC may be connected to the non-display area NA using a tape automated bonding (TAB) method, a chip on glass (COG) method, a chip on panel (COP) method, or a chip on film (COF) method.

[0065] First, refer to Figure 2, the display panel PN includes a substrate 110. The substrate 110 is a substrate that supports components disposed above the display device 100, and may be an insulating substrate. A plurality of pixels are formed on the substrate 110 to display an image. For example, the substrate 110 may be formed by including glass or resin. In addition, the substrate 110 may include a polymer or plastic. In some exemplary embodiments, the substrate 110 may be formed of a plastic material having flexibility. In some exemplary embodiments, the substrate 110 may be made of a flexible polymer film. For example, the flexible polymer film may be made of any one of polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyether sulfone (PES), polyarylate (PAR), polysulfone (PSF), cyclic olefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA) and polystyrene (PS), and the present disclosure is not limited thereto.

[0066] A plurality of sub-pixels SP may be formed on the substrate 110 to form a plurality of rows and columns. Each of the plurality of sub-pixels SP includes a light emitting diode ED and a pixel circuit that independently emits light.

[0067] A plurality of wirings for supplying various signals to a plurality of sub-pixels SP are provided on the substrate 110. For example, a plurality of data lines DL extending in the column direction, a plurality of high potential power lines VL1, and a plurality of low potential power lines may be provided on the substrate 110. For example, a plurality of light emitting control signal lines extending in the row direction, a plurality of auxiliary high potential power lines, a plurality of auxiliary low potential power lines, and a plurality of scanning lines may be provided on the substrate 110. The high potential power line VL1 extending in the column direction may be electrically connected to the auxiliary high potential power line extending in the row direction through a contact hole. At this time, the light emitting control signal line transmits the light emitting control signal to the pixel circuits of the plurality of sub-pixels SP to control the light emitting timing of the plurality of sub-pixels SP. However, the above-mentioned types of the plurality of wirings are exemplary, but the types of the plurality of wirings actually used may be changed to various types according to the design.

[0068] A pixel circuit for driving the light emitting diode ED is provided in each of the plurality of sub-pixels SP on the substrate 110. The pixel circuit may include a plurality of thin film transistors and a plurality of capacitors. Figure 2In the figure, for the convenience of description, only the driving transistor DT, the first capacitor C1 and the second capacitor C2 in the configuration of the pixel circuit are shown. However, the pixel circuit may also include a switching transistor, a sensing transistor, a light emitting control transistor, etc., but is not limited thereto. In the pixel circuit of the present disclosure, various configurations of the internal compensation circuit are possible. For example, the number of transistors TFT in the pixel circuit of the present disclosure may be three or more, and the number of capacitors may be 1 or more. For example, the pixel circuit of the present disclosure may be a 3T2C pixel circuit including three TFTs and two capacitors, a 5T1C pixel circuit including five TFTs and one capacitor, a 5T2C pixel circuit including five TFTs and two capacitors, or a 7T2C pixel circuit including seven TFTs and two capacitors, etc.

[0069] A light shielding layer BSM, a driving transistor DT, a first capacitor C1, a second capacitor C2, a reflective plate RF, a plurality of light emitting diodes ED, a first connection electrode CE1, a second connection electrode CE2, a bank BB, a protective layer 117, a plurality of patterns 119, a cover layer 160, an optical film MF, and an insulating layer may be disposed on the substrate 110. The insulating layer may include one or more inorganic insulating layers and / or one or more organic insulating layers, but is not limited thereto.

[0070] Among the insulating layers disposed on the substrate 110 , the plurality of inorganic insulating layers include a buffer layer 111 , a gate insulating layer 112 , a first interlayer insulating layer 113 , a second interlayer insulating layer 114 , a first passivation layer 115 a , and a second passivation layer 115 b .

[0071] In addition, among the insulating layers disposed on the substrate 110 , the plurality of organic insulating layers may include a first planarization layer 116 a , an adhesive layer AD, a second planarization layer 116 b , and a third planarization layer 116 c .

[0072] Reference Figure 2 , a light shielding layer BSM is provided on the substrate 110. The light shielding layer BSM blocks light incident on the active layer ACT of the plurality of transistors to minimize leakage current. For example, the light shielding layer BSM is provided under the active layer ACT of the driving transistor DT to block light incident on the active layer ACT. If light is irradiated onto the active layer ACT, leakage current is generated, thereby reducing the reliability of the transistor. Therefore, a light shielding layer BSM that blocks light is provided on the substrate 110 to improve the reliability of the driving transistor DT. The light shielding layer BSM may be composed of an opaque conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0073] The buffer layer 111 is disposed on the light shielding layer BSM. The buffer layer 111 is an inorganic insulating layer that reduces moisture or impurities from penetrating the substrate 110. For example, the buffer layer 111 may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. For example, the buffer layer 111 may be formed by a single layer or a multilayer inorganic film, for example, the single layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multilayer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. However, depending on the type of substrate 110 or the type of thin film transistor, the buffer layer 111 may be omitted, but is not limited thereto.

[0074] A driving transistor DT including an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE is disposed on the buffer layer 111 .

[0075] Even in Figure 2 Although not shown in the figure, an additional buffer layer may also be provided between the substrate 110 and the light shielding layer BSM. Similar to the above-mentioned buffer layer 111, the additional buffer layer is an inorganic insulating layer that reduces the penetration of moisture or impurities through the substrate 110, and may be composed of, for example, a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. For example, the additional buffer layer may be formed by a single layer or a multilayer of an inorganic film, for example, the single layer of the inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multilayer of the inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0076] First, the active layer ACT of the driving transistor DT is disposed on the buffer layer 111. The active layer ACT may be formed of a semiconductor material such as an oxide semiconductor, an amorphous semiconductor, or a polycrystalline semiconductor, but is not limited thereto.

[0077] Oxide semiconductor materials can have excellent effects of preventing leakage current and relatively cheap manufacturing costs. Oxide semiconductors can be made of metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) and titanium (Ti) or metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) or titanium (Ti) and combinations of their oxides. Specifically, oxide semiconductors can include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO) and indium gallium oxide (IGO), but are not limited thereto.

[0078] The polycrystalline semiconductor material has a fast moving speed of carriers such as electrons and holes, and thus has high mobility, and has low power consumption and excellent reliability. The polycrystalline semiconductor may be made of polycrystalline silicon (poly-Si), but is not limited thereto.

[0079] The amorphous semiconductor material may be made of amorphous silicon (a-Si), but is not limited thereto.

[0080] In addition, even if not shown in the figure, other transistors such as a switch transistor, a sensing transistor, and a light emission control transistor may be provided in addition to the driving transistor DT. The active layers of these transistors are also formed of semiconductor materials such as oxide semiconductors, amorphous silicon, or polycrystalline silicon, but are not limited thereto. The active layers of transistors such as the driving transistor DT, the switching transistor, the sensing transistor, and the light emission control transistor included in the pixel circuit may be formed of the same material, or may be formed of different materials.

[0081] The gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an inorganic insulating layer that electrically insulates the active layer ACT from the gate electrode GE, and may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. For example, the gate insulating layer 112 may be formed by a single layer or a multilayer inorganic film, for example, the single layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multilayer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0082] The gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0083] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the gate electrode GE. In the first interlayer insulating layer 113 and the second interlayer insulating layer 114, contact holes through which the source electrode SE and the drain electrode DE are connected to the active layer ACT are formed. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are inorganic insulating layers that protect the components thereunder, and may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto. For example, each of the first interlayer insulating layer 113 and the second interlayer insulating layer 114 may be formed by a single layer or a multilayer inorganic film, for example, a single layer of inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and a multilayer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0084] A source electrode SE and a drain electrode DE electrically connected to the active layer ACT are disposed on the second interlayer insulating layer 114. The source electrode SE is connected to the second capacitor C2 and the first electrode 134 of the light emitting diode ED, and the drain electrode DE is connected to another configuration of the pixel circuit. The source electrode SE and the drain electrode DE may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0085] A plurality of high potential power lines VL1 are disposed on the second interlayer insulating layer 114. The plurality of high potential power lines VL1 may transmit a high potential power voltage to the light emitting diode ED of each of the plurality of sub-pixels SP. The plurality of high potential power lines VL1 may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0086] Next, the first capacitor C1 is disposed on the gate insulating layer 112. The first capacitor C1 includes a 1-1th capacitor electrode C1a and a 1-2th capacitor electrode C1b.

[0087] First, the 1-1st capacitor electrode C1a is provided on the gate insulating layer 112. The 1-1st capacitor electrode C1a is formed integrally with the gate electrode GE of the driving transistor DT.

[0088] The 1-2nd capacitor electrode C1b is disposed on the first interlayer insulating layer 113. The 1-2nd capacitor electrode C1b is disposed to overlap with the 1-1st capacitor electrode C1a with the first interlayer insulating layer 113 therebetween.

[0089] Therefore, the first capacitor C1 is connected to the gate electrode GE of the driving transistor DT to maintain the voltage of the gate electrode GE of the driving transistor DT for a predetermined period.

[0090] Next, the second capacitor C2 is disposed on the substrate 110. The second capacitor C2 includes a 2-1st capacitor electrode C2a, a 2-2nd capacitor electrode C2b, and a 2-3rd capacitor electrode C2c. The second capacitor C2 includes a 2-1st capacitor electrode C2a as a lower capacitor electrode, a 2-2nd capacitor electrode C2b as a middle capacitor electrode, and a 2-3rd capacitor electrode C2c as an upper capacitor electrode.

[0091] The 2-1st capacitor electrode C2a is provided on the substrate 110. The 2-1st capacitor electrode C2a is provided on the same layer as the light shielding layer BSM, and is formed of the same material as the light shielding layer BSM.

[0092] The 2-2nd capacitor electrode C2b is provided on the buffer layer 111 and the gate insulating layer 112. The 2-2nd capacitor electrode C2b is provided on the same layer as the gate electrode GE and is formed of the same material as the gate electrode GE.

[0093] The 2-3rd capacitor electrode C2c is disposed on the first interlayer insulating layer 113. The 2-3rd capacitor electrode C2c is composed of a first layer C2c1 and a second layer C2c2. The first layer C2c1 of the 2-3rd capacitor electrode C2c is formed on the same layer as the 1-2nd capacitor electrode C1b using the same material as the 1-2nd capacitor electrode C1b. The first layer C2c1 is disposed to overlap the 2-1st capacitor electrode C2a and the 2-2nd capacitor electrode C2b with the first interlayer insulating layer 113 therebetween.

[0094] The second layer C2c2 of the 2-3rd capacitor electrode C2c is disposed on the second interlayer insulating layer 114. The second layer C2c2 is a portion extending from the source electrode SE of the driving transistor DT and is connected to the first layer C2c1 through a contact hole of the second interlayer insulating layer 114.

[0095] Therefore, the second capacitor C2 is electrically connected between the source electrode SE of the driving transistor DT and the light emitting diode ED to increase the inherent capacitance of the light emitting diode ED and allow the light emitting diode ED to emit light with higher brightness.

[0096] The first passivation layer 115a is disposed on the driving transistor DT, the first capacitor C1, and the second capacitor C2. The first passivation layer 115a is an inorganic insulating layer that protects the components below the first passivation layer 115a, and may be composed of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. For example, the first passivation layer 115a may be formed by a single-layer or multi-layer inorganic film, for example, the single-layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multi-layer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0097] The first planarization layer 116a is disposed on the first passivation layer 115a. The first planarization layer 116a may planarize an upper portion of the pixel circuit including the driving transistor DT. The first planarization layer 116a may be composed of a single layer or a double layer, and is composed of, for example, a benzocyclobutene or acrylic organic insulating layer.

[0098] Reference Figure 2 , a plurality of reflective plates RF are disposed on the first planarization layer 116a. The reflective plate RF has a configuration for reflecting light emitted from a plurality of light emitting diodes ED above the substrate 110, and is formed in a shape corresponding to each of a plurality of sub-pixels SP. One reflective plate RF is arranged to cover most of the area of ​​one sub-pixel SP. The reflective plate RF reflects the light emitted from the light emitting diode ED, and also serves as an electrode for electrically connecting the light emitting diode ED and the pixel circuit. Therefore, in consideration of light reflection efficiency and resistance, the reflective plate RF may include various conductive layers. For example, the reflective plate RF may use an opaque conductive layer such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti) or an alloy thereof, or a transparent conductive layer such as indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the reflective plate RF may use an opaque conductive layer such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti) or an alloy thereof and a transparent conductive layer such as indium tin oxide (ITO) or indium zinc oxide (IZO) together, but the structure of the reflective plate RF is not limited thereto.

[0099] The reflection plate RF includes a plurality of first reflection plates RFa and a plurality of second reflection plates RFb disposed in each of the plurality of sub-pixels SP.

[0100] The plurality of first reflective plates RFa reflect light emitted from the light emitting diodes ED to the outside of the display device 100. The plurality of first reflective plates RFa are disposed in the driving transistor DT in each of the plurality of subpixels SP to be electrically connected to the source electrode SE of the driving transistor DT and the second capacitor C2 through the first contact hole CH1.

[0101] A plurality of second reflection plates RFb may be disposed to overlap the light emitting diode ED. A plurality of second reflection plates RFb are disposed in the driving transistor DT in each of the plurality of sub-pixels SP to be electrically connected to the high potential power line VL1 through the second contact hole CH2. Therefore, the plurality of second reflection plates RFb reflect light emitted from the light emitting diode ED to the outside of the display device 100 while supplying a high potential power voltage to the light emitting diode ED.

[0102] Furthermore, the plurality of light emitting diodes ED may all be individually connected to the high potential power line VL1 without being connected to the reflection plate RF, but is not limited thereto.

[0103] Reference Figure 2 , the second passivation layer 115b is disposed on the plurality of reflective plates RF. The second passivation layer 115b is an inorganic insulating layer that protects the components below the second passivation layer 115b, and may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. For example, the second passivation layer 115b may be formed by a single layer or a multilayer inorganic film, for example, the single layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multilayer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0104] The adhesive layer AD is disposed on the second passivation layer 115b. The adhesive layer AD is formed on the front surface of the substrate 110 to fix the light emitting diode ED disposed on the adhesive layer AD. The adhesive layer AD is formed of an organic insulating layer. The adhesive layer AD may be formed of a photocurable adhesive material cured by light. For example, the adhesive layer AD may be formed of an acrylic material including a photoresist, but is not limited thereto.

[0105] A plurality of light emitting diodes ED are disposed in each of the plurality of sub-pixels SP on the adhesive layer AD. The light emitting diode ED is an element that emits light by current, and includes a first light emitting diode that emits red light, a second light emitting diode that emits green light, and a third light emitting diode that emits blue light, and various color lights including white light are realized by a combination thereof. For example, the light emitting diode ED may be a light emitting diode (LED) or a micro LED, but is not limited thereto.

[0106] The plurality of light emitting diodes ED include a first semiconductor layer 131 , an active layer 132 , a second semiconductor layer 133 , a first electrode 134 , and a second electrode 135 .

[0107] The plurality of light emitting diodes ED may be formed in various structures such as a lateral structure, a vertical structure, or a flip chip structure. The lateral light emitting diode includes a first electrode and a second electrode horizontally disposed on both sides of an active layer. The vertical light emitting diode includes a first electrode and a second electrode disposed above and below the active layer, respectively. The flip chip light emitting diode has a structure substantially the same as that of the lateral light emitting diode. However, in the lateral light emitting diode, the first electrode and the second electrode are horizontally disposed above the active layer, but in the flip chip light emitting diode, the first electrode and the second electrode are horizontally disposed below the active layer. In the following, it is assumed that the plurality of light emitting diodes ED have a lateral structure, but the type of the plurality of light emitting diodes ED is not limited thereto.

[0108] The first semiconductor layer 131 is disposed on the adhesive layer AD, and the second semiconductor layer 133 is disposed on the first semiconductor layer 131. The first semiconductor layer 131 and the second semiconductor layer 133 may be layers formed by doping n-type and p-type impurities into a specific material. For example, the first semiconductor layer 131 and the second semiconductor layer 133 may be layers doped with n-type and p-type impurities in a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurity may be magnesium (Mg), zinc (Zn), and beryllium (Be), and the n-type impurity may be silicon (Si), germanium (Ge), and tin (Sn), but is not limited thereto.

[0109] The active layer 132 is disposed between the first semiconductor layer 131 and the second semiconductor layer 133. Holes and electrons are supplied to the active layer 132 from the first semiconductor layer 131 and the second semiconductor layer 133 to emit light. The active layer 132 may be formed of a single layer or a multi-quantum well (MQW) structure, and may be formed of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0110] In addition, a portion of the first semiconductor layer 131 protrudes outward from the second semiconductor layer 133 and the active layer 132 to be exposed from the second semiconductor layer 133 and the active layer 132 .

[0111] The first semiconductor layer 131 is configured to surround the active layer 132 and the second semiconductor layer 133 on a plane. That is, all of the active layer 132 and the second semiconductor layer 133 may be disposed to overlap with the first semiconductor layer 131, and only a portion of the inner portion of the first semiconductor layer 131 overlaps with the active layer 132 and the second semiconductor layer 133.

[0112] At this time, the second semiconductor layer 133 and the active layer 132 protruding from the first semiconductor layer 131 are called a mesa portion. The side surfaces of the mesa portion (ie, the side surfaces of the second semiconductor layer 133 and the active layer 132) are arranged to be inclined relative to the bottom surface of the first semiconductor layer 131.

[0113] The first electrode 134 is disposed on the first semiconductor layer 131. The first electrode 134 is an electrode electrically connecting the driving transistor DT and the first semiconductor layer 131. In this case, the first semiconductor layer 131 is a semiconductor layer doped with n-type impurities, and the first electrode 134 may be a cathode. The first electrode 134 may be disposed on the top surface of the first semiconductor layer 131 exposed from the active layer 132 and the second semiconductor layer 133. The first electrode 134 may be composed of, for example, a conductive material (for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof), but is not limited thereto.

[0114] The second electrode 135 is disposed on the second semiconductor layer 133. The second electrode 135 is disposed on the top surface of the second semiconductor layer 133. The second electrode 135 is an electrode electrically connecting the high potential power line VL1 and the second semiconductor layer 133. In this case, the second semiconductor layer 133 is a semiconductor layer doped with p-type impurities, and the second electrode 135 may be an anode. The second electrode 135 may be composed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof, but is not limited thereto.

[0115] Next, an encapsulation layer 136 is provided to surround the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the first electrode 134, and the second electrode 135. The encapsulation layer 136 is formed of an insulating material to protect the first semiconductor layer 131, the active layer 132, and the second semiconductor layer 133. In the encapsulation layer 136, contact holes exposing the first electrode 134 and the second electrode 135 are formed to electrically connect the first connection electrode CE1 and the second connection electrode CE2 to the first electrode 134 and the second electrode 135, respectively.

[0116] In addition, a portion of the side surface of the first semiconductor layer 131 may be exposed from the encapsulation layer 136. The light emitting diode ED manufactured on the wafer is separated from the wafer to be transferred to the display panel PN. However, during the process of separating the light emitting diode ED from the wafer, a portion of the encapsulation layer 136 may be torn. For example, during the process of separating the light emitting diode ED from the wafer, a portion of the encapsulation layer 136 adjacent to the lower edge of the first semiconductor layer 131 of the light emitting diode ED is torn. Therefore, a portion of the lower side surface of the first semiconductor layer 131 may be exposed to the outside. However, even if the lower portion of the light emitting diode ED is exposed from the encapsulation layer 136, the first connection electrode CE1 and the second connection electrode CE2 are formed after forming the second planarization layer 116b and the third planarization layer 116c covering the side surface of the first semiconductor layer 131. Therefore, short circuit defects can be reduced.

[0117] Next, a second planarization layer 116 b and a third planarization layer 116 c are disposed on the adhesive layer AD and the light emitting diode ED.

[0118] The second planarization layer 116b overlaps a portion of the side surface of the plurality of light emitting diodes ED to fix and protect the plurality of light emitting diodes ED. The second planarization layer 116b may be composed of a single layer or a double layer, and may be composed of, for example, a benzocyclobutene or acrylic organic insulating layer. The second planarization layer 116b may be formed using a halftone mask. Thus, the second planarization layer 116b is formed to have a step.

[0119] Specifically, a portion of the second planarization layer 116b that is relatively adjacent to the light emitting diode ED is formed to have a smaller thickness, and a portion that is away from the light emitting diode ED is formed to have a larger thickness. For example, the thickness of the portion of the second planarization layer 116b that is adjacent to the light emitting diode ED is smaller than the thickness of the portion of the second planarization layer 116b that is away from the light emitting diode ED. The portion of the second planarization layer 116b that is adjacent to the light emitting diode ED is arranged to surround the light emitting diode ED and also to contact the side surface of the light emitting diode ED. Therefore, during the process of separating the light emitting diode ED from the wafer to transfer to the display panel PN, the torn portion of the encapsulation layer 136 that protects the side surface of the first semiconductor layer 131 of the light emitting diode ED is covered by the second planarization layer 116b. In this way, the contact and short circuit defects of the first connection electrode CE1 and the second connection electrode CE2 with the first semiconductor layer 131 can be suppressed thereafter.

[0120] The third planarization layer 116c is formed to cover the light emitting diode ED and the upper portion of the second planarization layer 116b, and a contact hole exposing the first electrode 134 and the second electrode 135 of the light emitting diode ED may be formed. The first electrode 134 and the second electrode 135 of the light emitting diode ED are exposed from the third planarization layer 116c, and the third planarization layer 116c is partially disposed in a region between the first electrode 134 and the second electrode 135 to reduce a short circuit defect. The second planarization layer 116b and the third planarization layer 116c may be composed of a single layer or a double layer, and may be formed of, for example, a photoresist or an acrylic organic insulating material.

[0121] In addition, the third planarization layer 116c may cover the light emitting diode ED and the region adjacent to the light emitting diode ED. The third planarization layer 116c is disposed in the region of the sub-pixel SP surrounded by the bank BB and is disposed in an island shape. Therefore, the bank BB is disposed on a portion of the top surface of the second planarization layer 116b. For example, the bank BB is disposed on the third planarization layer 116c so as to overlap a portion of the third planarization layer 116c.

[0122] The first and second link electrodes CE1 and CE2 are disposed on the third planarization layer 116c.

[0123] The first connection electrode CE1 is an electrode that electrically connects the first electrode 134 of the light emitting diode ED and the driving transistor DT. The first connection electrode CE1 is electrically connected to the first electrode 134 exposed from the third planarization layer 116c, and is simultaneously electrically connected to the first reflective plate RFa through a contact hole formed in the third planarization layer 116c, the second planarization layer 116b, the adhesive layer AD, and the second passivation layer 115b. Therefore, the first electrode 134 is electrically connected to the source electrode SE of the driving transistor DT through the first connection electrode CE1 and the first reflective plate RFa.

[0124] The second connection electrode CE2 is an electrode that electrically connects the second electrode 135 of the light emitting diode ED and the high potential power line VL1. The second connection electrode CE2 is electrically connected to the second electrode 135 exposed from the third planarization layer 116c, and is electrically connected to the second reflection plate RFb through a contact hole formed in the third planarization layer 116c, the second planarization layer 116b, the adhesive layer AD, and the second passivation layer 115b. Therefore, the second electrode 135 and the high potential power line VL1 are electrically connected through the second connection electrode CE2 and the second reflection plate RFb.

[0125] The first and second connection electrodes CE1 and CE2 are formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but are not limited thereto.

[0126] Furthermore, the first electrode 134, the first connection electrode CE1 and the first reflective plate RFa are shown to be electrically connected to the source electrode SE of the driving transistor DT. However, the first electrode 134, the first connection electrode CE1 and the first reflective plate RFa may be connected to the drain electrode DE of the driving transistor DT, but are not limited thereto.

[0127] Reference Figure 2 , the bank BB is disposed on the second planarization layer 116b and the third planarization layer 116c exposed from the first connection electrode CE1 and the second connection electrode CE2. The bank BB is disposed to be separated from the light emitting diode ED by a predetermined interval and at least partially overlap the reflective plate RF. For example, the bank BB may cover a portion of the first connection electrode CE1 and the second connection electrode CE2 formed in the contact holes of the third planarization layer 116c and the second planarization layer 116b. In addition, the bank BB may be disposed on the second planarization layer 116b and have a predetermined interval with the light emitting diode ED.

[0128] The bank BB may be formed of an opaque material to reduce color mixing between the plurality of sub-pixels SP, and may be formed of, for example, a black resin, but is not limited thereto.

[0129] In addition, the thickness of a portion of the bank BB formed in the contact hole of the third planarization layer 116c and the second planarization layer 116b to cover a portion of the first connection electrode CE1 and the second connection electrode CE2 and the thickness of a portion of the bank BB disposed on the second planarization layer 116b may be different from each other. Specifically, when a portion of the bank BB covers a portion of the first connection electrode CE1 and the second connection electrode CE2 formed in the contact hole of the third planarization layer 116c and the second planarization layer 116b, since the contact hole is formed from the second passivation layer 115b to the third planarization layer 116c, the bank BB may be disposed below the light emitting diode ED (i.e., disposed lower than the light emitting diode ED). Therefore, the thickness of a portion of the bank BB covering a portion of the first connection electrode CE1 and the second connection electrode CE2 formed in the contact hole of the third planarization layer 116c and the second planarization layer 116b may be greater than the thickness of a portion of the bank BB disposed on the second planarization layer 116b.

[0130] However, the embodiment is not limited thereto, and the bank BB may be disposed at the outside of the contact holes of the third and second planarization layers 116 c and 116 b to cover a portion of the first and second connection electrodes CE1 and CE2 .

[0131] The protective layer 117 is disposed on the first connection electrode CE1, the second connection electrode CE2, and the bank BB. The protective layer 117 is a layer for protecting the configuration below the protective layer 117. The protective layer 117 may be composed of a single layer or a double layer, and is composed of, for example, benzocyclobutene, light-transmitting epoxy resin, photoresist, or acrylic organic material, but is not limited thereto.

[0132] A plurality of ring-shaped patterns 119 are disposed on the protective layer 117. The plurality of patterns 119 are disposed to correspond to the plurality of light emitting diodes ED.

[0133] At this time, refer to Figure 3 , the plurality of patterns 119 may have a concentric shape, and the spacing distances between the plurality of patterns 119 may be the same. At this time, the plurality of patterns 119 may not be arranged in the region corresponding to the central portion of the light emitting diode ED. For example, the innermost pattern among the plurality of patterns may be arranged to surround a circle having a diameter of 6 μm to 8 μm. For example, the innermost pattern among the plurality of patterns may be arranged to surround a circle having a diameter of 6.5 μm to 7.5 μm, but is not limited thereto.

[0134] In addition, the sum of the width of one pattern 119 among the plurality of patterns 119 and the spacing distance between the plurality of patterns may be equal to or less than 10 μm. For example, the sum of the width of one pattern 119 among the plurality of patterns 119 and the spacing distance between the plurality of patterns may be 5 μm to 9 μm, but is not limited thereto. At this time, considering the spacing distance between the plurality of patterns 119 and the width of the plurality of patterns 119, at least three patterns 119 may be provided on the light emitting diode ED, but is not limited thereto. In addition, the width of the top surface of each of the plurality of patterns 119 may be 2 μm to 4 μm. For example, the width of the top surface of one of the plurality of patterns 119 may be 3 μm. The widths of the top surfaces of the plurality of patterns 119 may be the same or different, and the spacing distance between two adjacent patterns among the plurality of patterns 119 may be the same or different from the width of the top surface of one of the plurality of patterns 119, but is not limited thereto.

[0135] The plurality of patterns 119 may be formed of a material having a lower refractive index than the capping layer 160. For example, the plurality of patterns 119 may be formed of a photoresist or an acrylic organic material, but is not limited thereto.

[0136] The plurality of patterns 119 are disposed to overlap with the plurality of light emitting diodes ED disposed thereunder.

[0137] At this time, the diameter of the outermost pattern 119 among the plurality of patterns 119 may be twice or more the diameter of the light emitting diode ED. Therefore, the plurality of patterns 119 may extract light propagating in the lateral direction of the light emitting diode ED along the front direction. For example, the brightness of the light emitting diode ED may be higher on the side surface 50 to 70 degrees from the front surface. At this time, when the size of the light emitting diode ED is 10 μm to 30 μm and the light emitting diode ED and the plurality of patterns 119 are spaced apart from each other at intervals of 3 μm to 6 μm, the plurality of patterns 119 are disposed in an area corresponding to twice the diameter of the light emitting diode ED. Therefore, the light propagating in the lateral direction of the light emitting diode ED may be covered.

[0138] The plurality of patterns 119 may include bottom surfaces and inclined side surfaces of the plurality of patterns 119. For example, the inclination angle formed by the side surfaces of the plurality of patterns 119 and the bottom surfaces of the plurality of patterns 119 may be 55 degrees or more, and the inclined side surfaces of the plurality of patterns 119 may change the path of light propagating in the lateral direction of the light emitting diodes ED.

[0139] The capping layer 160 is disposed over the plurality of patterns 119 and the protection layer 117 .

[0140] The cover layer 160 may be disposed to cover the plurality of patterns 119, and may be formed of a material having a higher refractive index than the plurality of patterns 119. For example, the cover layer 160 may be formed of a material including polyparaxylene, but is not limited thereto.

[0141] Reference Figure 2 , an optical film MF covering the upper part of the cover layer 160 is provided in the entire upper area of ​​the substrate 110. The optical film MF is provided on the sealing member and the protective layer 117. Although not shown, the sealing member may be provided to surround the side surface of the display device 100 to protect the display device 100 from external impact, moisture, oxygen, or the like. For example, the sealing member may be made of polyimide (PI), polyurethane, epoxy resin, or acrylic-based insulating material, but is not limited thereto. The optical film MF may be a functional film that achieves higher image quality while protecting the display device 100. For example, the optical film MF may include an anti-scattering film, an anti-glare film, an anti-reflection film, a low-reflection film, an OLED transmittance controllable film, or a polarizer, but is not limited thereto.

[0142] In addition, the edge of the sealing member and the edge of the optical film MF may be arranged in a colinear manner. During the manufacturing process of the display device 100, a larger-sized optical film MF may be attached to the substrate 110 (for example, the size of the optical film MF is larger than the size of the substrate 110), and a sealing member for covering the side surface of the display device 100 may be formed. Afterwards, portions of the sealing member and the optical film MF may be cut by irradiating a laser to the sealing member and the optical film MF to correspond to the edge of the display device 100. Therefore, the size of the display device 100 may be adjusted by the process of cutting the outer portion of the sealing member and the optical film MF, and the edge of the display device 100 may be formed flat.

[0143] In addition, an adhesive unit is provided between the protective layer 117 and the optical film MF above the substrate 110. The adhesive unit is formed on the front surface of the substrate 110 to be bonded between the protective layer 117 and the optical film MF. The adhesive unit may be formed of a photocurable adhesive material that is cured by light. For example, the adhesive unit may be formed of an acrylic material including a photoresist, but is not limited thereto.

[0144] Figure 4A and Figure 4B is a graph for explaining the effect of the display device according to an exemplary embodiment of the present disclosure. Figure 4A is a graph for explaining the brightness distribution of a display device according to a comparative example, and Figure 4B is a graph for explaining the luminance distribution of the display device 100 according to the example of the present disclosure. In the display device according to the comparative example, the plurality of patterns 119 and the cover layer 160 are not provided, which is different from the display device 100 according to the example of the present disclosure.

[0145] Figure 4A and Figure 4B The luminance distribution according to the viewing angles measured in the comparative example and the example is shown, and the luminance distribution according to the viewing angles when the inclination angle of the mesa unit is changed to 64°, 67°, 70°, 73°, 76°, 79°, and 82° in the comparative example and the example is shown. Figure 4A and Figure 4B In the graph of , the X-axis represents the viewing angle. Figure 4A and Figure 4B In the curve graph of , the Y-axis represents brightness, and the brightness in the front direction is set to 1.

[0146] Reference Figure 4A and Figure 4B In the comparative example and the example, the brightness is higher in the lateral direction of 50° to 70° than in the front direction, and is maximum at about 60°. Figure 4A In the comparative example, the maximum brightness is about 1.2 to 1.4. Figure 4B, in the example, the maximum brightness is about 1.0 to 1.2, so that it can be confirmed that the brightness deviation is reduced compared with the comparative example.

[0147] according to Figure 4A and Figure 4B The results of the curve diagram are summarized in Table 1 below.

[0148] [Table 1]

[0149] Front brightness Brightness deviation at viewing angle Brightness ratio of viewing angle Comparative Example 100％ 8％ 1.34 Example 113％ 5.1％ 1.12

[0150] The viewing angle brightness deviation refers to the deviation between the maximum brightness measured under each condition when the inclination angle of the table unit is 64°, 67°, 70°, 73°, 76°, 79° and 82°.

[0151] The front brightness is the brightness at a viewing angle of 0° when the inclination angle of the mesa unit is 67°, and is the brightness when the front brightness is 100% in the comparative example.

[0152] The viewing angle brightness ratio is the ratio of the maximum brightness measured in the lateral direction to the front brightness when the inclination angle of the mesa unit is 67°.

[0153] Reference Figure 4A and Figure 4B As shown in Table 1, when the front brightness in the comparative example is 100%, the front brightness in the example is about 113%. At this time, it can be confirmed that the front brightness in the example with multiple patterns 119 is increased by about 13% compared with the comparative example without multiple patterns 119.

[0154] In addition, refer to Figure 4A and Figure 4B As shown in Table 1, when the viewing angle luminance deviation in the comparative example is 8%, the viewing angle luminance deviation in the example is about 5.1%. That is, it can be confirmed that the viewing angle luminance deviation in the example in which the plurality of patterns 119 are set is reduced by about 2.9% compared with the comparative example in which the plurality of patterns 119 are not set.

[0155] In addition, refer to Figure 4A and Figure 4B As shown in Table 1, the viewing angle brightness ratio in the comparative example is 1.34, and the viewing angle brightness ratio in the example is 1.12. It can be confirmed that the viewing angle brightness ratio in the example where the plurality of patterns 119 are provided is reduced by about 0.22 compared to the comparative example where the plurality of patterns 119 are not provided.

[0156] Figure 5A , Figure 5B and Figure 5C is a graph for explaining the effect of the display device according to an exemplary embodiment of the present disclosure. Figure 5AIn the graph of , the X-axis represents the center hole size of the plurality of patterns 119, and it represents the inner diameter of the pattern 119 disposed at the center of the plurality of patterns 119. Figure 5B In the graph of , the X-axis represents the upper width of the plurality of patterns 119. Figure 5C In the graph of , the X-axis represents the inclination angle of the plurality of patterns 119. FIG. 5A to FIG. 5C In the curve graph, the Y-axis represents brightness.

[0157] exist FIG. 5A to FIG. 5C In the graph shown, the total light quantity, front brightness and brightness uniformity of the example when the center hole size of the plurality of patterns 119, the upper end width of the plurality of patterns 119 and the inclination angle of the plurality of patterns 119 are changed are shown. FIG. 5A to FIG. 5C In the figure, the total light amount indicates the total light amount of the example when the total light amount extracted in the comparative example is 1. The front brightness refers to the ratio of the front brightness of the example when the front brightness of the comparative example is 1. In addition, the brightness uniformity indicates the deviation between the front brightness and the maximum brightness in the lateral direction.

[0158] Reference Figure 5A , when the center hole size of the plurality of patterns 119 changes from 0 μm to 10 μm, the highest brightness of about 1.15 is obtained when the center hole size of the plurality of patterns 119 is 0 μm. In addition, when the center hole size of the plurality of patterns 119 is 6 μm, the highest total light quantity of about 1.05 is obtained, and when the center hole size of the plurality of patterns 119 is 8 μm, the brightness uniformity with the minimum deviation of about 1.45 is obtained.

[0159] Reference Figure 5B , when the upper width of the plurality of patterns 119 changes from 1 μm to 4 μm, the smaller the upper width of the plurality of patterns 119, the greater the front brightness and the total amount of light. When the upper width of the plurality of patterns 119 is 1 μm, the front brightness is about 1.17, and the total amount of light is about 1.05. When the center hole size of the plurality of patterns 119 is 3 μm, a brightness uniformity with a minimum deviation of about 1.47 is obtained.

[0160] Reference Figure 5C , when the inclination angle of the plurality of patterns 119 changes from 45 degrees to 75 degrees, the highest front brightness of about 1.25 is obtained at the inclination angle of the plurality of patterns 119 of 71 degrees. In addition, the highest total light amount of about 1.05 is obtained at the inclination angle of the plurality of patterns 119 of 65 degrees. However, when the inclination angle of the plurality of patterns 119 is 55 degrees or less, the brightness uniformity is higher than the brightness uniformity of about 1.5 of the comparative example. Therefore, it can be confirmed that the brightness deviation according to the viewing angle increases compared with the comparative example.

[0161] In the display device, brightness deviation occurs depending on the viewing angle according to the shape of the light-emitting diode and component tolerance. When a micro light-emitting diode (micro LED / micro LED) is used as a light-emitting diode, the lateral brightness (i.e., the brightness in the direction of 50 to 70 degrees) increases more than the front brightness, and the maximum brightness is obtained in the direction of about 60 degrees. Therefore, the brightness distribution curve according to the viewing angle can be shown as an M shape, which may cause a moire phenomenon.

[0162] Furthermore, in the case of a micro-LED, the brightness distribution according to the viewing angle may vary according to the inclination of a region called a mesa unit of the light-emitting diode (i.e., the side surfaces of the second semiconductor layer 133 and the active layer 132). In addition, since the light-emitting diode is manufactured to have a small size, the shape and inclination of the mesa unit may be affected even by a small tolerance. For example, when the light-emitting diode is manufactured to have a size of about 30 μm, even with a tolerance of the μm level, the inclination of the mesa portion may deviate. Therefore, it is difficult to control the viewing angle deviation according to the tolerance.

[0163] Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, a plurality of annular patterns 119 formed of a low refractive index material are disposed under the cover layer 160 formed of a high refractive index material to cover the light emitted laterally and thus extracted in the front direction. In addition, the plurality of concentric patterns 119 are disposed to correspond to the size of the light emitting diode ED to cover the brightness deviation of the light emitting diode ED caused by the transfer error. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the light propagating laterally is extracted in the front direction to reduce the viewing angle deviation and achieve high color reproducibility. In addition, the front brightness of the display device 100 is increased to provide a display device 100 having high brightness and high efficiency, and to improve the moire phenomenon.

[0164] Figure 6 is a cross-sectional view of a pixel region of a display device according to another exemplary embodiment of the present disclosure. Figure 6 The display device 600 and Figures 1 to 3 The only difference between the display devices 100 is the plurality of patterns 619, but the other configurations are substantially the same, so redundant description will be omitted.

[0165] Reference Figure 6, a plurality of annular patterns 619 are disposed on the protective layer 117. The plurality of patterns 619 may be recessed toward the substrate 110. For example, each pattern 619 has a minimum height at the center and a maximum height in the lateral direction. For example, the height of each pattern 619 at the periphery is greater than the height of each pattern 619 at the center. At this time, the top surface of each pattern 619 is disposed to have a predetermined inclination angle relative to the bottom surface of the pattern 619. For example, the top surface of each pattern 619 is disposed to have an inclination angle of 0° to 90° relative to the bottom surface of the pattern 619, for example, the top surface of each pattern 619 is disposed to have an inclination angle of 30° to 60° relative to the bottom surface of the pattern 619. For example, as Figure 6 As shown, the top surface of each pattern 619 may be formed by two planes symmetrically arranged relative to the center of the pattern 619 , but the present disclosure is not limited thereto, and the top surface of each pattern 619 may be formed by two planes asymmetrically arranged relative to the center of the pattern 619 .

[0166] The cover layer 660 is disposed over the plurality of patterns 619 and the protective layer 117 to cover the top and side surfaces of the plurality of patterns 619. Alternatively, a sealing member (not shown) may be disposed around the side surface of the display device 100 to protect the display device 100 from external impact, moisture, oxygen, or the like. For example, the sealing member may be made of polyimide (PI), polyurethane, epoxy resin, or acrylic-based insulating material, but is not limited thereto.

[0167] In a display device 600 according to another exemplary embodiment of the present disclosure, a plurality of annular patterns 619 formed of a low refractive index material are disposed under a cover layer 660 formed of a high refractive index material to extract light propagating laterally in a front direction. In addition, a display device 600 having high color reproducibility, high brightness, and high efficiency can be realized.

[0168] In the display device 600 according to another exemplary embodiment of the present disclosure, the top surfaces of the plurality of patterns 619 are recessed toward the substrate 110. For example, the top surfaces of the plurality of patterns 619 may be formed of a plane inclined relative to the bottom surfaces of the plurality of patterns 619. Therefore, light laterally incident on the top surfaces of the plurality of patterns 619 propagates in a front direction while passing through the inclined top surfaces of the plurality of patterns 619. Therefore, in the display device 600 according to another exemplary embodiment of the present disclosure, the front brightness is improved, so that the display device 600 having high brightness and high efficiency can be realized.

[0169] Figure 7 is a cross-sectional view of a pixel region of a display device according to still another exemplary embodiment of the present disclosure. Figure 7 The display device 700 and Figures 1 to 3The only difference between the display devices 100 is the plurality of patterns 719, but the other configurations are substantially the same, so redundant description will be omitted.

[0170] Reference Figure 7 , a plurality of annular patterns 719 are disposed on the protective layer 117. The plurality of patterns 719 may be recessed toward the substrate 110. Therefore, each pattern 719 has a minimum height at the center and a maximum height in the lateral direction. For example, the height of each pattern 719 at the periphery is greater than the height of each pattern 719 at the center. For example, the top surfaces of the plurality of patterns 719 are curved surfaces recessed toward the substrate 110. Therefore, the inclination angle formed by the top surface and the bottom surface of each pattern 719 may vary depending on the position, and for example, the inclination angle of the top surface of the pattern 719 may increase as it moves away from the center of each pattern 719.

[0171] The cover layer 760 is disposed over the plurality of patterns 719 and the protective layer 117 to cover the top and side surfaces of the plurality of patterns 719. Alternatively, a sealing member (not shown) may be disposed around the side surface of the display device 100 to protect the display device 100 from external impact, moisture, oxygen, or the like. For example, the sealing member may be made of polyimide (PI), polyurethane, epoxy resin, or acrylic-based insulating material, but is not limited thereto.

[0172] In a display device 700 according to another exemplary embodiment of the present disclosure, a plurality of annular patterns 719 formed of a low refractive index material are disposed under a cover layer 760 formed of a high refractive index material to extract light propagating laterally in a front direction. In addition, a display device 700 having high color reproducibility, high brightness, and high efficiency can be realized.

[0173] In a display device 700 according to another exemplary embodiment of the present disclosure, the top surfaces of the plurality of patterns 719 are recessed toward the substrate 110. For example, the top surfaces of the plurality of patterns 719 may be formed by a curved surface recessed toward the bottom surfaces of the plurality of patterns 719. Therefore, the inclination angle formed by the top and bottom surfaces of the plurality of patterns 719 may vary at each position. Therefore, the viewing angle brightness distribution of the display device 700 may be controlled according to the inclination angle formed by the top surfaces of the plurality of patterns 719. Therefore, in a display device 700 according to another exemplary embodiment of the present disclosure, the top surfaces of the plurality of patterns 719 are arranged to have a curved shape to adjust the viewing angle brightness distribution of the display device 700.

[0174] Figure 8 is a cross-sectional view of a pixel region of a display device according to still another exemplary embodiment of the present disclosure. Fig. 9 is a plan view of a plurality of patterns of a display device according to still another exemplary embodiment of the present disclosure. Fig. 9 yes Figure 8 A plan view of multiple patterns 819. Figure 8 The display device 800 and Figures 1 to 3 The only difference between the display devices 100 is the plurality of patterns 819, but the other configurations are substantially the same, so redundant description will be omitted.

[0175] Reference Figure 8 , a plurality of annular patterns 819 are disposed on the protection layer 117 .

[0176] The spacing distance between the plurality of patterns 819 disposed on one side from the center of the light emitting diode ED and the spacing distance between the plurality of patterns 819 disposed on the other side from the center of the light emitting diode ED may be different. Figure 8 As shown, the second electrode 135 of the light emitting diode ED is disposed on one side of the light emitting diode ED, and the first electrode 134 of the light emitting diode ED is disposed on the other side of the light emitting diode ED. At this time, the spacing distance between the plurality of patterns 819 disposed on one side from the center of the light emitting diode ED is smaller than the spacing distance between the plurality of patterns 819 disposed on the other side from the center of the light emitting diode ED.

[0177] Reference Fig. 9 , the first interval d1 is the interval distance between the plurality of patterns 819 disposed on one side of the center of the light emitting diode ED, and the second interval D2 is the interval distance between the plurality of patterns 819 disposed on the other side of the center of the light emitting diode ED. Therefore, the plurality of patterns 819 are asymmetrically disposed with respect to the center, and are asymmetrical with respect to the center of the light emitting diode ED.

[0178] In addition, the light emitting diode ED has different brightness distributions according to the viewing angle, and the plurality of patterns 819 are arranged to correspond to the brightness distribution of the light emitting diode ED. For example, the maximum brightness at one side of the light emitting diode ED is higher than the maximum brightness at the other side of the light emitting diode ED. The spacing distance between the plurality of patterns 819 arranged on one side of the light emitting diode ED may be smaller than the spacing distance between the plurality of patterns 819 arranged on the other side of the light emitting diode ED.

[0179] The cover layer 860 is disposed over the plurality of patterns 819 and the protective layer 117 to cover the top and side surfaces of the plurality of patterns 819. Alternatively, a sealing member (not shown) may be disposed around the side surface of the display device 100 to protect the display device 100 from external impact, moisture, oxygen, or the like. For example, the sealing member may be made of polyimide (PI), polyurethane, epoxy resin, or acrylic-based insulating material, but is not limited thereto.

[0180] In the following, we will refer to Figures 10A to 11BThe brightness distribution of the light emitting diode ED and the spacing distances between the plurality of patterns 819 are described.

[0181] Fig. 10A and Fig. 10B is a schematic plan view of a display device according to still another exemplary embodiment of the present disclosure. Fig. 10A and Fig. 10B yes Figure 8 A plan view of a display device 800 is provided, and Fig. 10A and Fig. 10B In the figure, for the convenience of illustration, only the reflector RF, the light emitting diode ED, the light emitting region A and the plurality of patterns 819 are shown, and the light emitting diode ED and the light emitting region A are schematically shown. Fig. 10A Multiple patterns 819 are omitted.

[0182] Reference Fig. 10A and Fig. 10B The reflection plate RF is disposed to overlap with the light emitting diode ED. The reflection plate RF may be disposed to have an area greater than an area of ​​a bottom surface of the light emitting diode ED.

[0183] In addition, the reflective plate may be arranged asymmetrically with respect to the center of the light emitting diode ED. For example, the center of the light emitting diode ED and the center of the reflective plate RF may be different, and as shown in FIG. Fig. 10A and Fig. 10B As shown, the light emitting diode ED may be arranged to be inclined toward one side of the reflector RF. In addition, the reflector RF has an opening area OPEN with a portion of the area removed. In this case, the opening area OPEN of the reflector RF may be asymmetric relative to the center of the light emitting diode ED. For example, Fig. 10A and Fig. 10B In the embodiment, the length of the reflector RF extending from the center of the light emitting diode ED to one side may be shorter than the length of the reflector RF extending from the center of the light emitting diode ED to the other side. Therefore, the area of ​​the opening region OPEN located at the lower side of the light emitting diode ED may be larger than the area of ​​the opening region OPEN located at the upper side of the light emitting diode ED. Therefore, the area of ​​the reflector RF disposed on one side of the center of the light emitting diode ED may be different from the area of ​​the reflector RF disposed on the other side.

[0184] Fig.11A and Fig. 11B is a graph for explaining the effect of a display device according to still another exemplary embodiment of the present disclosure. Fig.11A is a graph for explaining the brightness distribution of a display device according to a comparative example, and Fig. 11Bis a graph for explaining the luminance distribution of the display device 800 according to still another exemplary embodiment of the present disclosure. In the display device according to the comparative example, the plurality of patterns 819 and the cover layer 860 are not provided, which is different from the display device 800 according to another example of the present disclosure.

[0185] exist Fig.11A and Fig. 11B In the graph of , the X-axis represents the viewing angle, and shows that the position matching the center of the light emitting diode ED is 0°, one direction of the light emitting diode ED is (+), and the other direction of the light emitting diode ED is (-). Fig.11A and Fig. 11B In the graph of , the Y-axis indicates brightness, and the brightness in the front direction (ie, the brightness measured at 0°) is set to 1 in the comparative example.

[0186] Reference Fig.11A In the comparative example, it can be confirmed that the luminance in the lateral direction of -50° to -70° and in the lateral direction of 50° to 70° is higher than the luminance in the front direction, and the maximum luminance in one direction is different from the maximum luminance in the other direction. Fig. 11B , a maximum brightness of about 1.5 is obtained at a viewing angle of about 60° in one direction, and a maximum brightness of about 1.3 is obtained at a viewing angle of about -50° in another direction.

[0187] In contrast, reference Fig. 11B , in the display device 800 according to another exemplary embodiment of the present disclosure, the front brightness is about 1.35. Therefore, in the display device 800 according to another exemplary embodiment of the present disclosure, Fig.11A Compared with the comparative example, it can be confirmed that the front brightness increases by about 0.35.

[0188] In addition, refer to Fig. 11B , it can be confirmed that the maximum brightness in the lateral direction is similar to the front brightness, and there is almost no deviation between the maximum brightness in one direction and the maximum brightness in the other direction. Therefore, in the display device 800 according to another exemplary embodiment of the present disclosure, it can be confirmed that the viewing angle deviation is reduced more than the comparative example, and the brightness asymmetry is improved.

[0189] In a display device 800 according to another exemplary embodiment of the present disclosure, a plurality of annular patterns 819 formed of a low refractive index material are disposed under a cover layer 860 formed of a high refractive index material to extract light propagating laterally in a front direction. In addition, a display device 800 having high color reproducibility, high brightness, and high efficiency can be realized.

[0190] In addition, a reflective plate is provided in the display device, which is arranged to overlap with the light-emitting diode. At this time, the reflective plate can be formed of various reflective materials arranged on the display device. For example, in the display device, various electrodes or wirings arranged in the pixel circuit themselves can be used as reflective plates, or the reflective plate can be formed of the same material as the various electrodes or wirings arranged in the pixel circuit. Therefore, according to the position of the pixel circuit and the position of the light-emitting diode, the reflective plate can be formed to be asymmetric relative to the center of the light-emitting diode. Therefore, when the reflective plate is asymmetrically arranged, the brightness in a specific direction increases, and the viewing angle brightness distribution may be asymmetric.

[0191] In addition, the light emitting area of ​​the display device may be asymmetric with respect to the center of the light emitting diode. For example, when the light emitting diode is a lateral light emitting diode, the first electrode is disposed in an area other than the display area. Therefore, considering the arrangement of the first electrode, the active layer may be disposed asymmetrically and the light emitting area may also be asymmetric. Therefore, the maximum brightness in the area where the first electrode is disposed is different from the maximum brightness in the area where the second electrode is disposed.

[0192] In a display device 800 according to another exemplary embodiment of the present disclosure, a plurality of patterns 819 are asymmetrically arranged in consideration of the light emitting area A and the brightness distribution of the light emitting diode ED. For example, the spacing distance between the plurality of patterns 819 in the area with greater brightness is smaller than the spacing distance between the plurality of patterns 819 in the area with less brightness. Therefore, by adjusting the spacing distance between the plurality of patterns 819, the viewing angle brightness deviation is improved, and the asymmetric brightness is improved.

[0193] Fig.12 is a cross-sectional view of a pixel region of a display device according to still another exemplary embodiment of the present disclosure. Fig.12 The display device 1200 and Figures 1 to 3 The only difference between the display devices 100 is that a scattering layer 1280 is added, but other configurations are substantially the same, so redundant description will be omitted.

[0194] Reference Fig.12 , the scattering layer 1280 is disposed on the cover layer 160. The scattering layer 1280 includes scattering particles to improve the light extraction efficiency. The scattering particles may be nano-sized spherical inorganic oxide particles having light scattering properties. The scattering particles may be, for example, one of titanium dioxide (TiO2) particles, silicon dioxide (SiO2) particles, zinc oxide (ZnO) particles, and aluminum oxide (AlO4) particles, but are not limited thereto. In addition, the scattering particles may be spherical, porous, or fibrous, but are not limited thereto.

[0195] In a display device 1200 according to another exemplary embodiment of the present disclosure, a plurality of annular patterns 119 formed of a low refractive index material are disposed under a cover layer 160 formed of a high refractive index material to extract light propagating laterally in a front direction. In addition, a display device 1200 having high color reproducibility, high brightness, and high efficiency can be realized.

[0196] In addition, in the display device 1200 according to another exemplary embodiment of the present disclosure, a scattering layer 1280 including scattering particles is disposed on the light emitting diode ED. Therefore, light emitted from the light emitting diode ED is reflected or scattered by the scattering layer 1280 to improve light extraction efficiency.

[0197] Exemplary embodiments of the present disclosure may also be described as follows:

[0198] According to one aspect of the present disclosure, a display device is provided, which includes: a substrate; a light emitting diode disposed on the substrate; a plurality of patterns disposed on the light emitting diode and having a ring shape; and a cover layer located on the plurality of patterns, wherein the light emitting diode is a micro light emitting diode.

[0199] The spacing distance between any two adjacent patterns among the plurality of patterns may be the same.

[0200] A diameter of an outer circumference of an outermost pattern among the plurality of patterns may be two or more times the diameter of the light emitting diode.

[0201] The innermost pattern among the plurality of patterns may be formed to surround a circle having a diameter of 6 μm to 8 μm.

[0202] A width of a top surface of each of the plurality of patterns may be 3 μm.

[0203] An inclination angle formed by side surfaces of the plurality of patterns and bottom surfaces of the plurality of patterns may be 55 degrees or more.

[0204] Top surfaces of the plurality of patterns may be recessed toward the substrate.

[0205] The spacing distance between any two adjacent patterns among the plurality of patterns arranged on one side from the center of the light emitting diode may be different from the spacing distance between any two adjacent patterns among the plurality of patterns arranged on the other side from the center of the light emitting diode. The spacing distance between any two adjacent patterns among the plurality of patterns arranged on one side from the center of the light emitting diode may be smaller than the spacing distance between any two adjacent patterns among the plurality of patterns arranged on the other side from the center of the light emitting diode.

[0206] The display device also includes a reflector plate arranged below the light emitting diode, wherein the length of the reflector plate extending from the center of the light emitting diode to one side is shorter than the length of the reflector plate extending from the center of the light emitting diode to the other side.

[0207] The second electrode of the light emitting diode may be disposed on one side of the light emitting diode, and the first electrode of the light emitting diode may be disposed on the other side of the light emitting diode.

[0208] The display device may further include: a reflective plate disposed below the light emitting diode, wherein the reflective plate may be asymmetric relative to the center of the light emitting diode.

[0209] The refractive index of the plurality of patterns may be lower than the refractive index of the cover layer.

[0210] The pattern may be formed of a photoresist material, and the cover layer may be formed of parylene.

[0211] The display device may further include: a scattering layer disposed on the pattern and including scattering particles.

[0212] The scattering particles are nanometer-sized spherical inorganic oxide particles having light scattering properties.

[0213] According to another aspect of the present disclosure, a display device is provided. The display device includes: a substrate; a plurality of transistors disposed on the substrate; a plurality of light-emitting diodes connected to and disposed on the plurality of transistors; a protective layer disposed on the plurality of light-emitting diodes; and a plurality of patterns disposed on the protective layer to correspond to the plurality of light-emitting diodes, wherein the plurality of light-emitting diodes are micro light-emitting diodes (micro LEDs).

[0214] Top surfaces of the plurality of patterns may be curved surfaces recessed toward the substrate.

[0215] The maximum brightness at one side of the LED may be higher than the maximum brightness at the other side of the LED, and the spacing distance between any two adjacent patterns among the multiple patterns arranged on one side of the LED may be smaller than the spacing distance between any two adjacent patterns among the multiple patterns arranged on the other side of the LED.

[0216] The display device may further include: a reflective plate disposed below the light emitting diode, wherein the reflective plate is asymmetric with respect to a center of the light emitting diode, and wherein shapes of the plurality of patterns may be asymmetric with respect to the center of the light emitting diode.

[0217] The length of the reflective plate extending from the center of the light emitting diode to one side may be different from the length of the reflective plate extending from the center of the light emitting diode to the other side.

[0218] The display device may further include: a covering layer covering the plurality of patterns, wherein a refractive index of the covering layer may be greater than a refractive index of the plurality of patterns.

[0219] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the claims, and all technical concepts within their equivalent ranges should be interpreted as falling within the scope of the present disclosure.

[0220] CROSS-REFERENCE TO RELATED APPLICATIONS

[0221] This application claims the benefit of priority to Korean Patent Application No. 10-2023-0113441 filed in the Korean Intellectual Property Office on August 29, 2023, the entire contents of which are hereby expressly incorporated herein for all purposes.

Claims

1. A display device, comprising: substrate; A light emitting diode, wherein the light emitting diode is arranged on the substrate; a plurality of patterns, the plurality of patterns being disposed on the light emitting diode and having a ring shape; as well as a covering layer, the covering layer being located on the plurality of patterns, Wherein, the light emitting diode is a micro light emitting diode.

2. The display device according to claim 1, wherein: The spacing distance between any two adjacent patterns among the plurality of patterns is the same.

3. The display device according to claim 2, wherein: A diameter of an outer circumference of an outermost pattern among the plurality of patterns is two or more times greater than a diameter of the light emitting diode.

4. The display device according to claim 2, wherein: The innermost pattern among the plurality of patterns is formed to surround a circle having a diameter of 6 μm to 8 μm.

5. The display device according to claim 2, wherein: A width of a top surface of each of the plurality of patterns is 3 μm.

6. The display device according to claim 2, wherein: An inclination angle formed by side surfaces of the plurality of patterns and bottom surfaces of the plurality of patterns is 55 degrees or more.

7. The display device according to claim 1, wherein: A top surface of each of the plurality of patterns is recessed toward the substrate.

8. The display device according to claim 1, wherein: A spacing distance between any two adjacent patterns among the plurality of patterns disposed on one side from the center of the light emitting diode is different from a spacing distance between any two adjacent patterns among the plurality of patterns disposed on the other side from the center of the light emitting diode.

9. The display device according to claim 8, wherein: The spacing distance between any two adjacent patterns among the plurality of patterns disposed on the one side from the center of the light emitting diode is smaller than the spacing distance between any two adjacent patterns among the plurality of patterns disposed on the other side from the center of the light emitting diode.

10. The display device according to claim 9, further comprising: a reflective plate, the reflective plate being arranged below the light emitting diode, Wherein, a length of the reflective plate extending from the center of the light-emitting diode to one side is smaller than a length of the reflective plate extending from the center of the light-emitting diode to the other side.

11. The display device according to claim 9, wherein: The second electrode of the light emitting diode is disposed on one side of the light emitting diode, and the first electrode of the light emitting diode is disposed on the other side of the light emitting diode.

12. The display device according to claim 8, further comprising: a reflective plate, the reflective plate being arranged below the light emitting diode, Wherein, the reflection plate is asymmetric with respect to the center of the light emitting diode.

13. The display device according to claim 1, wherein: The refractive index of the plurality of patterns is lower than the refractive index of the cover layer.

14. The display device according to claim 1, wherein: The plurality of patterns are formed of a photoresist material, and the capping layer is formed of parylene.

15. The display device according to claim 1, further comprising: A scattering layer is disposed on the plurality of patterns and includes scattering particles.

16. The display device according to claim 15, wherein: The scattering particles are nano-sized spherical inorganic oxide particles having light scattering properties.

17. A display device, comprising: substrate; a plurality of transistors, wherein the plurality of transistors are disposed on the substrate; a plurality of light emitting diodes connected to the plurality of transistors and disposed on the plurality of transistors; A protective layer, the protective layer being disposed on the plurality of light emitting diodes; as well as a plurality of patterns, the plurality of patterns being arranged on the protection layer to correspond to the plurality of light emitting diodes, Wherein, the plurality of light emitting diodes are micro light emitting diodes.

18. The display device according to claim 17, wherein: A top surface of each of the plurality of patterns is a curved surface recessed toward the substrate.

19. The display device according to claim 17, wherein: The maximum brightness at one side of the light-emitting diode is higher than the maximum brightness at the other side of the light-emitting diode, and the spacing distance between any two adjacent patterns among the multiple patterns arranged on the one side of the light-emitting diode is smaller than the spacing distance between any two adjacent patterns among the multiple patterns arranged on the other side of the light-emitting diode.

20. The display device according to claim 17, further comprising: a reflective plate, the reflective plate being arranged below the light emitting diode, The reflector is asymmetric relative to the center of the light emitting diode, and The shapes of the plurality of patterns are asymmetric with respect to the center of the light emitting diode.

21. The display device according to claim 20, wherein: A length of the reflection plate extending from the center of the light emitting diode to one side is smaller than a length of the reflection plate extending from the center of the light emitting diode to the other side.

22. The display device according to claim 17, further comprising: a covering layer, the covering layer covering the plurality of patterns, Wherein, the refractive index of the covering layer is greater than the refractive index of the plurality of patterns.

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