Gate drive circuit, display panel and display device

Abstract

The invention provides a gate drive circuit, a display panel and a display device, and the gate drive circuit comprises an input module which is used for accessing a cascade signal outputted by a previous stage and inputting a preset high potential to a first node; the output module is used for controlling the output potential of the current-stage signal output node under the control of the potentials of the first node and the second node; the isolation module is used for isolating the potentials of the first node and the second node; the maintaining module is used for maintaining the potentials of the first node, the second node and the current-stage signal output node; and the reset module is used for resetting the potentials of the first node, the second node and the current-stage signal output node to low potentials. According to the scheme, the gate drive circuit, the display panel and the display device can solve the problem that the display picture of the display panel can have pit patterns.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit, a display panel and a display device. Background Art

[0002] At present, in order to improve the touch sensitivity of embedded touch display panels, it is generally adopted to insert touch signals multiple times during the display time of a frame of picture, which requires multiple stop pits, which will interrupt the normal display. In the gate drive circuit, some gate drive units will store charge through the pits, which will cause the threshold voltage of the thin film transistors in some gate drive units to drift forward. When displaying the picture, there are certain differences between the scanning signals generated by these gate drive units and the scanning signals generated by other gate drive units, resulting in the appearance of horizontal stripes (also called "stop pit stripes"), which affects the display effect. Summary of the invention

[0003] The embodiments of the present application provide a gate driving circuit, a display panel and a display device to solve the problem in the related art that the display panel may have stop grooves that affect the display effect.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] In a first aspect, the present application provides a gate driving circuit, comprising a plurality of cascaded gate driving units, at least one of the gate driving units comprising:

[0006] An input module, electrically connected to the first node, for receiving the cascade signal outputted from the previous stage and inputting a preset high potential to the first node;

[0007] an output module, electrically connected to the second node and the signal output node of the current stage, and configured to control the output potential of the signal output node of the current stage according to the potential of the first node and the potential of the second node;

[0008] an isolation module, electrically connected to the first node and the second node, and configured to isolate the potentials of the first node and the second node in response to an inverted signal of a touch signal;

[0009] a maintaining module, electrically connected to the first node, the second node and the current-stage signal output node, and configured to maintain the potentials of the first node, the second node and the current-stage signal output node; and

[0010] A reset module is electrically connected to the first node, the second node and the current-stage signal output node, and is used to reset the potentials of the first node, the second node and the current-stage signal output node.

[0011] In one embodiment, the input module comprises:

[0012] The first transistor includes a control electrode connected to the cascade signal output by the previous stage, a first electrode electrically connected to the control electrode, and a second electrode electrically connected to the first node.

[0013] In one embodiment, the output module includes:

[0014] A second transistor includes a control electrode electrically connected to the second node, a first electrode connected to the first clock signal, and a second electrode electrically connected to the signal output node of the current stage; and

[0015] The first capacitor includes a first electrode electrically connected to the first node and a second electrode electrically connected to the signal output node of the current stage.

[0016] In one embodiment, the isolation module comprises:

[0017] The third transistor includes a control electrode connected to the inverted signal of the touch signal, a first electrode electrically connected to the first node, and a second electrode electrically connected to the second node.

[0018] In one embodiment, the maintenance module comprises:

[0019] a first maintaining submodule, electrically connected to the first node, and configured to maintain the potential of the first node;

[0020] a second maintaining submodule, electrically connected to the second node, and configured to maintain the potential of the second node;

[0021] The third maintaining submodule is electrically connected to the signal output node of the current stage, and is used to maintain the potential of the signal output node of the current stage.

[0022] In one embodiment, the first maintaining submodule includes:

[0023] a fourth transistor including a second electrode, a control electrode electrically connected to the first node, and a first electrode; and,

[0024] The fifth transistor includes a control electrode electrically connected to the second electrode of the fourth transistor, a first electrode connected to the touch signal, and a second electrode electrically connected to the first node.

[0025] In one embodiment, the second maintaining submodule includes:

[0026] A first inverter includes an output terminal and an input terminal electrically connected to the second node; and

[0027] The sixth transistor includes a control electrode electrically connected to the output end of the first inverter, a first electrode electrically connected to the second node, and a second electrode connected to a constant low potential signal.

[0028] In one embodiment, the third maintaining submodule includes:

[0029] A first inverter includes an output terminal and an input terminal electrically connected to the second node; and

[0030] The seventh transistor includes a control electrode electrically connected to the output end of the first inverter, a first electrode electrically connected to the signal output node of the current stage, and a second electrode of the sixth transistor connected to a constant low potential signal.

[0031] In one embodiment, the reset module includes:

[0032] a first resetting submodule, electrically connected to the first node, and resetting the potential of the first node in response to a cascade signal of a next stage;

[0033] A second resetting submodule, electrically connected to the second node, and configured to discharge and reset the potential of the second node;

[0034] The third resetting submodule is electrically connected to the signal output node of the current stage, and is used to reset the potential of the signal output node of the current stage.

[0035] In one embodiment, the first resetting submodule includes:

[0036] The eighth transistor includes a control electrode connected to the cascade signal of the next stage, a first electrode electrically connected to the first node, and a second electrode connected to a constant low potential signal.

[0037] In one embodiment, the second resetting submodule includes:

[0038] The ninth transistor includes a control electrode connected to the touch signal, a first electrode electrically connected to the second node, and a second electrode connected to a constant low potential signal.

[0039] In one embodiment, the third resetting submodule includes:

[0040] The tenth transistor includes a gate of the tenth transistor connected to a control electrode of a touch signal, a first electrode electrically connected to the signal output node of the current stage, and a second electrode connected to a constant low potential signal.

[0041] In a second aspect, the present application also provides a display panel, comprising the above-mentioned gate driving circuit.

[0042] In a third aspect, the present application also provides a display device, comprising the above-mentioned display panel.

[0043] The present application provides a gate driving circuit, a display panel and a display device, wherein the gate driving circuit includes a plurality of cascaded gate driving units, at least one of the gate driving units includes: an input module electrically connected to a first node, for accessing a cascade signal outputted from a previous stage to input a preset high potential to the first node; an output module electrically connected to a second node and a signal output node of a current stage, for controlling the output potential of the signal output node of the current stage under the control of the potentials of the first node and the second node; an isolation module electrically connected to the first node and the second node, for isolating the potentials of the first node and the second node in response to an inverted signal of a touch signal; a maintaining module electrically connected to the first node, the second node and the signal output node of the current stage, for maintaining the potentials of the first node, the second node and the signal output node of the current stage; and a reset module electrically connected to the first node, the second node and the signal output node of the current stage, for resetting the potentials of the first node, the second node and the signal output node of the current stage. Through the above scheme, by setting an isolation module, the first node and the second node are separated, so that the display device can display normally in the display stage. In the touch stage, the first node is kept at a high potential, and the second node and the signal output node of this level are pulled down to a continuous low potential by the reset module, so that the stress of the transistor in the gate drive circuit remains consistent and there is no pitting problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0045] Attached Figure 1 This is a schematic diagram of the overall module of the gate driving unit in the embodiment of the present application;

[0046] Attached Figure 2 This is a schematic diagram of a specific module of a gate driving unit in an embodiment of the present application;

[0047] Attached Figure 3 is a circuit structure diagram of a gate driving unit in an embodiment of the present application;

[0048] Attached Figure 4 This is a working timing diagram of the gate driving unit in the embodiment of the present application;

[0049] Attached Figure 5 This is a schematic diagram of the structure of the display panel in the embodiment of the present application;

[0050] Attached Figure 6 Schematic diagram of the structure of the display device in the embodiment of the present application.

[0051] 1. Display device; 10. Display panel; 11. Gate drive circuit;

[0052] 100, gate drive unit; 110, input module; 120, output module; 130, isolation module; 140, maintenance module; 141, first maintenance submodule; 142, second maintenance submodule; 143, third maintenance submodule; 150, reset module; 151, first reset submodule; 152, second reset submodule; 153, third reset submodule. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0054] It should be noted that the transistors used in the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present application, in order to distinguish the source and drain of the transistor, one of the poles is called the first pole, and the other pole is called the second pole. In addition, the gate of the transistor is called the control pole. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. The following embodiments are explained with N-type transistors. When an N-type transistor is used, the first pole is the source of the N-type transistor, and the second pole is the drain of the N-type transistor. When the gate inputs a high level, the source and drain are turned on, and the P-type is the opposite. It can be imagined that the use of P-type transistors is something that a technician in the field can easily think of without paying creative labor, so it is also within the scope of protection of the embodiments of the present application.

[0055] Among them, since the transistors used in the embodiments of the present application are all N-type transistors, the working level signal in the embodiments of the present application refers to a high level signal, and the non-working level signal is a low level signal.

[0056] Reference Figure 1According to the first aspect of the present application, a gate driving circuit 11 is provided, which includes a plurality of cascaded gate driving units 100, at least one gate driving unit 100 includes: an input module 110, an output module 120, an isolation module 130, a maintenance module 140 and a reset module 150. Among them, the input module 110 is electrically connected to the first node Q, and is used to access the cascade signal G(N-1) output by the previous level to input a preset high potential to the first node Q; the output module 120 is electrically connected to the second node O and the signal output node G of the current level, and is used to control the output potential of the signal output node G of the current level under the control of the potentials of the first node Q and the second node O; the isolation module 130 is electrically connected to the first node Q and the second node O, and is used to isolate the potentials of the first node Q and the second node O in response to the inverted signal of the touch signal; the maintenance module 140 is electrically connected to the first node Q, the second node O and the signal output node G of the current level, and is used to maintain the potentials of the first node Q, the second node O and the signal output node G of the current level; the reset module 150 is electrically connected to the first node Q, the second node O and the signal output node G of the current level, and is used to reset the potentials of the first node Q, the second node O and the signal output node G of the current level to a low potential.

[0057] It should be noted that the output signal of the output node of this level, i.e., the output signal of the current row, not only outputs and drives the pixels of this row, but also serves as a reset signal of the previous row and an input signal of the next row. In the entire gate drive circuit 11, the input signal of the gate drive unit 100 of the first row is the frame start signal STV, and the first row does not output a reset signal; the gate drive unit 100 of the last row is connected to a row of Dummy to achieve the reset of the gate drive unit 100 of the last row.

[0058] Specifically, refer to Figure 2 In some embodiments of the present application, the maintaining module 140 includes: a first maintaining submodule 141, a second maintaining submodule 142 and a third maintaining submodule 143. The first maintaining submodule 141 is electrically connected to the first node Q, and is used to maintain the potential of the first node Q; the second maintaining submodule 142 is electrically connected to the second node O, and is used to maintain the potential of the second node O; the third maintaining submodule 143 is electrically connected to the current stage signal output node G, and is used to maintain the potential of the current stage signal output node G.

[0059] In some embodiments of the present application, the reset module 150 includes: a first reset submodule 151, a second reset submodule 152 and a third reset submodule 153. The first reset submodule 151 is electrically connected to the first node Q, and resets the potential of the first node Q in response to the cascade signal G(N+1) of the next stage; the second reset submodule 152 is electrically connected to the second node O, and is used to discharge and reset the potential of the second node O; the third reset submodule 153 is electrically connected to the signal output node G of the current stage, and is used to reset the potential of the signal output node G of the current stage.

[0060] More specifically, see Figure 3 In some embodiments of the present application, the input module 110 includes: a first transistor T1, the control electrode of the first transistor T1 is connected to the cascade signal G(N-1) output by the previous stage, the first electrode of the first transistor T1 is electrically connected to the control electrode of the first transistor T1, and the second electrode of the first transistor T1 is electrically connected to the first node Q.

[0061] In some embodiments of the present application, the output module 120 includes a second transistor T2 and a first capacitor C1. Among them, the control electrode of the second transistor T2 is connected to the second node O, the first electrode of the second transistor T2 is connected to the first clock signal, and the second electrode of the second transistor T2 is connected to the current signal output node G; the first electrode of the first capacitor C1 is connected to the first node Q, and the second electrode of the first capacitor C1 is connected to the current signal output node G. It should be noted that the second node O is the pull-up control node, the current signal output node G is connected to the current control electrode signal scan line, the second transistor T2 pulls up and outputs and pulls down to clear the current control electrode signal scan line, and the first capacitor C1 is a bootstrap capacitor, which is used to lift and stabilize the potential of the pull-up control node during the output process through capacitive coupling, thereby increasing the charging speed of the scan signal line.

[0062] In some embodiments of the present application, the isolation module 130 includes a third transistor T3, the control electrode of the third transistor T3 is connected to the inverted signal of the touch signal, the first electrode of the third transistor T3 is connected to the first node Q, and the second electrode of the third transistor T3 is connected to the second node O.

[0063] In some embodiments of the present application, the first maintaining submodule 141 includes a fourth transistor T4 and a fifth transistor T5, wherein the control electrode and the first electrode of the fourth transistor T4 are electrically connected to the first node Q; the control electrode of the fifth transistor T5 is electrically connected to the second electrode of the fourth transistor T4, the first electrode of the fifth transistor T5 is connected to the touch signal, and the second electrode of the fifth transistor T5 is electrically connected to the first node Q.

[0064] In some embodiments of the present application, the second maintaining submodule 142 includes a first inverter and a sixth transistor T6, wherein the input end of the first inverter is electrically connected to the second node O; and the control electrode of the sixth transistor T6 is electrically connected to the output end of the first inverter; the first electrode of the sixth transistor T6 is electrically connected to the second node O, and the second electrode of the sixth transistor T6 is connected to a constant low potential signal. It should be noted that the constant low potential signal in the embodiment of the present application can be the control electrode shutdown voltage VGL of the display panel 10.

[0065] In some embodiments of the present application, the third maintaining submodule 143 includes: a first inverter and a seventh transistor T7, wherein the input end of the first inverter is electrically connected to the second node O; the control electrode of the seventh transistor T7 is electrically connected to the output end of the first inverter, the first electrode of the seventh transistor T7 is electrically connected to the signal output node G of the current stage, and the second electrode of the sixth transistor T6 is connected to a constant low potential signal. It should be noted that in this embodiment, the third maintaining submodule 143 and the second maintaining submodule 142 both use the first inverter, which can be the same inverter, and the sixth transistor T6 and the seventh transistor T7 are connected to different output ends of the first inverter. In some embodiments, the second maintaining submodule 142 and the third maintaining submodule 143 can also use different inverters, and the present application does not limit this.

[0066] In some embodiments of the present application, the first reset submodule 151 includes an eighth transistor T8, the control electrode of the eighth transistor T8 is connected to the cascade signal G(N+1) of the next stage, the first electrode of the eighth transistor T8 is electrically connected to the first node Q, and the second electrode of the eighth transistor T8 is connected to a constant low potential signal.

[0067] In some embodiments of the present application, the second reset submodule 152 includes a ninth transistor T9, the control electrode of the ninth transistor T9 is connected to the touch signal, the first electrode of the ninth transistor T9 is electrically connected to the second node O, and the second electrode of the ninth transistor T9 is connected to a constant low potential signal. In addition to replacing the general reset circuit, the ninth transistor T9 can also clear the charge of the second node O each time the pit stops, reducing the risk of residual charge.

[0068] In some embodiments of the present application, the third reset submodule 153 includes a tenth transistor T10, the control electrode of the tenth transistor T10 is connected to the touch signal, the first electrode of the tenth transistor T10 is electrically connected to the signal output node G of this stage, and the second electrode of the tenth transistor T10 is connected to a constant low potential signal. It should be noted that the control electrode of the ninth transistor T9 is interconnected with the control electrode of the tenth transistor T10, and the touch signal is connected. Among them, the function of the tenth transistor T10 is similar to that of the ninth transistor T9. In addition to replacing the general reset circuit, the charge of the signal output node G of this stage can also be cleared at each pit stop to reduce the risk of residual charge. In addition, through the tenth transistor T10, a small waveform can be synchronously output to the signal output node G of this stage, reducing the in-plane loading time of the display panel 10 and improving the touch performance of the display panel 10.

[0069] It should be noted that the gate drive circuit 11 needs to be paused during the touch stage to collect the touch signal. At this time, the clock signal requires the pulse signal to be paused and set to a constant low potential signal. After the touch stage ends, the clock signal can resume the normal pulse signal. This inevitably requires the pull-up nodes of some gate drive units 100 (i.e., the second node O of the present application) to store a high voltage during the touch period. After the touch period ends, the gate drive circuit 11 can continue to work normally. Among them, the pull-up node stores a high voltage during the touch stage, which is called the stop level, and the potential of the pull-up node of most gate drive units 100 is low during the touch period. The related art does not have an isolation module to separate the first node Q from the second node O. Therefore, the voltage difference problem of the pull-up nodes of the stop level and the non-stop level is likely to form the stop pattern problem.

[0070] Reference Figure 4 As shown, Figure 3 The timing diagram of some signals in the gate driving unit 100 is shown, and the following is analyzed by stage:

[0071] In the display stage 1, the inverted signal of the touch signal set in the present application is at a high potential, the third transistor T3 is in a normally-on state, at which time the first node Q and the second node O are both at a high potential, and the display panel 10 displays normally.

[0072] In the touch stage, the inverted signal of the touch signal becomes a low potential, at which time the third transistor T3 is turned off, the first node Q maintains a high potential, and the second node O and the current signal output node G are respectively pulled to a low potential by the ninth transistor T9 and the tenth transistor T10. The present application allows the second node O to be pulled down to a low potential in the touch stage without having to maintain a high potential uniformly, thereby avoiding the stress problem caused by the uniform conduction of the second transistor, so that the stresses of the second transistor T2, the sixth transistor T6 and the seventh transistor T7 are kept consistent. It should be noted that transistors are affected by stress when working, such as from temperature changes, electric fields, mechanical stress, etc. It is very important to keep the stress of multiple transistors consistent, because the stress difference between different transistors may cause uneven performance, reliability problems or device failures. If the stress difference between transistors is too large, it may cause the performance of some transistors to decline or even fail.

[0073] At the end of the pit stop, that is, in stage 2 shown in the figure, the inverted signal of the touch signal changes from a low potential to a high potential, the third transistor T3 is turned on, the first node Q charges the second node O, and the second transistor T2 is turned on at this time, that is, normal level transmission is restored.

[0074] According to a second aspect of the present application, a display panel 10 is provided, comprising the above-mentioned gate driving circuit 11. The display panel 10 has all the beneficial effects of the above-mentioned gate driving circuit 11, which will not be described in detail in the present application.

[0075] Reference Figure 5As shown, specifically, in some embodiments of the present application, the display panel 10 includes a plurality of scan lines, a plurality of data lines, a plurality of sub-pixels arranged in an array, and a gate driving circuit 11 provided in any of the above embodiments, the gate driving circuit 11 is electrically connected to the scan lines, and each sub-pixel is electrically connected to a scan line and a data line. Among them, the gate driving circuit 11 includes a plurality of cascaded gate driving units 100, and the gate driving unit 100 at least includes: an input module 110, electrically connected to the first node Q, for accessing the cascade signal G(N-1) outputted from the previous stage to input a preset high potential to the first node Q; an output module 120, electrically connected to the second node O and the signal output node G of the current stage, for controlling the output potential of the signal output node G of the current stage under the control of the potentials of the first node Q and the second node O; an isolation module 130, electrically connected to the first node Q and the second node O, for isolating the potentials of the first node Q and the second node O in response to the inverted signal of the touch signal; a maintaining module 140, electrically connected to the first node Q, the second node O and the signal output node G of the current stage, for maintaining the potentials of the first node Q, the second node O and the signal output node G of the current stage; and a reset module 150, electrically connected to the first node Q, the second node O and the signal output node G of the current stage, for resetting the potentials of the first node Q, the second node O and the signal output node G of the current stage to a low potential.

[0076] Therefore, when the display panel provided in the embodiment of the present application includes the above-mentioned gate driving circuit, it has all the beneficial effects of the above-mentioned gate driving circuit, which will not be described in detail here.

[0077] It should be noted that the display panel provided in the embodiment of the present application can be applied to any product or component with a display function, such as televisions, monitors, digital photo frames, mobile phones, tablet computers, etc., wherein the display panel can also be used in combination with a flexible circuit board, a printed circuit board and a backplane.

[0078] Reference Figure 6 As shown, according to the third aspect of the present application, a display device 1 is provided, comprising a display panel 10 of any of the above-mentioned embodiments, and also comprising a source driving circuit, a system on chip, a power management chip and a timing driver, etc. The display device 1 has all the beneficial effects of the above-mentioned display panel 10, which will not be repeated in this application.

[0079] It should be noted that the display device can be any product or component with a display function, such as the above-mentioned television, monitor, digital photo frame, mobile phone, tablet computer, etc.

[0080] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0081] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0082] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0083] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A gate drive circuit, characterized in that: The invention comprises a plurality of cascaded gate driving units, at least one of the gate driving units comprising: An input module, electrically connected to the first node, for receiving the cascade signal outputted from the previous stage and inputting a preset high potential to the first node; an output module, electrically connected to the second node and the signal output node of the current stage, and configured to control the output potential of the signal output node of the current stage according to the potential of the first node and the potential of the second node; an isolation module, electrically connected to the first node and the second node, and configured to isolate the potentials of the first node and the second node in response to an inverted signal of a touch signal; a maintaining module, electrically connected to the first node, the second node and the current-stage signal output node, and configured to maintain the potentials of the first node, the second node and the current-stage signal output node; and A reset module is electrically connected to the first node, the second node and the current-stage signal output node, and is used to reset the potentials of the first node, the second node and the current-stage signal output node to a low potential.

2. The gate driving circuit according to claim 1, characterized in that: The input module comprises: The first transistor includes a control electrode connected to the cascade signal output by the previous stage, a first electrode electrically connected to the control electrode, and a second electrode electrically connected to the first node.

3. The gate driving circuit according to claim 1, characterized in that: The output module comprises: A second transistor includes a control electrode electrically connected to the second node, a first electrode connected to the first clock signal, and a second electrode electrically connected to the signal output node of the current stage; and The first capacitor includes a first electrode electrically connected to the first node and a second electrode electrically connected to the signal output node of the current stage.

4. The gate driving circuit according to claim 1, characterized in that: The isolation module comprises: The third transistor includes a control electrode connected to the inverted signal of the touch signal, a first electrode electrically connected to the first node, and a second electrode electrically connected to the second node.

5. The gate driving circuit according to claim 1, characterized in that: The maintenance module comprises: a first maintaining submodule, electrically connected to the first node, and configured to maintain the potential of the first node; a second maintaining submodule, electrically connected to the second node, and configured to maintain the potential of the second node; The third maintaining submodule is electrically connected to the signal output node of the current stage, and is used to maintain the potential of the signal output node of the current stage.

6. The gate driving circuit according to claim 5, characterized in that: The first maintaining submodule comprises: a fourth transistor including a second electrode, a control electrode electrically connected to the first node, and a first electrode; and, The fifth transistor includes a control electrode electrically connected to the second electrode of the fourth transistor, a first electrode connected to the touch signal, and a second electrode electrically connected to the first node.

7. The gate driving circuit according to claim 5, characterized in that: The second maintaining submodule comprises: A first inverter includes an output terminal and an input terminal electrically connected to the second node; and The sixth transistor includes a control electrode electrically connected to the output end of the first inverter, a first electrode electrically connected to the second node, and a second electrode connected to a constant low potential signal.

8. The gate driving circuit according to claim 5, characterized in that: The third maintaining submodule comprises: A first inverter includes an output terminal and an input terminal electrically connected to the second node; and The seventh transistor includes a control electrode electrically connected to the output end of the first inverter, a first electrode electrically connected to the signal output node of the current stage, and a second electrode of the sixth transistor connected to a constant low potential signal.

9. The gate driving circuit according to claim 1, characterized in that: The reset module comprises: a first resetting submodule, electrically connected to the first node, and resetting the potential of the first node in response to a cascade signal of a next stage; A second resetting submodule, electrically connected to the second node, and configured to discharge and reset the potential of the second node; The third resetting submodule is electrically connected to the signal output node of the current stage, and is used to reset the potential of the signal output node of the current stage.

10. The gate driving circuit according to claim 9, characterized in that: The first reset submodule includes: The eighth transistor includes a control electrode connected to the cascade signal of the next stage, a first electrode electrically connected to the first node, and a second electrode connected to a constant low potential signal.

11. The gate driving circuit according to claim 9, characterized in that: The second reset submodule comprises: The ninth transistor includes a control electrode connected to the touch signal, a first electrode electrically connected to the second node, and a second electrode connected to a constant low potential signal.

12. The gate driving circuit according to claim 9, characterized in that: The third reset submodule comprises: The tenth transistor includes a gate of the tenth transistor connected to a control electrode of a touch signal, a first electrode electrically connected to the signal output node of the current stage, and a second electrode connected to a constant low potential signal.

13. A display panel, characterized in that: A gate drive circuit comprising any one of claims 1 to 12.

14. A display device, characterized in that: Includes the display panel as claimed in claim 13.

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