Optical module interface circuit and communication system

Abstract

The optical module interface circuit comprises a first resistor and a second resistor, one end of the first resistor is connected with a first LVDS interface, the other end of the first resistor is grounded, one end of the second resistor is connected with a second LVDS interface, and the other end of the second resistor is grounded; the fifth resistor is connected with the first LVDS interface, and the sixth resistor is connected with the second LVDS interface. The communication system further comprises an FPGA, a fifth resistor of the optical module interface circuit is connected with a first LVDS interface of the FPGA, a sixth resistor of the optical module interface circuit is connected with a second LVDS interface of the FPGA, and the FPGA is configured to introduce an overtime reset mechanism and a receiving reset mechanism. The overtime reset mechanism comprises the following steps of: monitoring the SD, and resetting once when the SD is not turned over for a preset time; the receiving reset mechanism is characterized in that when the SD is detected to be overturned, primary reset is carried out actively. And the GPON OLT, the GPON ONU and a common optical module can be compatible at the same time.

Description

Technical Field

[0001] The present invention belongs to the technical field of optical fiber communication, and in particular relates to an optical module interface circuit and a communication system. Background Art

[0002] At present, with the continuous development of all walks of life, automation control scenarios with different needs and different volumes have emerged, which put forward higher and higher requirements for the scalability and customizability of the control system. Fiber-optic communication has many advantages over traditional copper wire communication. First, optical fiber has high bandwidth characteristics and can support faster data transmission speeds to meet the needs of modern communication for large data transmission. Secondly, optical fiber signal transmission is almost unaffected by distance, with less signal attenuation, and can cover longer distances and maintain communication stability. In addition, optical fiber communication is not easily affected by electromagnetic interference and external environment, and has high anti-interference ability. Therefore, optical fiber communication is widely used in modern communication networks, providing a reliable and efficient solution for communication transmission.

[0003] However, traditional fiber-optic communications usually use LVDS interfaces, which can only achieve point-to-point communication and are difficult to meet the current widespread multi-node design requirements.

[0004] There are two main existing solutions. The first solution is to form a mesh structure through cascading between modules to achieve multi-node optical port communication. The second solution is to use traditional GPON to achieve a point-to-multipoint star topology through GPON MAC, OLT, ONU and ODN network to achieve multi-point communication.

[0005] The first solution has two obvious disadvantages. First, in a cascaded mesh topology, if a node close to the starting segment is lost, all nodes under that node will be affected and face security risks. Second, this solution requires communication signals to be continuously forwarded between nodes, which will limit communication efficiency. If switches are used for auxiliary cascading, huge transmission costs will also be incurred.

[0006] In the second solution, the use of traditional GPON technology will lead to a significant increase in hardware implementation costs because the MAC that comes with GPON needs to be used. In addition, the MACs of OLT and ONU use different signal physical layers and protocols, so different MACs need to be adjusted in circuit design, which may result in the need to design two communication systems with different hardware. If compatibility with ordinary optical modules is also required, three different sets of hardware will be required, which will significantly increase the development and maintenance costs of the product. In addition, due to the use of conventional GPON technology, its public data encryption method may have an adverse effect on data security, resulting in lower data security. Summary of the invention

[0007] To solve the above problems, the present invention provides an optical module interface circuit and communication system, which can be compatible with GPON OLT (Gigabit passive optical network Optical Line Termination), GPON ONU (Gigabit passive optical network Optical Network Unit) and ordinary SFP optical modules at the same time. The interface design can realize the pluggable function. Users can choose to insert the GPON module to connect to the ODN network to realize GPON communication, or insert the ordinary optical module to realize point-to-point communication, which greatly simplifies the hardware cost of the system equipment and improves the flexibility and versatility of the product. In addition, the invention significantly reduces the development and maintenance costs, and has better security due to the private customization of its communication protocol.

[0008] The technical solution provided by the present invention is: an optical module interface circuit, comprising:

[0009] A first resistor and a second resistor, wherein one end of the first resistor is connected to the first LVDS interface and the other end is grounded, and one end of the second resistor is connected to the second LVDS interface and the other end is grounded;

[0010] A fifth resistor and a sixth resistor, wherein the fifth resistor is connected to the first LVDS interface, and the sixth resistor is connected to the second LVDS interface.

[0011] Preferably, it also includes a third resistor, a fourth resistor and a 3.3V DC power supply, one end of the third resistor is connected to the 3.3V DC power supply, and the other end is connected to the second end of the fifth resistor, and one end of the fourth resistor is connected to the 3.3V DC power supply, and the other end is connected to the second end of the sixth resistor.

[0012] Preferably, the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor satisfy the following relationship:

[0013]

[0014] 100≤800-R5×14≤680

[0015] 100≤800-R5×16≤680

[0016] 100≤350-R5×2×3.5≤680

[0017] R5=R6.

[0018] Preferably, a difference between a ratio of the resistance values ​​of the third resistor to the first resistor and 1.5 satisfies a preset threshold.

[0019] Preferably, the resistance values ​​of the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor are respectively:

[0020] R1=R2=82ohm.

[0021] R3=R4=120ohm

[0022] R5=R6=22ohm

[0023] Based on the same concept, the present invention further provides a communication system, comprising any one of the optical module interface circuits described above.

[0024] Preferably, it further comprises an FPGA, wherein the fifth resistor of the optical module interface circuit is connected to the first LVDS interface of the FPGA, the sixth resistor of the optical module interface circuit is connected to the second LVDS interface of the FPGA, and the FPGA is configured to introduce a timeout reset mechanism and a reception reset mechanism;

[0025] The timeout reset mechanism is: monitoring SD, and when SD does not flip over for a preset time, a reset is performed;

[0026] The receiving reset mechanism is: when SD flip is detected, a reset is actively performed.

[0027] Preferably, when the optical module is in place, the IIC interface of the fourth and fifth pins of the FPGA reads the optical signal wavelength information of the optical module in place to determine whether the optical module in place is a GPON OLT, and then determines whether to enable RX_Reset of the seventh pin of the FPGA according to a preset mechanism.

[0028] Preferably, the GPON optical module in the communication system is directly connected to the processor chip, so as to realize the application topology of only its physical layer; on the data link where the optical network unit sends and the optical network terminal receives, the optical network unit sending end is configured to remain in a static state when no packet is sent, and the bus has a stable level.

[0029] Preferably, token scheduling is selected as the communication scheduling mode of the communication system, and a dial code is set on each node in hardware. Each node has a unique identification number through different dial codes. The data frame includes a preamble and a token packet. The length of the preamble segment is less than the reset signal. When a node sends a data frame to the outside, all nodes on the bus can receive the data frame. Each node compares the identification number in the data frame with its own identification number. If the comparison is successful, the node replies with the data, otherwise the data will be lost.

[0030] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art:

[0031] The technical solution of the present invention enables the signal matching circuit at the receiving end of the optical module interface to simultaneously meet the signal range requirements of the GPON module and the ordinary optical module, and limits the resistance value of each resistor in the matching circuit, so that it can be compatible with the GPON OLT, GPON ONU and the ordinary optical module at the same time. The interface design can realize the pluggable function. The user can choose to insert the GPON module to connect to the ODN network to realize GPON communication, and can also insert the ordinary optical module to realize point-to-point communication, which greatly simplifies the hardware cost of the system equipment and improves the flexibility and versatility of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings, wherein:

[0033] Figure 1 This is a signal matching circuit diagram of the optical module interface receiving end of the present invention;

[0034] Figure 2 It is a key circuit diagram of the optical module interface package of the present invention;

[0035] Figure 3 It is a key circuit diagram of the optical module interface package of the present invention;

[0036] Figure 4 A schematic block diagram of an optical fiber communication system connected to a GPON module;

[0037] Figure 5 It is a schematic block diagram of an optical fiber communication system connected with ordinary optical modules;

[0038] Figure 6 This is the timing diagram of the optical network terminal reception. DETAILED DESCRIPTION

[0039] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0040] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0041] First embodiment

[0042] See also Figure 1 , is the optical module interface receiving end signal matching circuit diagram of the present invention, in this embodiment, FPGA is used as the communication system main chip platform, and the signal interface type provided is LVDS. In the receiving end signal matching circuit design, the RX resistor network needs to be compatible with GPON OLT, GPON ONU and ordinary optical module at the same time. In the optical module interface receiving end circuit signal transmission, the output interface type of GPON OLT is LVPECL without AC coupling, the output interface type of GPON ONU is CML with AC coupling, and the output interface type of ordinary optical module is LVDS. Therefore, the LVDS interface provided by FPGA needs to be able to meet these three output interface standards at the same time.

[0043] The signal matching circuit at the receiving end of the optical module interface needs to adapt to the above three high-speed level matching conditions respectively. According to the three high-speed level standards, the following signal matching circuit requirements are listed respectively:

[0044] 1. The receiving end of the LVDS interface needs to be set to 100ohm differential matching impedance;

[0045] 2. The signal at the LVPECL transmitter needs to be terminated at a common mode level through a 50ohm resistor, which is VCC-2V=1.3V in the standard. When used with LVDS, this level needs to be within the LVDS receiving common mode requirement;

[0046] 3. The output common-mode voltage of LVPECL and CML are within the standard range of the common-mode voltage of the LVDS receiver. According to the standard, the input standard of LVDS is 0.227 to 2.173V.

[0047] 4. By connecting resistors in series on the signal lines, the voltage swing of LVPECL and CML is within the LVDS standard range, which is 100 to 680mV.

[0048] The interface design method of this patent is mainly divided into two parts: the unification of the optical module signal matching circuit and the control method of the GPON module. This design method effectively achieves compatibility with GPON applications and improves the flexibility and scalability of the interface.

[0049] According to the above requirements, RX+ and RX- are biased to the same voltage using resistor networks, and the differential impedance is the sum of the impedances of the two resistor networks relative to the voltage. For the swing requirement, choose to connect resistors in series at the FPGA pin end. Since CML, LVDS, and LVPECL are all current-driven logic levels, the signal swing at the LVDS receiving end can be calculated based on the voltage drop of the standard current on the resistor. Therefore, the solution formula is obtained:

[0050]

[0051] 100≤800-R5×14≤680 (1-4)

[0052] 100≤800-R5×16≤680 (1-5)

[0053] 100≤350-R5×2×3.5≤680 (1-6)

[0054] R5=R6 (1-7)

[0055] By combining the seven equations, this embodiment selects R3≈1.5R1 and calculates a matching solution:

[0056] R1=R2=82ohm

[0057] R3=R4=120ohm

[0058] R5=R6=22ohm

[0059] See also Figure 4 , which is the key circuit diagram of the optical module interface package of this embodiment, considering that the signal sending interface is LVDS, and the GPON optical module TX receiving end usually has integrated AC coupling and 100 ohm differential impedance, it is only necessary to perform 100 ohm differential impedance matching on the LVDS output interface to meet the signal matching requirements of the ordinary optical module and the GPON optical module for the TX receiving end. This can ensure good matching during signal transmission and improve system performance and stability.

[0060] See also Figure 3 , is the key circuit diagram of the optical module interface package of this embodiment. Pins 4 and 5 of FPGA are the IIC (Inter-Integrated Circuit) interface of the optical module. When the optical module is in place, FPGA can read the relevant information of the optical module through the IIC interface. For example, by the wavelength of the optical signal, FPGA can distinguish whether the optical module in place is a GPON OLT, so as to choose whether to enable RX_Reset of pin 7. In the present invention, since the supporting MAC of GPON is not used, the physical layer of the GPON network is mainly used.

[0061] Based on the above design process, the technical solution of this embodiment is: an optical module interface circuit, including:

[0062] A first resistor and a second resistor, wherein one end of the first resistor is connected to the first LVDS interface and the other end is grounded, and one end of the second resistor is connected to the second LVDS interface and the other end is grounded;

[0063] A fifth resistor and a sixth resistor, wherein the fifth resistor is connected to the first LVDS interface, and the sixth resistor is connected to the second LVDS interface.

[0064] Preferably, it also includes a third resistor, a fourth resistor and a 3.3V DC power supply, one end of the third resistor is connected to the 3.3V DC power supply, and the other end is connected to the second end of the fifth resistor, and one end of the fourth resistor is connected to the 3.3V DC power supply, and the other end is connected to the second end of the sixth resistor.

[0065] Preferably, the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor satisfy the following relationship:

[0066]

[0067] 100≤800-R5×14≤680

[0068] 100≤800-R5×16≤680

[0069] 100≤350-R5×2×3.5≤680

[0070] R5=R6.

[0071] The technical solution enables the signal matching circuit at the receiving end of the optical module interface to meet the signal range requirements of the GPON module and the ordinary optical module at the same time, limits the resistance value of each resistor in the matching circuit, the mutual matching between various high-speed logic levels, and the partial replacement of the integrated chip for the GPON MAC, so that it can be compatible with GPON OLT, GPONONU and ordinary optical modules at the same time. The interface design can realize pluggable function. Users can choose to insert the GPON module to connect to the ODN network to realize GPON communication, or insert the ordinary optical module to realize point-to-point communication, which greatly simplifies the hardware cost of the system equipment and improves the flexibility and versatility of the product.

[0072] Preferably, a difference between a ratio of the resistance values ​​of the third resistor to the first resistor and 1.5 satisfies a preset threshold.

[0073] Preferably, the resistance values ​​of the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor are respectively:

[0074] R1=R2=82ohm.

[0075] R3=R4=120ohm

[0076] R5=R6=22ohm

[0077] Second embodiment

[0078] Based on the same concept, the present invention further provides a communication system, comprising any one of the optical module interface circuits described above.

[0079] This embodiment can support point-to-multipoint GPON communication through ODN network and GPON optical module, and can also realize conventional point-to-point optical port communication through optical fiber and ordinary optical module, realizing flexible switching between multipoint communication and point-to-point communication. Through the combination of LVDS, several GPIOs and peripheral matching circuits, the interface realizes unconventional GPON usage method, without the need for additional GPON MAC, greatly improving the flexibility of optical port design and node topology. Especially in the application scenario where ordinary optical modules need to be upgraded to GPON compatible, the design advantage is significant. This innovation brings a more convenient and efficient solution to the field of optical communication, showing great potential in the development of future communication technology.

[0080] Since the application of SFP optical modules does not require too much logic control, the present invention mainly introduces the implementation method of GPON communication. For the use of GPON network, the following points are mainly concerned:

[0081] Reset mechanism: The reset of the optical network terminal mainly involves two key control pins, RX_RESET and SINAL_DETECT (SD for short). Since the data upload mode of the optical network unit is burst, the optical network terminal is required to be in a signal receiving ready state at all times, so the first reset mechanism is introduced: the timeout reset mechanism. The specific implementation method of the timeout reset is: monitor SD, and when SD does not flip for a long time, perform a reset. There are three advantages to doing this. First, when there is no input signal, the optical network terminal can always remain in a signal receiving ready state; second, no matter when the input signal is generated, the reset signal will not affect the key data reception of the input signal (this feature is only valid for data packets with preamble codes. In the absence of preamble codes, if the reset signal and the input data packet are generated at the same time, data loss within the reset time may occur); third, this method can handle the continuous high pull-up of SD caused by data anomalies or noise.

[0082] The second reset mechanism is the receiving reset mechanism. The specific implementation method is: when SD flip is detected, a reset is actively performed. According to the optical network terminal manual, a reset is required before and after the data packet. Therefore, when a data packet is received, SD is pulled high, and a reset is performed at this time; when the data packet is received, SD is pulled low, and the optical network terminal is reset again. Under this mechanism, the data packet is required to have a leading code segment, otherwise it may cause partial data loss.

[0083] Default level: On the data link where the optical network unit sends and the optical network terminal receives, since the data uploading mode of the optical network unit is burst, the optical network unit transmitter is required to remain in a static state when not sending packets, that is, the bus is at a stable level, so there is no need to perform special processing on the static optical network unit transmitter. On the other hand, since the logic device interface type corresponding to the optical network terminal receiver is LVDS, and the LVDS bus remains long 0, it may cause abnormalities, so it is necessary to perform data reverse processing on the internal logic, so that the optical network terminal receiver is in a long 1 state in a static state.

[0084] In the data link sent by the optical network terminal and received by the optical network unit, it was found through actual measurement that if the bus has maintained a long 0 or a long 1 for a long time, it may cause the CDR of the optical network unit receiving port to shift and fail to receive data packets normally. Therefore, the optical network terminal is required to emit a continuous deflection level in static state.

[0085] Communication protocol: In conventional GPON communication, the frame structures of upstream data and downstream data are different. Taking the downstream frame as an example, in addition to the data itself, it also has structures such as Psync (frame synchronization), Ident (frame counter), PLOAMd (line alarm and monitoring design) and GTC header, making the overall data packet relatively bloated.

[0086] In the design of this case, token scheduling is selected as the communication scheduling method of the system. First, the dial code is set on each node in the hardware, and each node has a unique identification number through different dial codes. It has been mentioned in the previous description that the data frame needs to use a preamble, and the length of the preamble segment should be less than the reset signal. In addition to the preamble, a token packet is required in the data frame. When a node sends a data frame outward, all nodes on the bus can receive the data frame. At this time, each node compares the identification number in the data frame with its own identification number. If the comparison is successful, the node replies with the data, otherwise the data will be lost. Other frame structures can be customized according to the user.

[0087] Preferably, it further comprises an FPGA, wherein the fifth resistor of the optical module interface circuit is connected to the first LVDS interface of the FPGA, the sixth resistor of the optical module interface circuit is connected to the second LVDS interface of the FPGA, and the FPGA is configured to introduce a timeout reset mechanism and a reception reset mechanism;

[0088] The timeout reset mechanism is: monitoring SD, and when SD does not flip over for a preset time, a reset is performed;

[0089] The receiving reset mechanism is: when SD flip is detected, a reset is actively performed.

[0090] Preferably, when the optical module is in place, the IIC interface of the fourth and fifth pins of the FPGA reads the optical signal wavelength information of the optical module in place to determine whether the optical module in place is a GPON optical network terminal, and then determines whether to enable RX_Reset of the seventh pin of the FPGA according to a preset mechanism.

[0091] To meet the needs of GPON optical network terminals, a GPIO port is added to connect to pin 7 of the optical module (used as RX_Reset in the optical network terminal optical module to control the receive reset signal input of the optical network terminal).

[0092] Preferably, the GPON optical module in the communication system is directly connected to the processor chip, so that only the physical layer thereof is applied to the topology;

[0093] On the data link where the optical network unit sends and the optical network terminal receives, the optical network unit sending end is configured to remain in a static state when no packet is sent, and the bus is at a stable level.

[0094] It can eliminate the increased cost caused by the use of GPON MAC. It can also unify the hardware corresponding to the optical network terminal, optical network unit and ordinary optical module, thus avoiding the appearance of multiple sets of hardware in one system, thereby reducing development and maintenance costs. Integrated chips with logic processing functions such as MCU or FPGA or CPU or even CPLD are used as GPON MAC, not just FPGA. This article only uses FPGA as an example to realize the control of GPON optical module. Since this part occupies less resources, this chip can usually be used as a processing module for optical port signals at the same time, realizing the unification of MAC and main chip platform.

[0095] Preferably, the communication system is connected in a star topology via an ODN network.

[0096] Preferably, token scheduling is selected as the communication scheduling mode of the communication system, and a dial code is set on each node in hardware. Each node has a unique identification number through different dial codes. The data frame includes a preamble and a token packet. The length of the preamble segment is less than the reset signal. When a node sends a data frame to the outside, all nodes on the bus can receive the data frame. Each node compares the identification number in the data frame with its own identification number. If the comparison is successful, the node replies with the data, otherwise the data will be lost.

[0097] The advantage is that a star topology can be realized, so there is no need to worry about the impact of the loss of a single node on the entire system; at the same time, the present invention can significantly reduce development and maintenance costs through the ODN network.

[0098] Those skilled in the art can clearly understand that, for the sake of convenience and brevity in description, the identification content specifically executed by the above-described system and device can refer to the corresponding process in the aforementioned method embodiment.

[0099] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they still fall within the protection scope of the present invention.

Claims

1. An optical module interface circuit, characterized in that: include: A first resistor and a second resistor, wherein one end of the first resistor is connected to the first LVDS interface and the other end is grounded, and one end of the second resistor is connected to the second LVDS interface and the other end is grounded; A fifth resistor and a sixth resistor, wherein the fifth resistor is connected to the first LVDS interface, and the sixth resistor is connected to the second LVDS interface.

2. The optical module interface circuit according to claim 1, characterized in that: It also includes a third resistor, a fourth resistor and a 3.3V DC power supply, one end of the third resistor is connected to the 3.3V DC power supply, and the other end is connected to the second end of the fifth resistor, one end of the fourth resistor is connected to the 3.3V DC power supply, and the other end is connected to the second end of the sixth resistor.

3. The optical module interface circuit according to claim 2, characterized in that: The first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor satisfy the following relationship: 100≤800-R5×14≤680 100≤800-R5×16≤680 100≤350-R5×2×3.5≤680 R5=R6.

4. The optical module interface circuit according to claim 2 or 3, characterized in that: The difference between the ratio of the resistance values ​​of the third resistor to the first resistor and 1.5 satisfies a preset threshold.

5. The optical module interface circuit according to claim 4, characterized in that: The resistance values ​​of the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor are respectively: R1=R2=82ohm. R3=R4=120ohm R5=R6=22ohm 6. A communication system, characterized in that: The optical module interface circuit comprises any one of claims 1 to 5.

7. The communication system according to claim 6, characterized in that: Also includes an FPGA, the fifth resistor of the optical module interface circuit is connected to the first LVDS interface of the FPGA, the sixth resistor of the optical module interface circuit is connected to the second LVDS interface of the FPGA, and the FPGA is configured to introduce a timeout reset mechanism and a reception reset mechanism; The timeout reset mechanism is: monitoring SD, and when SD does not flip over for a preset time, a reset is performed; The receiving reset mechanism is: when SD flip is detected, a reset is actively performed.

8. The communication system according to claim 7, characterized in that: When the optical module is in place, the IIC interface of the fourth and fifth pins of the FPGA reads the optical signal wavelength information of the optical module in place to determine whether the optical module in place is a GPON OLT, and then determines whether to enable RX_Reset of the seventh pin of the FPGA according to a preset mechanism.

9. The communication system according to claim 8, characterized in that: In the communication system, the GPON optical module is directly connected to the processor chip, so that only the physical layer thereof is applied to the topology; On the data link where the optical network unit sends and the optical network terminal receives, the optical network unit sending end is configured to remain in a static state when no packet is sent, and the bus is at a stable level.

10. The communication system according to claim 8, characterized in that: The communication scheduling method of the communication system selects token scheduling, and sets dial codes on each node in hardware. Through different dial code methods, each node has a unique identification number. The data frame includes a preamble and a token packet. The length of the preamble segment is less than the reset signal. When a node sends a data frame to the outside, all nodes on the bus can receive the data frame. Each node compares the identification number in the data frame with its own identification number. If the comparison is successful, the node replies with the data, otherwise the data will be lost.

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