Photoelectric synapse transistor capable of programming wide spectrum under ferroelectric modulation and preparation method thereof

Abstract

The invention discloses a photoelectric synapse transistor with wide spectral response and a manufacturing method thereof, and mainly solves the problems that the conductivity and the response rate of the existing photoelectric synapse transistor are difficult to linearly regulate and control at the same time and the light response wave band is narrow. The device comprises a substrate layer, an ultraviolet light channel layer, a source electrode, a drain electrode, a visible light channel layer and a grid electrode from bottom to top, and a ferroelectric medium layer is arranged on the upper portion of the visible light channel layer and used for changing the polarization state to change the doping state of the visible light channel layer, so that the device has multiple working states; the grid electrode is located on the ferroelectric dielectric layer in parallel so as to regulate and control the polarization state of the ferroelectric dielectric layer; the source electrode and the drain electrode are located between the ultraviolet light channel layer and the visible light channel layer. When the visible light irradiates the visible light channel layer or the ultraviolet light irradiates the ultraviolet light channel layer, the light signal is responded and the light current is transmitted. The photosynaptic transistor can widen the photoresponse wave band of the photosynaptic transistor, realizes linear regulation and control of the conductivity and the response rate of the device, and can be used for a photoelectric detector and a neural calculator.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a photoelectric synapse transistor and a preparation method thereof, which can be used for a photoelectric detector. Background Art

[0002] With the booming development and continuous progress of artificial intelligence and the Internet of Things, the data and information that need to be processed have emerged in an explosive manner. The traditional von Neumann architecture separates sensors, memory and computing units. Due to the physical separation between processing and storage units, this configuration is difficult to handle parallel or complex situations, such as real-time processing. So people turned their attention to the human brain. As a natural biological supercomputer, the human brain can perform multiple functions at the same time, such as recognition, learning and calculation. Therefore, based on the human brain, neuron-like computing has been extended. Neuron-like computing inherits the high computing efficiency and low power consumption of human brain computing, and has great potential to break through the limitations of von Neumann configuration. The basic unit of the neuromorphic system is the synapse. The current synapses are mainly divided into two categories: electrical stimulation and optical stimulation. The artificial synapses proposed earlier for electrical stimulation will produce resistance-capacitance delay and power loss due to the connection of metal wires. In contrast, optoelectronic artificial synapses have good input bandwidth, improve signal processing rate, and improve power utilization efficiency.

[0003] In order to realize data calculation, linear regulation of synaptic weights is of great significance. For photoelectric synapses, synaptic weights are usually expressed as response rates, and changes in artificial synaptic weights that rely on electrical stimulation depend on changes in conductance. In addition, the response frequency of photoelectric synapses is also an important parameter. The wider the response spectrum of the photoelectric synapse, the wider its application range and the broader its application prospects. Two-dimensional van der Waals heterostructures have gradually become ideal materials for the development of wide-spectrum photoelectric synaptic devices due to their versatility, adjustability and photosensitivity. At present, most photoelectric synaptic devices based on two-dimensional materials exhibit excellent light response in the visible to infrared band, while the light response in the ultraviolet spectrum has been relatively less studied.

[0004] Patent document with application number CN202410236568 discloses a multi-sensory ferroelectric semiconductor synaptic device for neuromorphic computing, and its preparation method and application. The photoelectric synaptic transistor device prepared by the device has the function of realizing non-volatile linear adjustment of the neural network weights of conductance and response rate, which solves the problem of preparation difficulties in the prior art, inability to obtain intermediate state information of conductance and response rate, and thus inability to be used for neuromorphic computing. However, since it only introduces one gate, it cannot further regulate the ferroelectric dielectric layer, and the working state is relatively single. Moreover, since it has only a single optical channel, the width of its response spectrum is narrow.

[0005] The patent document with application number CN202410013416 discloses a photosynaptic transistor with a wide spectrum response and a method for making the same. The photosynaptic transistor prepared by the method broadens the light response band of the device. At the same time, the two semiconductors form a heterojunction, simulating the synaptic characteristics of the photosynaptic transistor under the wide spectrum of ultraviolet, visible, near-infrared and mid-infrared light, and expanding the application range of the photosynaptic transistor. However, the problem of linear regulation of synaptic weights is not reflected, that is, if the applied light signal is doubled, the increase in photocurrent may not be doubled. This nonlinear regulation makes it difficult to flexibly control the strength of signal transmission, which in turn affects the learning and memory process of the neural network. Summary of the invention

[0006] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and propose a photoelectric synaptic transistor with programmable wide spectrum under ferroelectric modulation and a preparation method, so as to realize linear adjustable synaptic weight and simultaneously regulate the conductance and photoresponse rate of the device, thereby improving the flexibility of precisely programming neuromorphic devices and widening the photoresponse band of the photoelectric synaptic transistor.

[0007] The technical solutions for achieving the purpose of the present invention include the following:

[0008] 1. A photoelectric synaptic transistor with a wide spectrum response, comprising from bottom to top: a substrate layer, an ultraviolet light channel layer, a source and a drain, a visible light channel layer, and a gate. When visible light irradiates the visible light channel layer or the ultraviolet light channel layer, a large number of photogenerated carriers will be generated to achieve a response to an optical signal, characterized in that:

[0009] A ferroelectric dielectric layer is provided on the upper portion of the visible light channel layer, which is used to change the polarization state, realize the change of the doping state of the visible light channel layer, and enable the device to have multiple working states;

[0010] The gates are provided in two numbers and are located in parallel on the ferroelectric dielectric layer to achieve regulation of the polarization state of the ferroelectric dielectric layer;

[0011] The source electrode and the drain electrode are located between the ultraviolet light channel layer and the visible light channel layer to realize the transmission of photocurrent.

[0012] Furthermore, the ferroelectric dielectric layer is made of polyvinylidene fluoride-trifluoroethylene P (VDF-TrFE) or lithium niobate (LiNbO 3 ) and has a thickness of 20 to 500 nm.

[0013] Furthermore, the substrate layer is made of Si material or sapphire material with a thickness of 50 μm to 500 μm.

[0014] Furthermore, the ultraviolet light channel layer is made of GaN, Ga 2 O 3, AlGaN, with a thickness of 50nm to 300nm; the visible light channel layer is made of WSe 2, 、MoSe 2 、MoS 2 Any one of which has a thickness of 4nm to 12nm.

[0015] Furthermore, the source and drain electrodes are made of Ti / Al / Ni / Au with a thickness of 10nm-80nm / 10nm-60nm / 20nm-120nm / 10nm-200nm or Ti / Au with a thickness of 10nm-80nm / 70nm-200nm; the two gate electrodes (7) are both made of Ni / Au with a thickness of 20nm-80nm / 60nm-300nm, and the distance between the two is 2μm-5μm.

[0016] 2. A method for preparing a photosynaptic transistor with programmable wide spectrum under ferroelectric modulation, characterized in that it comprises the following steps:

[0017] S1: growing a UV channel layer on a substrate by metal organic chemical vapor deposition (MOCVD);

[0018] S2: Deposit source and drain electrodes on the UV channel layer by photolithography, electron beam evaporation and lift-off technology, and transfer multilayer WSe on top of the source and drain electrodes by a two-dimensional material transfer platform. 2 Materials, forming a visible light channel layer;

[0019] S3: adding a ferroelectric dielectric layer on the visible light channel layer by spin coating process;

[0020] S4: The device is fabricated by depositing two parallel metal electrodes as gate electrodes on the ferroelectric dielectric layer using photolithography, electron beam evaporation and lift-off techniques.

[0021] Compared with the existing invention, the present invention has the following advantages:

[0022] 1) Since two gates are added to the ferroelectric dielectric layer, the polarization state on both sides of the ferroelectric dielectric layer can be modulated by controlling the gate voltage.

[0023] Different polarization states can change the doping type and doping concentration of the visible light channel layer under the gate to form PN junctions, NP junctions, or NN and PP junctions with different doping concentrations. Therefore, the device can achieve four working states by programming and changing the gate voltage.

[0024] Since the polarization state can be maintained, the gate voltage can be removed after the PN junction / NP junction is formed to achieve self-powered mode. After applying light stimulation, current will be generated through the photoelectric effect without applying source and drain voltages.

[0025] Since the built-in electric fields of the PN junction and the NP junction have different directions, bidirectional current can be achieved. Therefore, the enhancement and inhibition states of the photoelectric synapse can be controlled by controlling the gate voltage.

[0026] 2) Since the present invention introduces a ferroelectric dielectric layer, the conductivity and response rate of the photoelectric synapse device can be linearly modulated.

[0027] Since the polarization direction of ferroelectric materials has multiple intermediate levels between the completely "up" and "down" states, it helps to precisely control the doping level and reversible electronic behavior of atomically thin 2D materials, improve the flexibility and tunability of precisely programming neuromorphic devices, and achieve superlinear and discrete multiple weights.

[0028] 3) The present invention can realize photocurrent transmission under different light responses by placing the source and drain electrodes in the middle of the vertical stacking structure of the ultraviolet light channel layer and the visible light channel. That is, when visible light and ultraviolet light are irradiated, the photogenerated carriers generated can directly transmit the carriers through the contacting source and drain electrodes without passing through other channel layers.

[0029] 4) The present invention adopts a mechanical transfer method to transfer two-dimensional materials, and the thickness requirement of the two-dimensional materials is not high, that is, the two-dimensional materials can be transferred when the thickness is 4-12nm, which lowers the threshold of device preparation and makes it universal.

[0030] 5) The present invention can replace the material of the ultraviolet light channel layer according to the requirements of the response light wavelength, and replace the material of the ferroelectric dielectric layer according to the requirements of transmittance and cost, thereby increasing the flexibility of the device.

[0031] 6) The present invention adopts a spin coating method to prepare a ferroelectric dielectric layer, which has a simple process and low cost, and the formed film has high uniformity and the film thickness can be adjusted by adjusting the spin coating speed. The spin coating method adopts a low temperature annealing process, which helps to protect the base material and its device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the structure of a photoelectric synaptic transistor with programmable wide spectrum under ferroelectric modulation of the present invention;

[0033] Figure 2 The invention is made Figure 1 Schematic diagram of the device process flow. DETAILED DESCRIPTION

[0034] The present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0035] Reference Figure 1The ferroelectric modulation programmable wide spectrum photosynaptic transistor of the present invention comprises a top gate 6, a ferroelectric dielectric layer 5, a visible light channel layer 4, an ultraviolet light channel layer 2, a substrate 1, a source 3S, and a drain 3D. Among them:

[0036] The substrate 1 is made of Si or sapphire with a thickness of 50 μm to 500 μm.

[0037] The ultraviolet light channel layer 2 is made of GaN, Ga 2 O 3 Or any one of AlGaN, with a thickness of 50nm to 300nm, which is located on the substrate 1.

[0038] The visible light channel layer 4 is made of WSe 2 ,、MoSe 2 、MoS 2 Any one of the above, with a thickness of 4nm to 12nm, which is located on the ultraviolet light channel layer 2.

[0039] The ferroelectric dielectric layer 5 is made of polyvinylidene fluoride-trifluoroethylene P (VDF-TrFE) or LiNbO 3 In any one of the above, the thickness is 20nm to 500nm, and it is located on the visible light channel layer 4.

[0040] The source electrode 3S is made of Ti / Al / Ni / Au with a thickness of 10nm-80nm / 10nm-60nm / 20nm-120nm / 10nm-200nm, or Ti / Au with a thickness of 10nm-80nm / 70nm-200nm, and is located on the ultraviolet channel layer 2;

[0041] The drain electrode 3D is made of Ti / Al / Ni / Au with a thickness of 10nm-80nm / 10nm-60nm / 20nm-120nm / 10nm-200nm, or Ti / Au with a thickness of 10nm-80nm / 70nm-200nm, and is located on the ultraviolet channel layer 2;

[0042] The gate 6 is made of Ni / Au with a thickness of 20 nm to 80 nm / 60 nm to 300 nm, with a spacing of 2 μm to 5 μm, and is located on the ferroelectric dielectric layer 5 .

[0043] Reference Figure 2 The present invention provides the following three examples, but the embodiments of the present invention are not limited thereto. The experimental methods described in the following examples are conventional methods unless otherwise specified; the reagents and materials described are commercially available unless otherwise specified.

[0044] Example 1: The material of the ferroelectric dielectric layer made on the Si substrate with a thickness of 50 μm is polyvinylidene fluoride-trifluoroethylene P

[0045] (VDF-TrFE), thickness is 300nm, and the visible light channel layer uses WSe 2 , with a thickness of 4nm and an ultraviolet light channel layer of AlGaN with a thickness of 2μm, a programmable wide-spectrum photosynaptic transistor.

[0046] Step 1: epitaxially depositing a group III nitride material on the front side of the Si substrate 1 to form an ultraviolet light channel layer 2, such as Figure 2 (a).

[0047] Using metal organic chemical vapor deposition (MOCVD) technology, 3 Under the process conditions of a flow rate ratio of 1000 to TMAl, a temperature of 450° C., and a growth pressure of 50 mbar, an AlN buffer layer with a thickness of 1 μm is epitaxially grown on a Si substrate 1 with a thickness of 50 μm;

[0048] AlGaN UV channel layer deposited on AlN 2:

[0049] Using metal organic chemical vapor deposition MOCVD technology, including but not limited to: NH 3 Under the process conditions that the flow rate ratio of NH4O2 to TMGa is 1000, the flow rate ratio of TMGa to TMAl is 4, the temperature is 800°C, and the growth pressure is 50 mbar, an AlGaN ultraviolet channel layer 2 with an Al component of 0.25 and a thickness of 1 μm is epitaxially grown on AlN, wherein the NH 3 The flow rate ratio of the gas and the TMGa gas can be selected in the range of 1000 to 2000 according to actual needs, and the flow rate ratio of the TMGa gas and the TMAl gas can also be selected in the range of 4 to 20 according to actual needs.

[0050] Step 2: Deposit the source electrode 3S and the drain electrode 3D on the surface of the AlGaN ultraviolet channel layer 2, such as Figure 2 (b).

[0051] 2.1) The surface of the AlGaN ultraviolet channel layer 2 is photolithographically processed, i.e., a layer of photoresist is first coated on the AlGaN ultraviolet channel layer 2, and then alignment, exposure, development, and pattern detection are sequentially performed to form the source and drain regions of the device; and then the source and drain regions are bombarded with oxygen plasma for 3 minutes to reduce the ohmic contact resistance of the source and drain regions;

[0052] 2.2) Through electron beam evaporation E-Beam, the vacuum in the working room is evacuated to 2.0×10 -4Under the process conditions of 1000 Pa, 100 kV electron gun acceleration voltage, 100 mA electron gun beam current, and 210 s evaporation time, Ti / Al / Ni / Au with a thickness of 50 / 40 / 100 / 20 nm is deposited in the source and drain regions as the source 3S and the drain 3D, and then the wafer is placed in a photoresist stripping solution to remove the photoresist;

[0053] 2.3) Place the wafer with the source and drain metal deposited in an annealing furnace at 800°C N 2 Rapid annealing is performed in the atmosphere for 50 seconds to form high-quality ohmic contacts at the contact surfaces of the source and drain metals and the AlGaN ultraviolet channel layer 2 .

[0054] Step 3: Via WSe 2 The wafer is transferred to form a visible light channel layer 4 on the AlGaN ultraviolet light channel layer 2 and the source and drain electrodes, such as Figure 2 (c).

[0055] 3.1) Get the existing WSe 2 wafer and mechanically peeled off the WSe using repeated tape peeling 2 Wafer obtained with multilayer WSe bonded to tape 2 Thin slices;

[0056] 3.2) Glue polydimethylsiloxane (PDMS) to a glass slide and attach it to tape. 2 The thin film was transferred to PDMS and then clamped with WSe 2 Thin PDMS glass slide;

[0057] 3.3) Place the sample obtained in step 2 on the stage of the two-dimensional material transfer platform, and use the two-dimensional material transfer platform to transfer the WSe on the PDMS. 2 The sheet is aligned with the sample source 3S and drain 3D, and then the slide is lowered to allow the WSe on the PDMS to 2 The thin film was placed in contact with the sample and allowed to stand for 5 min to allow the WSe 2 The wafer is separated from the PDMS and adhered to the AlGaN ultraviolet light channel layer 2 below the source and drain electrodes to form a visible light channel layer 4 .

[0058] Step 4: Spin-coat the ferroelectric dielectric layer 5 polyvinylidene fluoride-trifluoroethylene P (VDF-TrFE) on the visible light channel layer 4 by a spin coating process and perform annealing, such as Figure 2 (d).

[0059] 4.1) Place the sample on the tray of the coating machine, drop polyvinylidene fluoride-trifluoroethylene P (VDF-TrFE) on the visible light channel layer 4, turn on the coating machine to spin-coat polyvinylidene fluoride-trifluoroethylene P (VDF-TrFE) on the visible light channel layer 4 to form a thin film. The process conditions are:

[0060] The glue spinner first spins at a low speed of 500r / s for 3s;

[0061] Then spin coating is performed at a high speed of 2800 r / s for 25 seconds to complete the spin coating;

[0062] 4.2) The thin film-formed sample was annealed at 135° C. for 4 h.

[0063] Step 5: Deposit a gate 6 on the ferroelectric dielectric layer 5, such as Figure 2 (e).

[0064] 5.1) The surface of the ferroelectric dielectric layer 5 is again photolithographically formed into a gate region, and the vacuum is evacuated to 2.0×10 -4 Under the process conditions of 8 kV electron gun acceleration voltage, 1000 mA electron gun beam current and 120 s evaporation time, Ni / Au with a spacing of 2 μm and a thickness of 20 nm / 60 nm is deposited in the gate region as the gate 6 to form a Schottky contact at the contact surface of the gate metal and the ferroelectric dielectric layer 5;

[0065] 5.2) The wafer with the gate electrode 6 deposited thereon is placed in a photoresist stripping solution to remove the photoresist, thereby completing the device preparation.

[0066] Example 2: The material of the ferroelectric dielectric layer made on a Si substrate with a thickness of 300 μm is LiNbO 3 , thickness is 200nm, visible light channel layer 4 is made of MoSe 2 Any one of the above, with a thickness of 8nm, and the ultraviolet channel layer 2 is GaN with a thickness of 3

[0067] μm programmable broad-spectrum photosynaptic transistor.

[0068] Step 1: epitaxially depositing a III-nitride material on the front surface of the Si substrate 1 to form an ultraviolet light channel 2, such as Figure 2 (a).

[0069] Using metal organic chemical vapor deposition MOCVD technology, set NH 3 Under the process conditions of a flow rate ratio of 3000 to TMAl, a temperature of 750° C., and a growth pressure of 250 mbar, an AlN buffer layer with a thickness of 0.2 μm is epitaxially grown on the front side of a Si substrate 1 with a thickness of 300 μm;

[0070] Using metal organic chemical vapor deposition MOCVD technology, the settings include but are not limited to NH 3 A GaN trench ultraviolet channel layer 2 with a thickness of 3 μm is epitaxially grown on AlN under the process conditions of a flow rate ratio of 2000 to TMGa, a temperature of 1000°C, and a growth pressure of 150 mbar. 3 The flow rate ratio can be selected between 1500 and 2500.

[0071] Step 2: Deposit source 3S and drain 3D metal electrodes on the surface of the GaN trench ultraviolet channel layer 2, such as Figure 2 (b).

[0072] The surface of the GaN groove ultraviolet channel layer 2 is photolithographically processed, that is, a layer of photoresist is first coated on the GaN groove ultraviolet channel layer 2, and then alignment, exposure, development, and pattern detection are sequentially performed to form the source and drain regions of the device, and then the source and drain regions are bombarded with oxygen plasma for 3 minutes to reduce the ohmic contact resistance of the source and drain regions;

[0073] The chamber was evacuated to a vacuum of 2.0 × 10 -5 Pa, the electron gun acceleration voltage is 7Kv, the electron gun beam current is 60mA, and the evaporation time is 180s. Ti / Al / Ni / Au with a thickness of 20 / 40 / 100 / 20nm is deposited in the source and drain regions as the source 3S and the drain 3D, and then the wafer is placed in a photoresist stripping solution to remove the photoresist;

[0074] The wafer with the source and drain metal deposited is placed in an annealing furnace at N 2 Rapid annealing is performed at 800° C. for 50 seconds in an atmosphere to form high-quality ohmic contacts at the contact surfaces of the source and drain metals and the GaN trench ultraviolet channel layer 2 .

[0075] Step 3: Through MoSe 2 The wafer is transferred to form a visible light channel layer 4 on the GaN ultraviolet light channel layer 2 and the source and drain electrodes, such as Figure 2 (c).

[0076] Get an existing MoSe 2 wafer, and mechanical exfoliation from MoSe using repeated tape peeling 2 Wafer obtained with multilayer MoSe bonded to tape 2 Thin slices;

[0077] Glue polydimethylsiloxane (PDMS) to a glass slide and attach it to tape, then place MoSe on the tape. 2 The thin film was transferred to PDMS and then sandwiched with MoSe 2Thin PDMS glass slide;

[0078] The sample obtained in step 2 is placed on the stage of the two-dimensional material transfer platform, and the MoSe on the PDMS is transferred using the two-dimensional material transfer platform. 2 The sheet is aligned with the sample source 3S and drain 3D, and then the slide is lowered to allow the MoSe on PDMS to 2 The flakes were placed in contact with the sample and allowed to stand for 5 min to allow the MoSe 2 The wafer is separated from the PDMS and adhered to the GaN ultraviolet light channel layer 2 below the source and drain electrodes to form a visible light channel layer 4 .

[0079] Step 4: Spin coating the ferroelectric dielectric layer 5LiNbO 3 Spin-coated on the visible light channel layer 4 and annealed, such as Figure 2 (d).

[0080] Place the sample on the coating machine tray and drop LiNbO on top of the visible light channel layer 4. 3 , turn on the glue coating machine to make LiNbO 3 Spin coating on the visible light channel layer 4 to form a thin film, the process conditions are:

[0081] The glue spinner first spins at a low speed of 1000r / s for 6s;

[0082] Then spin coating is performed at a high speed of 3000 r / s for 30 seconds to complete the spin coating;

[0083] The thin film-formed sample was annealed at 550° C. for 1 h.

[0084] Step 5: Deposit a gate 6 on the ferroelectric dielectric layer 5, such as Figure 2 (e) Device preparation is completed.

[0085] The surface of the ferroelectric dielectric layer 5 is again photolithographically formed into a gate region, and the vacuum is evacuated to 2.0×10 -5 Under the process conditions of 1000 Pa, electron gun acceleration voltage of 6 Kv, electron gun beam current of 800 mA, and evaporation time of 110 s, Ni / Au with a spacing of 5 μm and a thickness of 30 nm / 80 nm is deposited in the gate region as the gate 6 to form a Schottky contact at the contact surface of the gate metal and the ferroelectric dielectric layer 6;

[0086] The wafer with the gate electrode 6 deposited thereon is placed in a photoresist stripping solution to remove the photoresist, thereby completing the device preparation.

[0087] Example 3: A device is fabricated on a sapphire substrate with a thickness of 500 μm, and the material used to fabricate the ferroelectric dielectric layer is LiNbO 3, with a thickness of 100nm, and the visible light channel layer 4 is made of MoS 2 , thickness is 12nm, and the ultraviolet channel layer 2 is Ga 2 O 3 , 3μm thick, photosynaptic transistor.

[0088] Step A: epitaxially grow an ultraviolet light channel layer 2 on the front surface of the sapphire substrate 1, such as Figure 2 (a).

[0089] Ga was deposited on the sapphire substrate 1 2 O 3 UV channel layer 3:

[0090] Metal organic chemical vapor deposition (MOCVD) technology is used to deposit Ga with a thickness of 180 nm on the substrate insulating layer 2. 2 O 3 The process conditions of the ultraviolet light channel layer 3 include but are not limited to:

[0091] The reaction sources are triethylgallium (TEGa) and high-purity oxygen (O 2 ),

[0092] High purity Ar is used as the carrier gas for TEGa.

[0093] The temperature in the reaction chamber is maintained at 1100°C and the pressure is maintained at 200 mbar.

[0094] The flow rate ratio of oxygen to TEGa carrier gas is 100. 2 The flow rate ratio to TEGa can be 100 to 1000.

[0095] Step B: In Ga 2 O 3 The source 3S and drain 3D metal electrodes are deposited on the surface of the ultraviolet channel layer 2, such as Figure 2 (b).

[0096] B1) Ga 2 O 3 The surface of the ultraviolet channel layer 2 is photolithographically processed, that is, on the Ga 2 O 3 A layer of photoresist is first coated on the ultraviolet channel layer 2, and then alignment, exposure, development, and pattern detection are performed in sequence to form the source and drain regions of the device, and then the source and drain regions are bombarded with oxygen plasma for 3 minutes;

[0097] B2) Ti / Au with a thickness of 50 / 20 nm is deposited in the source and drain regions as the source 3S and drain 3D by electron beam evaporation E-Beam, and then the wafer is placed in a photoresist stripping solution to remove the photoresist. The evaporation process conditions are: the workroom is evacuated to 2.0×10 -7Pa, the electron gun acceleration voltage is 6Kv, the electron gun beam current is 50mA, and the evaporation time is 70s;

[0098] B3) Place the wafer with the source and drain metal deposited in an annealing furnace at N 2 The source and drain metals and Ga 2 O 3 The contact surface of the ultraviolet light channel layer 2 forms a high-quality ohmic contact.

[0099] Step C: Through MoS 2 Wafer transfer, in Ga 2 O 3 A visible light channel layer 4 is formed above the ultraviolet light channel layer 2 and the source and drain electrodes, such as Figure 2 (c).

[0100] C1) Obtaining existing MoS 2 wafers and used a mechanical exfoliation method with repeated tape peeling to remove MoS 2 Wafer obtained with tape-detached multilayer MoS 2 Thin slices;

[0101] C2) Glue polydimethylsiloxane (PDMS) to a glass slide and attach it to tape, then place the MoS 2 The thin film was transferred to PDMS and then sandwiched with MoS 2 Thin PDMS glass slide;

[0102] C3) placing the sample obtained in step B on the stage of the two-dimensional material transfer platform, and using the two-dimensional material transfer platform to transfer the MoS 2 The sheet is aligned with the sample source 3S and drain 3D, and then the slide is lowered to allow the MoS on PDMS to 2 The flakes were placed in contact with the sample and allowed to stand for 5 min to allow the MoS 2 The wafer is released from the PDMS and the Ga 2 O 3 The ultraviolet light channel layers 2 are adhered together to form a visible light channel layer 4 .

[0103] Step D: Spin coating the ferroelectric dielectric layer 5LiNbO 3 Spin-coated on the visible light channel layer 4 and annealed, such as Figure 2 (d).

[0104] Place the sample on the coating machine tray and drop LiNbO on top of the visible light channel layer 4. 3 , turn on the glue coating machine to make LiNbO 3Spin coating on the visible light channel layer 4 to form a thin film, the process conditions are:

[0105] The glue spinner first spins at a low speed of 800r / s for 5s;

[0106] Then spin coating is performed at a high speed of 2900 r / s for 28 seconds to complete the spin coating;

[0107] The thin film-formed sample was annealed at 550° C. for 1 h.

[0108] Step E: Depositing a gate 6 on the ferroelectric dielectric layer 5, such as Figure 2 (e).

[0109] 5.1) The surface of the ferroelectric dielectric layer 5 is again photolithographically formed into a gate region, and the vacuum is evacuated to 2.0×10 -7 Under the process conditions of 5 kV electron gun acceleration voltage, 50 mA electron gun beam current and 100 s evaporation time, Ni / Au with a spacing of 4 μm and a thickness of 30 nm / 70 nm is deposited in the gate region as the gate 6 to form a Schottky contact at the contact surface between the gate metal and the ferroelectric dielectric layer 5;

[0110] 5.2) The wafer with the gate electrode 6 deposited thereon is placed in a photoresist stripping solution to remove the photoresist, thereby completing the device preparation.

[0111] The above descriptions are only several specific examples of the present invention and do not constitute any limitation to the present invention. Obviously, after understanding the content and principle of the present invention, professionals in this field may make various modifications and changes in form and details without departing from the principle and structure of the present invention. 3 In addition, other ferroelectric materials with good light transmittance and compatible with CMOS process can also be used; in addition to WSe in this example, the visible light channel layer 2 、MoSe 2 、MoS 2 In addition, other materials with high visible light response rate and changeable doping type under electric field modulation can also be used; in addition to GaN and Ga 2 O 3 In addition to AlGaN, other materials with high ultraviolet light response rate and compatible with CMOS process can also be used. However, these modifications and changes based on the concept of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A photoelectric synaptic transistor with a wide spectrum response, comprising from bottom to top: a substrate layer (1), an ultraviolet light channel layer (2), a source electrode (3S) and a drain electrode (3D), a visible light channel layer (4), and a gate electrode (6). When visible light irradiates the visible light channel layer (4) or the ultraviolet light channel layer (2), a large number of photogenerated carriers will be generated to achieve a response to a light signal, characterized in that: A ferroelectric dielectric layer (5) is provided on the upper part of the visible light channel layer (4) for changing the polarization state, thereby changing the doping state of the visible light channel layer (4) and enabling the device to have multiple working states; The gates (6) are provided in two numbers and are located in parallel on the ferroelectric dielectric layer (5) to achieve regulation of the polarization state of the ferroelectric dielectric layer; The source electrode (3S) and the drain electrode (3D) are located between the ultraviolet light channel layer (2) and the visible light channel layer (4) to realize the transmission of photocurrent.

2. The device according to claim 1, characterized in that: The ferroelectric dielectric layer (5) is made of one of polyvinylidene fluoride-trifluoroethylene P (VDF-TrFE) or lithium niobate (LiNbO3), and has a thickness of 20nm to 500nm.

3. The device according to claim 1, characterized in that: The substrate layer (1) is made of Si material or sapphire with a thickness of 50 μm to 500 μm.

4. The device according to claim 1, characterized in that: The ultraviolet light channel layer (2) is made of any one of GaN, Ga2O3, and AlGaN, and has a thickness of 50nm to 300nm; The visible light channel layer (4) is made of any one of WSe2, MoSe2, and MoS2, and has a thickness of 4 nm to 12 nm.

5. The device according to claim 1, characterized in that: The source electrode (3S) and the drain electrode (3D) are made of Ti / Al / Ni / Au with a thickness of 10nm-80nm / 10nm-60nm / 20nm-120nm / 10nm-200nm or Ti / Au with a thickness of 10nm-80nm / 70nm-200nm; The two gates (6) are both made of Ni / Au with a thickness of 20nm-80nm / 60nm-300nm, and the distance between the two is 2μm-5μm.

6. A method for preparing a photosynaptic transistor with programmable wide spectrum under ferroelectric modulation, characterized in that: The following steps are involved: S1: growing a UV channel layer on a substrate by metal organic chemical vapor deposition (MOCVD); S2: Depositing source and drain electrodes on the ultraviolet light channel layer by photolithography, electron beam evaporation and lift-off technology, and transferring multiple layers of WSe2 material on top of the source and drain electrodes by a two-dimensional material transfer platform to form a visible light channel layer; S3: adding a ferroelectric dielectric layer on the visible light channel layer by spin coating process; S4: The device is fabricated by depositing two parallel metal electrodes as gate electrodes on the ferroelectric dielectric layer using photolithography, electron beam evaporation and lift-off techniques.

7. The method according to claim 6, characterized in that: In step S1, an ultraviolet light channel layer is grown on the substrate by metal organic chemical vapor deposition (MOCVD), and the process conditions are as follows: The deposited material is GaN or Ga2O3 or AlGaN; The deposition temperature is maintained at 800°C to 1100°C; The deposition pressure was maintained at 50 mbar to 200 mbar. For depositing GaN materials, the gases are TMGa and NH3, and the flow rate ratio between the two is 1500-2500; For depositing AlGaN material, the gases are TMGa, TMAl and NH3, the flow rate ratio of NH3 gas to TMGa gas is 1000-2000, and the flow rate ratio of TMGa gas to TMAl gas is 4-20; For depositing Ga2O3 material, the gases are O2 and TEGa, and the flow rate ratio of the two is 100-1000.

8. The method according to claim 6, characterized in that: The electron beam evaporation E-Beam in step S2 deposits the electrode on the ultraviolet channel layer, and the process conditions are as follows: The working room is evacuated to 2.0×10 -7 Pa~2.0×10 -4 Pa, The electron gun acceleration voltage is 6Kv~10Kv, The electron gun beam current is 50mA~100mA, The evaporation time is 70s to 210s.

9. The method according to claim 6, characterized in that: In step S3, a ferroelectric dielectric layer is added on the visible light channel layer by a spin coating process, which is achieved as follows: First, the ferroelectric material is drop-coated on the insulating layer of the target substrate, and the substrate is placed on a spin coating machine and spin-coated at a low speed of 500r / s-1000r / s for 3s to 6s; Then spin coating is performed at a high speed of 2800 r / s to 3000 r / s for 25 to 30 seconds to complete the spin coating.

10. The method according to claim 6, characterized in that: The electron beam evaporation E-Beam in step S4 deposits the electrode on the ultraviolet light channel layer, and the process conditions are as follows: The working room is evacuated to 2.0×10 -7 Pa~2.0×10 -4 Pa, The electron gun acceleration voltage is 5Kv~8Kv, The electron gun beam current is 50mA~1000mA, The evaporation time is 100s~120s.

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