Control circuit, source driving chip and display system

Abstract

This disclosure provides a control circuit, a source driver chip, and a display system. The control circuit includes a receiving circuit, a modulation circuit, and an output circuit, wherein: the receiving circuit is used to receive source input data, convert the source input data, and output initial output data; the modulation circuit is used to determine the refresh rate of the source input data, and when the refresh rate of the source input data is less than or equal to a preset refresh rate, it generates a flip signal and sends it to the output circuit; the output circuit is used to receive the initial output data, and during the process of converting the initial output data into target output data for output, if a flip signal is received, it performs at least once within one frame of data: chopping and polarity flipping the initial output data to obtain the target output data and outputting it; wherein, the output circuit includes at least a chopper circuit and an amplifier, and chopper polarity flipping refers to using the chopper circuit to change the polarity of the amplifier's offset.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a control circuit, a source driver chip, and a display system. Background Technology

[0002] In source driver chip design, the offset voltage of the operational amplifier is a crucial factor affecting display quality. Due to system design asymmetry and limitations in chip manufacturing processes, mismatches exist between the differential input transistors of the operational amplifier, meaning the offset voltage can only be reduced, not completely eliminated.

[0003] To further improve offset, a chopper circuit can be used to continuously switch the differential input of the operational amplifier, dynamically switching the positive and negative polarities of the offset voltage at the operational amplifier's input. This utilizes the low-pass filtering characteristics of the human eye to improve display quality. However, with the increasing application of dynamic wide refresh rates (e.g., 24Hz→165Hz), the time uniformity effect of the chopper circuit is significantly weakened at low refresh rates, leading to display abnormalities such as vertical lines and noise. Summary of the Invention

[0004] This disclosure provides a control circuit, a source driver chip, and a display system.

[0005] In a first aspect, embodiments of this disclosure provide a control circuit, including a receiving circuit, a modulation circuit, and an output circuit, wherein:

[0006] The receiving circuit is used to receive source input data, convert and process the source input data, and output initial output data.

[0007] The control circuit is used to determine the refresh rate of the source input data, and when the refresh rate of the source input data is less than or equal to a preset refresh rate, it generates a flip signal and sends it to the output circuit.

[0008] The output circuit is used to receive the initial output data, and during the process of converting the initial output data into target output data for output, if the flip signal is received, it performs at least once within a frame of data: performing chopping polarity flip on the initial output data to obtain target output data and outputting it; wherein, the output circuit includes at least a chopper circuit and an amplifier, and chopping polarity flip refers to using the chopper circuit to change the polarity of the amplifier's offset.

[0009] In some embodiments, the control circuit is further configured to receive a frame start pulse signal and determine the refresh rate of the source input data based on the frame start pulse signal.

[0010] In some embodiments, the control circuit includes a detection module and a polarity reversal module; wherein,

[0011] The detection module is configured to receive a frame start pulse signal, determine the refresh rate of the source input data based on the frame start pulse signal, and output a command signal when the refresh rate of the source input data is less than or equal to the preset refresh rate.

[0012] The polarity reversal module is used to receive the command signal and output the reversal signal under the instruction of the command signal.

[0013] In some embodiments, the control circuit further includes a storage circuit;

[0014] The receiving circuit is also used to send the initial output data to the storage circuit;

[0015] The storage circuit is used to receive and temporarily store the initial output data; and to send the initial output data to the output circuit when the refresh rate of the source input data is less than or equal to a preset refresh rate.

[0016] The output circuit is also used to receive the initial output data sent by the storage circuit, and based on the flip signal, to perform at least once within a frame of data: to chop the initial output data to flip its polarity to obtain the target output data and output it.

[0017] In some embodiments, the output circuit is configured to receive only the initial output data sent by one of the storage circuit and the receiving circuit.

[0018] In some embodiments, the output circuit is further configured to not perform chopping polarity reversal on the initial output data within the range of the one-frame data when the reversal signal is not received.

[0019] In some embodiments, the control circuit is further configured to, when the refresh rate of the source input data is less than or equal to a preset refresh rate, determine a preset flip signal corresponding to the current refresh rate as the flip signal, and send the flip signal to the output circuit; wherein, the preset flip signal represents the number of times the initial output data is chopper polarity flipped within the range of one frame of data;

[0020] The output circuit is also used to perform chopping polarity reversal on the initial output data a corresponding number of times according to the reversal signal.

[0021] In some embodiments, the voltage polarity of the target output data remains unchanged within the range of a single frame of data.

[0022] Secondly, embodiments of this disclosure provide a source driver chip, including the control circuit as described in any one of the first aspects.

[0023] Thirdly, embodiments of this disclosure provide a display system including the source driver chip as described in the second aspect.

[0024] This disclosure provides a control circuit, a source driver chip, and a display system. The control circuit includes a receiving circuit, a modulation circuit, and an output circuit. The receiving circuit receives source input data, converts the source input data, and outputs initial output data. The modulation circuit determines the refresh rate of the source input data and generates a flip signal to send to the output circuit when the refresh rate of the source input data is less than or equal to a preset refresh rate. The output circuit receives the initial output data and, during the process of converting the initial output data into target output data for output, if a flip signal is received, performs at least one operation within one frame of data: chopping and polarity reversing the initial output data to obtain the target output data and outputting it. The output circuit includes at least a chopper circuit and an amplifier; chopper polarity reversal refers to using the chopper circuit to change the polarity of the amplifier's offset.

[0025] In this way, since the control circuit can generate a flip signal when the refresh rate of the source input data is less than or equal to the preset refresh rate (i.e., at a low refresh rate), the output circuit can, according to the flip signal, flip the chopping polarity of the initial output data within a frame of data during the output of the initial output data to obtain the target output data and output it; that is, by periodically changing the chopping polarity of the target output data, the positive and negative chopping polarities can cancel each other out within a frame of data, improving the time uniformity of the chopping circuit and reducing display anomalies at low refresh rates (such as vertical lines, noise, and other display problems). Attached Figure Description

[0026] Figure 1 A pixel polarity diagram provided for embodiments of this disclosure. Figure 1 ;

[0027] Figure 2 A schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure;

[0028] Figure 3 A schematic diagram of the composition structure of an output circuit provided in an embodiment of this disclosure;

[0029] Figure 4 A pixel polarity diagram provided for embodiments of this disclosure. Figure 2 ;

[0030] Figure 5 A signal timing diagram provided for an embodiment of this disclosure Figure 1 ;

[0031] Figure 6 A pixel polarity diagram provided for embodiments of this disclosure. Figure 3 ;

[0032] Figure 7 A signal timing diagram provided for an embodiment of this disclosure Figure 2 ;

[0033] Figure 8 A schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure;

[0034] Figure 9 A schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure is shown in Figure 3.

[0035] Figure 10 A schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure is shown below;

[0036] Figure 11 A schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure is shown in Figure 5.

[0037] Figure 12 A schematic diagram illustrating the working process of a control circuit provided in an embodiment of this disclosure;

[0038] Figure 13 A schematic diagram of the composition structure of a source driver chip provided in an embodiment of this disclosure;

[0039] Figure 14 This is a schematic diagram of the composition structure of a display system provided in an embodiment of the present disclosure. Detailed Implementation

[0040] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0042] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0043] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0044] Before providing a further detailed description of the embodiments of this disclosure, the nouns and terms used in the embodiments of this disclosure will be explained. The nouns and terms used in the embodiments of this disclosure shall be interpreted as follows:

[0045] Source driver integrated circuits (SDICs);

[0046] Source output voltage (SOUT);

[0047] Panel;

[0048] Pixel;

[0049] Polarity Inversion (POL);

[0050] Offset voltage;

[0051] Chop;

[0052] Hertz (Hz);

[0053] P-type metal-oxide-semiconductor (PMOS);

[0054] N-type metal-oxide-semiconductor (NMOS).

[0055] Figure 1 This is a schematic diagram of pixel polarity on a display panel. Here, we will use 4 frames of data as an example to illustrate the changes in pixel polarity. Figure 1The diagram shows nine pixels in the display panel. For each pixel, the POL polarity is shown in the pattern-filled area, and the chopper polarity is shown to the right of the pattern-filled area. For example, pixel 12 has a POL polarity of - (negative) and a chopper polarity of + (positive). Each pixel is connected to a transistor. The source and drain of the transistor are connected to the pixel and the source driver chip, respectively. The gate of the transistor is connected to a switch control signal. When the switch control signal turns on the transistor, the source charging voltage provided by the source driver chip charges the pixel from the source to the drain (or from the drain to the source). Figure 1 As shown, the gates of a row of pixels are connected to the same gate control signal, and the three rows of pixels are denoted as G1, G2 and G3 respectively. The source / drain of a column of pixels is connected to the same source charging voltage, and the three columns of pixels are denoted as S1, S2 and S3 respectively.

[0056] Here, each pixel is composed of one or more liquid crystal molecules. By using POL polarity flipping (or inversion, such as frame-by-frame inversion, row-by-row inversion, column-by-column inversion, etc.), the polarity of the voltage on each pixel (i.e., the output voltage of the source driver chip) can be changed periodically, which helps to prevent the polarization of liquid crystal molecules, thereby reducing image residue, maintaining its good display effect, and improving display stability. Figure 1 The POL polarity of the S1 column pixels in the first to fourth frames is +, -, +, - respectively, meaning that the POL polarity flips once per frame.

[0057] By reversing the chopping polarity of the voltage on each pixel, the low-pass filtering characteristic of the human eye can be utilized to reduce display anomalies such as roughness, uneven vertical lines, and ripples caused by excessive offset voltage, both temporally and spatially, thereby improving display quality. For example, Figure 1 In the first frame, the chopping polarity of the pixels in rows G1 to G3 is +, -, + respectively, making the chopping polarity spatially uniform; the POL polarity of pixel 11 in the first frame is +, and the chopping polarity is +, while the POL polarity of pixel 11 in the third frame is +, and the chopping polarity is -, making the chopping polarity temporally uniform.

[0058] However, with the increasing use of dynamic wide refresh rate applications (such as 24Hz→165Hz), at low refresh rates (such as below 48Hz), the human eye can easily perceive changes in brightness, and the uniformity of chopping polarity will lose its effect, leading to display abnormalities and display problems such as vertical lines and noise.

[0059] Based on this, the present disclosure provides a control circuit that, under low refresh rate conditions, increases the number of chopper polarity reversals so that the positive and negative chopper polarities can cancel each other out within a frame of data, thereby improving the time uniformity of the chopper circuit, reducing display anomalies under low refresh rates, and improving display problems such as vertical lines and noise.

[0060] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0061] In one embodiment of this disclosure, see [link to embodiment]. Figure 2 This illustrates a schematic diagram of the composition of a control circuit 100 provided in an embodiment of this disclosure. For example... Figure 2 As shown, the control circuit 100 includes a receiving circuit 110, a regulating circuit 120, and an output circuit 130, wherein:

[0062] The receiving circuit 110 is used to receive source input data, convert and process the source input data, and output initial output data.

[0063] The control circuit 120 is used to determine the refresh rate of the source input data. When the refresh rate of the source input data is less than or equal to the preset refresh rate, a flip signal is generated and sent to the output circuit 130.

[0064] The output circuit 130 is used to receive initial output data and, during the process of converting the initial output data into target output data for output, if a flip signal is received, performs at least once within a frame of data: performing chopping polarity flip on the initial output data to obtain target output data and outputting it; wherein, the output circuit includes at least a chopper circuit and an amplifier, and chopping polarity flip refers to using the chopper circuit to change the polarity of the amplifier's offset.

[0065] It should be noted that, in the embodiments of this disclosure, the control circuit 100 can be applied to the source driver chip or as part of the source driver chip, and is used to provide the source charging voltage (i.e. target output data) to the pixel.

[0066] Here, the source input data can be in a first format, such as a digital format, like grayscale values ​​or gray levels; the initial output data can be in a second format, such as an analog data signal, like voltage. After receiving the source input data, the receiving circuit 110 can perform processes on the source input data, including but not limited to the following, to generate the initial output data: serial-to-parallel conversion, voltage conversion (low voltage to high voltage), digital-to-analog conversion, etc.

[0067] It should also be noted that in this embodiment, the output circuit 130 includes at least a chopper circuit and an amplifier. Chopper polarity reversal refers to using the chopper circuit to change the polarity of the amplifier's offset. The chopper polarity is the polarity of the output data (i.e., the target output data) offset of the output circuit 130. Specifically, due to the asymmetry in the amplifier design of the output circuit 130 and limitations in chip manufacturing processes, there is a voltage deviation between the actual data output by the output circuit 130 (i.e., the target output data) and the target data to be achieved. When the voltage of the actual data is greater than that of the target data, the chopper polarity of the data is +; when the voltage of the actual data is less than that of the target data, the chopper polarity of the data is -. It can be understood that the relationship between the actual data and the target data is an objectively existing deviation caused by factors such as chip manufacturing processes. By reversing the chopper polarity, the chopper polarity of the data is changed between "+" and "-", thus resulting in a more uniform overall performance.

[0068] For example, Figure 3 This is a simplified structural diagram of an optional output circuit 130 provided in an embodiment of the present disclosure; in other embodiments, the output circuit 130 may also be any other feasible structure, and there is no limitation thereto.

[0069] like Figure 3 As shown, the output circuit 130 includes an amplifier 121 and a chopper circuit. The chopper circuit includes a first switch SW1 to a fourth switch SW4. Specifically, the first switch SW1 is connected to the first input terminal (+) of the amplifier 121, the second switch SW2 is connected to the second input terminal (-) of the amplifier 121, the third switch SW3 is connected between the first input terminal and the output terminal of the amplifier 121, and the fourth switch SW4 is connected between the second input terminal and the output terminal of the operational amplifier 121. The amplifier 121 can be an operational amplifier.

[0070] like Figure 3 As shown, when the first switch SW1 and the fourth switch SW4 are on, and the second switch SW2 and the third switch SW3 are off, the initial output data can be followed by amplifier 121 (e.g., signal buffering, isolation, impedance matching, etc.) to generate the target output data. When the switch is switched so that the second switch SW2 and the third switch SW3 are on, and the first switch SW1 and the fourth switch SW4 are off, the amplifier 121 follows the signal and changes the polarity of the initial output data to generate the target output data. In other words, in Figure 3 In the example shown, "chopping" is to switch the state of each switch so that the output of amplifier 121 is connected to the first input or the second input of amplifier 121 at different cycles, thereby achieving a uniform display effect.

[0071] Among them, the first switch SW1, the fourth switch SW4, the second switch SW2 and the third switch SW3 can all be transistors (for example, all of them are NMOS transistors or all of them are PMOS transistors, or some are NMOS transistors and the other part is PMOS transistors) and other devices with switching functions, and their conduction and disconnection are controlled by corresponding switching signals.

[0072] In this embodiment of the present disclosure, the output circuit 130 may further include a signal generation circuit that generates each switch signal. The flip signal can change the working mode of the signal generation circuit, thereby changing the frequency of each switch signal, and then controlling the on / off state of the first switch SW1 to the fourth switch SW4 through the switch signal to control the number of flips of the chopper polarity.

[0073] For example, within the first half-frame data range, the first switch SW1 and the fourth switch SW4 are turned on; within the second half-frame data range, the second switch SW2 and the third switch SW3 are turned on; this alternation allows for the alternating output of target output data with different chopping polarities.

[0074] exist Figure 1 In the previous method, the chopping polarity of the same pixel was the same in the first and second frames, and it was only flipped in the third frame. In this embodiment of the present disclosure, for low refresh rates, the chopping polarity is controlled to flip at least once within one frame. Thus, for the initial output data of the same frame, assuming that the chopping polarity is controlled to flip once within one frame, the output target data has one chopping polarity (e.g., +) in the first half of the frame and another chopping polarity (e.g., -) in the second half of the frame. The specific flipping can be achieved by alternately switching the connection relationship between the input and output of amplifier 121, thereby switching the chopping polarity of the target output data output by output circuit 130 within one frame of data, so that the positive and negative chopping polarities can cancel each other out and reduce display abnormalities.

[0075] Furthermore, in some embodiments, the voltage polarity (i.e., POL polarity) of the target output data remains unchanged within a frame of data; that is, the POL polarity of the target output data is the same within the same frame, and the POL polarity is opposite in adjacent frames. For example... Figure 4 and Figure 5 As shown, where, Figure 4 This is a diagram illustrating the polarity of pixels during a single chopping polarity flip within a frame of data. Figure 5 For the corresponding Figure 4 The signal timing diagram (only the chopper polarity of column S1 is shown); for comparison, Figure 6 This is a schematic diagram illustrating the polarity of pixels whose polarity is flipped by chopping when not controlled by a flip signal. Figure 7 For the corresponding Figure 6 The signal timing diagram (only the chopper polarity of column S1 is shown).

[0076] Taking a low refresh rate and a single frame of data with one chopping polarity reversal as an example, such as... Figure 4 and Figure 5 As shown, the (n-1)th frame includes a first half-frame (frame-1) and a second half-frame (frame-2), and the nth frame includes a first half-frame (frame-1) and a second half-frame (frame-2). The POL polarity of column S1 in the (n-1)th frame is +, and the POL polarity of column S1 in the nth frame is -. This helps prevent polarization of liquid crystal molecules, thereby reducing image retention, maintaining good display performance, and improving display stability. The chopping polarity of the target output data for the three rows of pixels (G1~G3) in frame-1 is +-+ in sequence, and the chopping polarity of the target output data for the three rows of pixels (G1~G3) in frame-2 is -+- in sequence. This improves the time uniformity of the chopping circuit within a single frame of data, reducing display abnormalities.

[0077] It should also be noted that, such as Figure 5 As shown, for each frame of data, the first half of the frame can be denoted as frame1, and the second half as frame2. For example, the target output data in the nth frame includes n frame1 and n frame2, and the chopping polarities of n frame1 and n frame2 are opposite. This is equivalent to outputting the data twice consecutively within one frame of data, with the chopping polarities of the two outputs being opposite. Compared to not flipping the chopping polarity of the target output data (… Figure 6 and Figure 7 As shown), flipping the chopping polarity of the target output data allows the positive and negative chopping polarities to cancel each other out within a single frame of data, improving the time uniformity of the chopping circuit and reducing display anomalies at low refresh rates; Figure 7 In this context, each frame of data can be denoted as a frame. For example, the target output data of the nth frame can be denoted as n frame. This means that the chopping polarity of the data output remains unchanged within the time of one frame of data.

[0078] In this embodiment, the preset refresh rate can be set according to actual needs. For example, when the display panel operates below 48Hz, display problems such as abnormalities and vertical lines are prone to occur. Therefore, the preset refresh rate can be set to 48Hz. The number of chopper polarity flips can be set according to actual needs. The more chopper polarity flips, the more times the positive and negative chopper polarity switches within a frame of data, which usually improves the display problem better. Since the preset refresh rate is a low refresh rate, the duration of the target output data is longer. The chopper polarity switching time does not affect the total time of pixel charging and maintenance, thus not affecting the display effect of the display panel.

[0079] Please refer to the following. Figures 8 to 10The components of the control circuit 100 provided in the embodiments of this disclosure will be described in detail.

[0080] In some embodiments, the control circuit 120 is specifically used to receive a frame start pulse signal and determine the refresh rate of the source input data according to the frame start pulse signal; and when the refresh rate of the source input data is less than or equal to a preset refresh rate, output a flip signal to the output circuit 130; the flip signal is used to control the number of flips of the chopper polarity.

[0081] It should be noted that, in the embodiments of this disclosure, the frame start pulse signal is used to mark the beginning of a frame of data, such as... Figure 5 or Figure 7 As shown, when a pulse appears in the frame start pulse signal, it indicates that a frame of data has been received. Every time the receiving circuit 110 receives a frame of source input data, the control circuit 120 will detect a pulse in the frame start pulse signal. Thus, the control circuit 120 can determine the refresh rate (i.e., frequency) of the source input signal based on the number of pulses received per unit time.

[0082] It should also be noted that, such as Figure 5 or Figure 7 As shown, each frame of source input data can include processing data and dummy data. The processing data usually carries valuable information, such as panel brightness information; the dummy data is usually used to fill the empty parts in each frame of source input data to ensure the integrity and consistency of each frame of source input data and avoid parsing errors caused by inconsistent source input data lengths.

[0083] In some embodiments, the control circuit 120 is further configured to determine a preset flip signal corresponding to the current refresh rate as a flip signal when the refresh rate of the source input data is less than or equal to a preset refresh rate, and send the flip signal to the output circuit; wherein, the preset flip signal represents the number of times the initial output data is chopped and flipped within a frame of data.

[0084] The output circuit 130 is also used to perform chopping polarity reversal on the initial output data a corresponding number of times according to the reversal signal.

[0085] It should be noted that, in this embodiment of the present disclosure, when the control circuit 120 determines that the refresh rate of the source input data is less than or equal to a preset refresh rate, it outputs a flip signal. Here, the flip signal is used to indicate the chopping polarity flip within a frame of data. The number of flips can be a fixed value, or the number of chopping polarity flips within a frame of data can be controlled by the flip signal; for example, the flip signal can control the number of chopping polarity flips within a frame of data to be 1 time, 2 times, etc. Thus, the output circuit 130 changes its chopping polarity when outputting the initial output data according to the indication of the flip signal.

[0086] As mentioned above Figure 3 For example, the flip signal can control the number of chopper polarity flips within a data frame to a fixed number, say one. The corresponding signal generation circuit then has two operating modes: the first is the normal operating mode when no flip signal is received, where the chopper polarity does not flip within each data frame; the second is the operating mode when a flip signal is received, which increases the number of chopper polarity flips, meaning the chopper polarity flips once within each data frame. In this mode, the frequency of each switching signal is higher than in the normal operating mode. Here, receiving a flip signal can be understood as enabling the flip signal, and not receiving a flip signal can be understood as disabling it. For example, if the flip signal is a one-bit level signal, when the flip signal is "1" (i.e., high level), it is considered enabled; when the flip signal is "0" (i.e., low level), it is considered disabled. Alternatively, it can be the other way around; there is no specific limitation.

[0087] like Figure 3 As shown, taking four switches as NMOS transistors as an example, assuming that the first switch SW1 and the fourth switch SW4 are turned on in the first half of the data frame, and the second switch SW2 and the third switch SW3 are turned on in the second half of the data frame; then, in the first half of the data frame, the state of each switch signal generated by the signal generation circuit is as follows: the first switch signal controlling the first switch SW1 and the fourth switch signal controlling the fourth switch SW4 are at a high level (logic "1"), and the second switch signal controlling the second switch SW2 and the third switch signal controlling the third switch SW3 are at a low level (logic "0"); the level states in the second half of the data frame are opposite to those in the first half of the frame; this alternation allows for the alternating output of target output data with different chopping polarities.

[0088] It should also be noted that the embodiments of this disclosure may predetermine multiple preset flip signals, each preset flip signal corresponding to a preset low refresh rate or a preset low refresh rate range. The optimal time-space uniformity effect of chopper polarity flipping is determined in advance through experiments or theoretical calculations, and the corresponding preset flip signal is stored. The preset flip signal indicates the corresponding number of chopper polarity flips.

[0089] For example, the preset refresh rate is A5, and five preset low refresh rate ranges are pre-set from smallest to largest: less than A1, A1~A2, A2~A3, A3~A4, and A4~A5 (boundary data can be set to belong to one of these ranges based on actual conditions). The corresponding preset flip signals are C1, C2, C3, C4, and C5, respectively. Each preset flip signal indicates the number of chopping polarity flips corresponding to the low refresh rate. Assuming the detected refresh rate is less than or equal to A5 and specifically falls within the range of A2~A3, the preset flip signal C3 is sent to the output circuit 130 as the flip signal. The output circuit 130 chops and flips the initial data output within one frame of data according to the number of chopping flips indicated by C3 to obtain the target output data and output it.

[0090] In this configuration, the signal generation circuit operates in six modes: a standard mode and five modes corresponding to five preset low refresh rate ranges. Each mode generates switching signals at different frequencies. Each preset toggle signal can be a multi-bit binary number, with different values ​​corresponding to different operating modes of the signal generation circuit. For example, a preset toggle signal of three bits, C1=001, C2=010, C3=011, C4=100, and C5=101, corresponds to the five modes within the five preset low refresh rate ranges. Furthermore, when the refresh rate is higher than the preset refresh rate, the output toggle signal is 000, indicating that the mode is disabled. For the signal generation circuit, "000" indicates that no toggle signal has been received, and the switching signals are generated according to the standard mode.

[0091] In other embodiments, the toggle signal may also be a logic signal of other bit lengths or other types of signals (such as analog signals), which is not limited in this disclosure.

[0092] It should also be noted that when the refresh rate of the source input data is greater than the preset refresh rate, the control circuit 120 may not output a flip signal or may output a flip signal indicating that the number of flips is 0 (within this frame of data, the actual operation follows the circuit's original settings, for example). Figure 6 and Figure 7 (The chopper flip is shown).

[0093] For example Figure 6As shown, in the (n-1)th frame, the POL polarity of the target output data corresponding to the pixels in column S1 is all +, and the chopping polarity is +-+ in sequence; in the nth frame, the POL polarity of the target output data corresponding to the pixels in column S1 is all -, and the chopping polarity is -+- in sequence. That is to say, the POL polarity and chopping polarity are flipped simultaneously in each frame, meaning that the output circuit 130 does not perform any additional actions and maintains the original data timing.

[0094] In this embodiment of the disclosure, by setting the control circuit 120 to detect the refresh rate of the source input data, the number of chopper polarity flips can be dynamically adjusted based on the refresh rate of the source input data, which helps to ensure the stability of display quality at different refresh rates.

[0095] In some embodiments, such as Figure 8 As shown, the control circuit 120 may include a detection module 121; wherein, the detection module 121 is used to receive a frame start pulse signal, and determine the refresh rate of the source input data according to the frame start pulse signal; and output a command signal when the refresh rate of the source input data is less than or equal to a preset refresh rate; the command signal serves as the aforementioned toggle signal.

[0096] It should be noted that since the refresh rate of the frame start pulse signal is equal to the refresh rate of the source input data, the detection module 121 can determine that the refresh rate of the source input data is less than or equal to the preset refresh rate when the refresh rate of the frame start pulse signal is less than or equal to the preset refresh rate. In addition, the command signal output by the detection module 121 can be used as a toggle signal, so the detection module 121 has the functions of detecting the refresh rate and controlling the chopper polarity toggle. This not only helps to reduce the size (or area) of the control circuit, but also reduces the intermediate circuits for signal transmission, thereby improving the signal transmission efficiency and accuracy.

[0097] In some embodiments, such as Figure 9 As shown, the control circuit 120 may include a detection module 121 and a polarity reversal module 122; wherein, the detection module 121 is used to receive a frame start pulse signal, and determine the refresh rate of the source input data according to the frame start pulse signal; and output a command signal when the refresh rate of the source input data is less than or equal to a preset refresh rate;

[0098] The polarity reversal module 122 is connected to the detection module 121 and is used to output a reversal signal under the instruction of the command signal after receiving the command signal.

[0099] It should be noted that since the detection module 121 outputs a command signal based on the refresh rate of the frame start pulse signal, the polarity reversal module 122 outputs a reversal signal under the instruction of the command signal; thus, the functions of different modules are more specialized, which not only reduces the difficulty of circuit design, but also facilitates circuit debugging and maintenance, and helps to improve the stability and reliability of the control circuit.

[0100] It should also be noted that, Figure 8 and Figure 9 The detection module 121 shown is also used to not output a command signal or to output a command signal indicating that the number of toggles is 0 when the refresh rate of the source input data (i.e., the frame start pulse signal) is greater than the preset refresh rate. In this way, when the output circuit 130 outputs the received initial output data, it does not perform any additional actions and maintains the original data timing action.

[0101] In other words, the control circuit 120 may contain only one detection module 121, or it may consist of a detection module 121 and a polarity reversal module 122; there is no specific limitation on this.

[0102] In some embodiments, the output circuit 130 is configured to, under the instruction of a flip signal, flip the chopping polarity of the initial output data within a frame of data at least once during the output of the initial output data.

[0103] It should be noted that, taking one chopper polarity reversal within a single frame of data as an example, the target output data with one chopper polarity can be denoted as the first output data, and the target output data with another chopper polarity can be denoted as the second output data. Within a single frame of data, under the instruction of the reversal signal, the output circuit 130 can output the first output data in the first half of the frame, then reverse the chopper polarity of the first output data to obtain the second output data and output it. Alternatively, taking three chopper polarity reversals as an example, within a single frame of data, under the instruction of the reversal signal, the output circuit 130 can sequentially and alternately output the first and second output data within the first 1 / 4 frame, 1 / 4-2 / 4 frames, 2 / 4-3 / 4 frames, and 3 / 4-1 frame.

[0104] It should be noted that when the output circuit 130 does not receive a flip signal, or the received flip signal indicates that the number of flips is 0, the output circuit 130 does not perform any additional actions when outputting the initial output data, but maintains the original data timing and outputs the first output data.

[0105] In this embodiment of the disclosure, since the output circuit 130 flips the polarity of the output signal or maintains the original data timing under the control of the flip signal, a single module can perform multiple tasks, thereby improving the utilization rate of the output circuit 130 and reducing the complexity of the circuit.

[0106] In some embodiments, such as Figure 10 or Figure 11 As shown, the control circuit 100 may further include a storage circuit 140;

[0107] The receiving circuit 110 is also used to send the initial output data to the storage circuit 140;

[0108] The storage circuit 140 is used to receive and temporarily store the initial output data; and to send the initial output data to the output circuit 130 when the refresh rate of the source input data is less than or equal to the preset refresh rate.

[0109] The output circuit 130 is also used to receive the initial output data sent by the storage circuit 140, and based on the flip signal, to perform at least once within a frame of data: chopping the initial output data to flip the polarity to obtain the target output data and outputting it.

[0110] It should be noted that, in Figure 8 On the basis of, such as Figure 10 As shown, when the control circuit 120 only includes the detection module 121 (containing only one module, it can also be directly called the control circuit 120), when the control circuit 120 determines that the refresh rate of the source input data is less than or equal to the preset refresh rate, the control circuit 120 outputs a toggle signal and a command signal. Here, the toggle signal and the command signal can be the same signal or different signals. The command signal is used to indicate that the refresh rate of the source input signal is less than or equal to the preset refresh rate, so as to control the output circuit 120 / storage circuit 140 to perform the corresponding operation.

[0111] The storage circuit 140 outputs the initial output data to the output circuit 130 under the instruction of the command signal; the output circuit 130 receives the initial output data output by the storage circuit 140, and under the instruction of the flip signal, flips the chopping polarity of the initial output data within a frame of data at least once during the output of the initial output data.

[0112] It should also be noted that, in Figure 9 On the basis of, such as Figure 11 As shown, in this implementation, after generating a command signal, the detection module 121 simultaneously sends it to the polarity reversal module 122 and the storage circuit 140, while the rest are connected to... Figure 10 Similarly, this will not be elaborated upon here.

[0113] In some embodiments, such as Figure 10or Figure 11 As shown, the output circuit 130 is connected to the receiving circuit 110 and is also used to prevent the initial output data from being chopped and polarity-reversed within a frame of data when no reversal signal is received.

[0114] Specifically, when the control circuit 120 determines that the refresh rate of the source input data is greater than the preset refresh rate, it does not output a toggle signal or a command signal. At this time, the output circuit 130 processes the initial output data output by the receiving circuit 110 according to the original timing sequence.

[0115] It should also be noted that the output circuit 130 is used to receive initial output data sent by only one of the storage circuit 140 and the receiving circuit 110.

[0116] In this embodiment of the disclosure, when the control circuit 100 includes a storage circuit 140, during the output of initial output data, if the chopping polarity of the initial output data is flipped based on the control of the flip signal, the output circuit 130 can receive the initial output data output by the storage circuit 140; if the chopping polarity of the initial output data is not flipped based on the flip signal, the output circuit 130 receives the initial output data output by the receiving circuit 110. That is, when the refresh rate of the source input data is less than the preset refresh rate (i.e., in the case of a low refresh rate), the storage circuit 140 outputs the initial output data to the output circuit 130; when the refresh rate of the source input data is greater than the preset refresh rate (i.e., in the case of a high refresh rate), the receiving circuit 110 directly outputs the initial output data to the output circuit 130. In this way, signals with different refresh rate ranges are transmitted through different paths, thereby improving data processing efficiency, especially when the refresh rate changes (e.g., from greater than the preset refresh rate to less than the preset refresh rate), which can improve data processing efficiency and reduce latency.

[0117] In this embodiment of the disclosure, under the control of the flip signal, the output circuit 130 can flip the chopping polarity of the initial output data during the process of outputting the initial output data, thereby periodically changing the chopping polarity of the output data of the output circuit 130, improving the time uniformity of the chopping circuit, and improving the display quality even at low refresh rates.

[0118] Next, with Figure 11 Taking the control circuit 100 shown as an example, combined with Figure 12 The flowchart shown illustrates the operation of the control circuit 100. For example, the POL polarity flips once per frame, and the chopper polarity flips twice per frame (including one intra-frame flip between the first and second halves of the frame, and one inter-frame flip between adjacent frames).

[0119] like Figure 12 As shown, first, step S11 is executed, STV≤Preset Refresh Rate; that is, it is determined whether the refresh rate of the frame start pulse signal (STV) is less than or equal to the preset refresh rate (e.g., 48Hz).

[0120] If the refresh rate of the frame start pulse signal (STV) is greater than the preset refresh rate, the source input data is determined to be at a high refresh rate. The control circuit 100 will not perform any additional actions and will maintain the original signal timing action, that is, it will not chop and reverse the polarity of the stored frame data before outputting it.

[0121] If the refresh rate of the frame start pulse signal (STV) is less than or equal to the preset refresh rate, then the source input data is determined to be low refresh rate, and steps S12 and S13 are executed next.

[0122] In step S12, the POL polarity and chopper polarity of the output target data remain unchanged; that is, the control circuit 100 outputs half a frame of target output data according to the original POL polarity and chopper polarity, i.e., outputs the first output data; because the refresh rate is low, it will not affect the pixel charging time.

[0123] In step S13, the POL polarity of the output target data remains unchanged, while the chopper polarity is flipped. When the control circuit 100 outputs the target output data in the second half of the frame, it flips the chopper polarity, i.e., outputs the second output data.

[0124] In this embodiment, since the POL polarity of the first output data and the second output data remains unchanged and the chopping polarity is opposite, the positive and negative chopping polarities of the same pixel can cancel each other out within one frame of data, thereby improving the time uniformity effect of the chopping circuit and improving the display quality.

[0125] The control circuit 100 provided in this embodiment can store a frame of data. When the refresh rate of the source input data is detected to be lower than the preset refresh rate (e.g., 48Hz), the output circuit 130 can continuously output target output data with opposite chopping polarities twice (or four times, eight times, etc.) within a frame of data. This increases the frequency of chopping polarity changes of the target output data, improves the time uniformity of the chopping circuit, and improves the display quality.

[0126] In another embodiment of this disclosure, see Figure 13 This illustrates a schematic diagram of the composition structure of a source driver chip provided in an embodiment of this disclosure. For example... Figure 13 As shown, the source driver chip 200 includes a control circuit 100.

[0127] Thus, since the source driver chip 200 includes the aforementioned control circuit 100, it has at least the same advantages as the aforementioned control circuit 100.

[0128] In another embodiment of this disclosure, see [reference needed]. Figure 14 This illustration shows a schematic diagram of the composition structure of a display system provided in an embodiment of this disclosure. For example... Figure 14 As shown, the display system 300 may include the source driver chip 200 as described in any of the foregoing embodiments.

[0129] In the embodiments disclosed herein, the display system 300 may be any product or component with display function, such as a mobile phone, tablet computer, flexible display device, television set, or monitor, and no specific limitation is made thereto.

[0130] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0131] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0132] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0133] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0134] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0135] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0136] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A control circuit, characterized in that, It includes a receiving circuit, a control circuit, and an output circuit, wherein: The receiving circuit is used to receive source input data, convert and process the source input data, and output initial output data. The control circuit is used to determine the refresh rate of the source input data. When the refresh rate of the source input data is less than or equal to a preset refresh rate, a preset flip signal corresponding to the current refresh rate is determined as a flip signal, and the flip signal is sent to the output circuit. The preset flip signal represents the number of times the initial output data is chopper polarity flipped within a frame of data. The output circuit is used to receive the initial output data, and during the process of converting the initial output data into target output data for output, if the flip signal is received, it performs at least once within a frame of data: performing chopping polarity flipping on the initial output data a number of times corresponding to the flip signal, thereby obtaining and outputting the target output data; wherein, the output circuit includes at least a chopper circuit and an amplifier, and chopping polarity flipping refers to using the chopper circuit to change the polarity of the amplifier's offset.

2. The control circuit according to claim 1, characterized in that, The control circuit is also used to receive a frame start pulse signal and determine the refresh rate of the source input data based on the frame start pulse signal.

3. The control circuit according to claim 1, characterized in that, The control circuit includes a detection module and a polarity reversal module; wherein... The detection module is configured to receive a frame start pulse signal, determine the refresh rate of the source input data based on the frame start pulse signal, and output a command signal when the refresh rate of the source input data is less than or equal to the preset refresh rate. The polarity reversal module is used to receive the command signal and output the reversal signal under the instruction of the command signal.

4. The control circuit according to claim 1, characterized in that, The control circuit also includes a storage circuit; The receiving circuit is also used to send the initial output data to the storage circuit; The storage circuit is used to receive and temporarily store the initial output data; and to send the initial output data to the output circuit when the refresh rate of the source input data is less than or equal to a preset refresh rate. The output circuit is also used to receive the initial output data sent by the storage circuit, and based on the flip signal, to perform at least once within a frame of data: to chop the initial output data to flip its polarity to obtain the target output data and output it.

5. The control circuit according to claim 4, characterized in that, The output circuit is configured to receive the initial output data sent by only one of the storage circuit and the receiving circuit.

6. The control circuit according to claim 1, characterized in that, The output circuit is also configured to not perform chopping polarity reversal on the initial output data within the range of the one-frame data when the reversal signal is not received.

7. The control circuit according to any one of claims 1 to 6, characterized in that, Within the range of the data frame, the voltage polarity of the target output data remains unchanged.

8. A source driver chip, characterized in that, Includes the control circuit as described in any one of claims 1 to 7.

9. A display system, characterized in that, Including the source driver chip as described in claim 8.

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