Display configuration method and device of display, electronic equipment and readable medium

Abstract

The embodiment of the invention provides a display configuration method and device of a displayer, electronic equipment and a readable medium, and relates to the technical field of computers.The method comprises the steps that under the condition that the displayer is not compatible with a first signal type, a target setting statement is obtained; the first signal type is a signal type currently supported by a display controller in the electronic equipment. Executing the target setting statement during starting so as to set a specified register bit of a configuration register corresponding to the display controller as a specified value; wherein the display card in the electronic equipment outputs the display signal of the second signal type under the condition that the appointed register bit is the appointed value, so that the display normally displays. Therefore, the display card can be controlled to output the display signal conforming to the second signal type by setting the specified register bit of the configuration register corresponding to the display controller as the specified value, so that the display can normally display the received display signal, and the problem of abnormal display of an old display is avoided.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a display configuration method, device, electronic device and readable medium of a display. Background Art

[0002] With the continuous development of electronic equipment technology, electronic equipment is increasingly widely used. At present, electronic equipment is often equipped with an external display, and the electronic equipment controls the display state of the display through a display controller in a graphics card, thereby displaying images to users.

[0003] In the related art, the display signal type output by the graphics card may be inconsistent with the display signal type supported by the monitor, and some old monitors are not compatible with the display signal type output by the graphics card, which may cause abnormal display problems. Summary of the invention

[0004] The embodiments of the present invention provide a display configuration method, device, electronic device and readable medium of a display, which can solve the problem of abnormal display.

[0005] In order to solve the above problem, an embodiment of the present invention discloses a display configuration method of a display, which is applied to an electronic device, and the method includes:

[0006] In the case where the display is not compatible with a first signal type, acquiring a target setting statement; the first signal type is a signal type currently supported by a display controller in the electronic device;

[0007] The target setting statement is executed upon startup to set the designated register bit of the configuration register corresponding to the display controller to a designated value; wherein, when the designated register bit is the designated value, the graphics card in the electronic device outputs a display signal of the second signal type so that the display can display normally.

[0008] Optionally, the method further comprises:

[0009] Outputting the test signal of the first signal type to the display through the graphics card;

[0010] In the event that the display does not normally respond to the test signal, it is determined that the display is not compatible with the first signal type.

[0011] Optionally, the target setting statement includes a first setting statement and / or a second setting statement; and executing the target setting statement at startup includes:

[0012] When the electronic device enters the firmware startup phase, executing the first setting statement to control the designated register bit to remain at the designated value during the firmware running phase; and / or,

[0013] When the electronic device enters the system startup phase, the second setting statement is executed to control the designated register bit to remain at the designated value during the system operation phase.

[0014] Optionally, the target setting statement includes a destination address and a preset register value; the register value of the designated register bit included in the preset register value is the designated value, and the destination address is a corresponding address of the configuration register;

[0015] The step of setting the designated register bit of the configuration register corresponding to the display controller to a designated value comprises:

[0016] The preset register value is written to the destination address to set the designated register bit to the designated value and keep other register bits at default values.

[0017] Optionally, the designated register bit includes a packet enable bit; wherein the register value of the packet enable bit included in the preset register value is 0.

[0018] Optionally, the designated register bit also includes an audio enable bit and a disable bit of the leading monitoring segment; wherein the register value of the audio enable bit included in the preset register value is 0, and the register value of the disable bit of the leading monitoring segment is 1.

[0019] Optionally, the method further comprises:

[0020] If the configuration register is a volatile register, the target setting statement is re-acquired each time a startup instruction is received.

[0021] On the other hand, an embodiment of the present invention discloses a display configuration device for a display, which is applied to an electronic device, wherein the electronic device includes an integrated graphics card and a display, and the device includes:

[0022] A first acquisition module, configured to acquire a target setting statement when the display is not compatible with a first signal type; the first signal type is a signal type currently supported by a display controller in the electronic device;

[0023] An execution module is used to execute the target setting statement at startup to set the specified register bit of the configuration register corresponding to the display controller to a specified value; wherein, when the specified register bit is the specified value, the graphics card in the electronic device outputs a display signal of the second signal type to enable the display to display normally.

[0024] Optionally, the device further comprises:

[0025] an output module, configured to output a test signal of the first signal type to the display via the graphics card;

[0026] The determination module is used to determine that the display is not compatible with the first signal type when the display does not respond to the test signal normally.

[0027] Optionally, the target setting statement includes a first setting statement and / or a second setting statement; and the execution module is specifically configured to:

[0028] When the electronic device enters the firmware startup phase, executing the first setting statement to control the designated register bit to remain at the designated value during the firmware running phase; and / or,

[0029] When the electronic device enters the system startup phase, the second setting statement is executed to control the designated register bit to remain at the designated value during the system operation phase.

[0030] Optionally, the target setting statement includes a destination address and a preset register value; the register value of the designated register bit included in the preset register value is the designated value, and the destination address is a corresponding address of the configuration register;

[0031] The execution module is further specifically used for:

[0032] The preset register value is written to the destination address to set the designated register bit to the designated value and keep other register bits at default values.

[0033] Optionally, the designated register bit includes a packet enable bit; wherein the register value of the packet enable bit included in the preset register value is 0.

[0034] Optionally, the designated register bit also includes an audio enable bit and a disable bit of the leading monitoring segment; wherein the register value of the audio enable bit included in the preset register value is 0, and the register value of the disable bit of the leading monitoring segment is 1.

[0035] Optionally, the device further comprises:

[0036] The second acquisition module is configured to reacquire the target setting statement each time a startup instruction is received if the configuration register is a volatile register.

[0037] On the other hand, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the aforementioned method.

[0038] The embodiment of the present invention further discloses a machine-readable medium on which instructions are stored. When executed by one or more processors, the processors are enabled to execute the method described above.

[0039] The embodiment of the present invention includes the following advantages: In the display configuration method of the display provided by the embodiment of the present invention, when the display is not compatible with the first signal type, a target setting statement is obtained; the first signal type is the signal type currently supported by the display controller in the electronic device. The target setting statement is executed at startup to set the specified register bit of the configuration register corresponding to the display controller to a specified value; wherein, when the specified register bit is the specified value, the graphics card in the electronic device outputs a display signal of the second signal type so that the display can display normally. In this way, by setting the specified register bit of the configuration register corresponding to the display controller to the specified value, the graphics card can be controlled to output a display signal that conforms to the second signal type, so that the display can normally display the received display signal, thereby avoiding the problem of abnormal display of old displays. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0041] Figure 1 is a flowchart of a display configuration method of a display provided by an embodiment of the present invention;

[0042] Figure 2 is a schematic diagram of a configuration register provided by an embodiment of the present invention;

[0043] Figure 3 is a block diagram of a display configuration device of a display provided by an embodiment of the present invention;

[0044] Figure 4 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] Figure 1 is a flowchart of a display configuration method of a display provided by an embodiment of the present invention, such as Figure 1 As shown, the display configuration method of the display may include the following steps:

[0047] Step 101: When the display is not compatible with a first signal type, obtain a target setting statement; the first signal type is a signal type currently supported by a display controller in the electronic device.

[0048] Step 102: execute the target setting statement upon startup to set the designated register bit of the configuration register corresponding to the display controller to a designated value; wherein, when the designated register bit is the designated value, the graphics card in the electronic device outputs a display signal of a second signal type to enable the display to display normally.

[0049] The display configuration method of the display provided in the embodiment of the present invention can be applied to electronic devices. Among them, the graphics card can be an integrated graphics card or an independent graphics card, and the display controller can be a display controller of an integrated graphics card, or it can also be a display controller of an independent graphics card. The display can be a display external to the electronic device or a display screen integrated with the electronic device, and the embodiment of the present invention does not limit this.

[0050] In an embodiment of the present invention, the second signal type may be a signal type supported by the display. The first signal type and the second signal type may be determined according to actual conditions. For example, the first signal type may be a High Definition Multimedia Interface (HDMI) signal type, and the second signal type may be a Digital Visual Interface (DVI) signal type. Accordingly, the graphics card of the electronic device may support HDMI signal output, and the display of the electronic device may be a display with a DVI interface (referred to as a DVI display). In the related art, the display signal output by the graphics card to the display is an HDMI signal, but some old DVI displays are not designed for compatibility with HDMI signals, which may lead to abnormal display problems.

[0051] Exemplarily, in the related art, new DVI displays often have compatibility designs for HDMI signals. If the HDMI signal is input normally, the DVI display can decode the HDMI signal internally to convert the HDMI signal into a standard DVI signal. Alternatively, some new DVI displays have HDMI interfaces and DVI interfaces, which are compatible with each other. In this way, the graphics card directly outputs the HDMI signal to the display, and the DVI display can also display normally. However, in actual application scenarios, the display used by the electronic device may be an old device, the display only has a DVI interface, and the display does not have a compatibility design for decoding the HDMI signal into the DVI signal. If the HDMI signal is output directly, it will cause abnormal picture or abnormal display of no picture. It should be noted that in an embodiment of the present invention, the display configuration method of the above-mentioned display may be executed when the DVI interface of the display is connected to avoid unnecessary configuration operations when the HDMI interface is connected.

[0052] In some scenarios, with the rapid development of information technology and the differentiation of user needs, the use of integrated graphics cards that output HDMI signals is expanding, and there are a large number of needs to use DVI display interfaces for display output. However, some electronic devices specify the use of old DVI monitors, so it is impossible to replace DVI monitors with new monitors in time. In this way, when the host of the electronic device is replaced with a host that uses an integrated graphics card that supports HDMI signals, there will be display incompatibility and problems that cannot be displayed normally.

[0053] Furthermore, it is possible to first detect whether the display used by the electronic device is compatible with the signal type currently supported by the display controller. If it is not compatible, an operation of obtaining a target setting statement can be performed. The target device statement is used to configure the configuration register corresponding to the integrated graphics card. The target setting statement can be input by the user or a predetermined instruction preset in the firmware or operating system kernel. In the embodiment of the present invention, the specific behavior of the graphics card outputting the display signal can be controlled by setting the value of the specified register bit in the configuration register.

[0054] Specifically, the target setting statement may be an executable statement, for example, the target setting statement may be a command statement for instructing to set a specified register bit of a configuration register corresponding to the display controller to a specified value. Accordingly, executing the target setting statement at startup can achieve setting the specified register bit of the configuration register corresponding to the display controller to a specified value. Among them, the specified register bit and the specified value may be predefined. Since the graphics card has the characteristic of outputting a display signal of the second signal type when the specified register bit is a specified value. Therefore, by setting the specified register bit of the configuration register corresponding to the display controller to a specified value, the graphics card can be controlled to generate and output a display signal of the second signal type, so that the display can normally display the received display signal of the second signal type.

[0055] In summary, in the display configuration method of the display provided by the embodiment of the present invention, when the display is not compatible with the first signal type, a target setting statement is obtained; the first signal type is the signal type currently supported by the display controller in the electronic device. The target setting statement is executed at startup to set the specified register bit of the configuration register corresponding to the display controller to a specified value; wherein, when the specified register bit is the specified value, the graphics card in the electronic device outputs a display signal of the second signal type so that the display can display normally.

[0056] In this way, by setting the specified register bit of the configuration register corresponding to the display controller to a specified value, the graphics card can be controlled to output a display signal that conforms to the second signal type, so that the monitor can display the received display signal normally, avoiding the problem of abnormal display on old monitors.

[0057] Optionally, the embodiment of the present invention may further include the following steps:

[0058] Step S21: outputting a test signal of the first signal type to the display via the graphics card.

[0059] Step S22: When the display does not normally display the response test signal, determine that the display is not compatible with the first signal type.

[0060] In an embodiment of the present invention, when the display is connected for the first time, or when the electronic device is started for the first time, it can be tested whether the display is compatible with the first signal type. If the display is compatible with the first signal type, it means that the display can normally load and display the corresponding data of the display signal of the first signal type. In this case, there is no need to set the specified register bit of the configuration register corresponding to the display controller to a specified value. Otherwise, it is necessary to set the specified register bit of the configuration register corresponding to the display controller to a specified value so that the graphics card outputs a display signal of the second signal type to ensure that the display can display normally. Exemplarily, a test data display instruction can be sent to the electronic device, and the electronic device can output the display information of the corresponding test data through the graphics card in response to the test data display instruction. At this time, the graphics card adopts the default configuration, that is, each register bit of the configuration register corresponding to the graphics card is the default value conventionally adopted, and the display information output by the graphics card (that is, the above-mentioned test signal) is the first signal type. For example, the graphics card normally outputs an HDMI signal.

[0061] Among them, the test data can be a pre-prepared image or video file. Exemplarily, the test data can be a startup screen of an electronic device. In an embodiment of the present invention, the startup button of the electronic device can be clicked to control the startup of the electronic device. The operation of clicking the startup button can trigger a test data display instruction. Under normal circumstances, the electronic device outputs a display signal of an HDMI type startup screen through a graphics card. Accordingly, if the display displays the startup screen normally, it can be determined that the display is compatible with the first signal type. Conversely, if the display does not display the startup screen normally, it can be determined that the display is not compatible with the first signal type.

[0062] Specifically, the tester can determine whether the display normally displays the boot screen by viewing the display screen of the display. Accordingly, the tester can input indication information representing a normal response when the display is viewed normally, and input indication information representing an abnormal response when the display is not viewed normally. The electronic device can determine that the display is compatible with the first signal type when receiving the indication information representing a normal response, and determine that the display is not compatible with the first signal type when receiving the indication information representing an abnormal response. Alternatively, the electronic device can also take a screenshot of the display to obtain the currently displayed image. Then the currently displayed image is compared with the preset boot image. If the two are consistent, it can be determined that the normal response test signal is determined, and then it is determined that the display is compatible with the first signal type. If the two are inconsistent, it can be determined that the abnormal response test signal is determined, and then it is determined that the display is not compatible with the first signal type. Further, when it is determined that the display is not compatible with the first signal type, a target setting statement can be obtained to configure the configuration register corresponding to the display controller of the graphics card.

[0063] It should be noted that, in the embodiment of the present invention, the above steps S21 to S22 can be performed before the above step 101. After the above steps S21 to S22 are performed once, if it is determined that the display is not compatible with the first signal type, a compatibility mark used to characterize that the display is not compatible with the first signal type can be set at the first designated position. In this way, the subsequent electronic device can directly detect the first designated position. If the compatibility mark characterizing that the display is not compatible with the first signal type is detected, it can be directly determined that the display is not compatible with the first signal type. In this way, the efficiency of determining whether the display is compatible with the first signal type can be improved to a certain extent. Among them, the specific address of the first designated position can be set as needed, and the embodiment of the present invention does not limit this. The specific form of the compatibility mark characterizing that the display is not compatible with the first signal type can also be set as needed, and the embodiment of the present invention does not limit this. Further, it is also possible to determine whether the display is compatible with the first signal type in other ways. Exemplarily, the user can manually check whether the display is compatible with the first signal type. Accordingly, the electronic device can determine that the display is not compatible with the first signal type when receiving information input by the user to indicate that the display is not compatible with the first signal type. The embodiment of the present invention does not limit this.

[0064] In an embodiment of the present invention, a test signal of the first signal type is first output to the display through the graphics card. Then, if the display does not respond to the test signal normally, it is determined that the display is not compatible with the first signal type. In this way, by actually outputting a real test signal of the first signal type to the display, and based on whether the display can respond to the test signal normally, it is determined whether the display is compatible with the first signal type. Specifically, if the display does not respond to the test signal normally, it is determined that the display is not compatible with the first signal type. In this way, through actual testing, the accuracy of detecting whether the display is compatible with the first signal type can be ensured.

[0065] Optionally, the embodiment of the present invention may further include:

[0066] Step S31: If the configuration register is a volatile register, then each time a startup instruction is received, the target setting statement is reacquired.

[0067] Specifically, registers can be divided into volatile registers and non-volatile registers. Among them, volatile registers will lose their configuration values ​​after power failure, so that after the electronic device is powered off, the values ​​of each register bit in the volatile register are restored to the default value. Non-volatile registers will still maintain their configuration values ​​after power failure, so that even after the electronic device is powered off, the values ​​of each register bit in the non-volatile register are the previously configured values.

[0068] In an embodiment of the present invention, the startup instruction may be triggered by a user clicking a power button of the electronic device. That is, when the electronic device receives the startup instruction, it indicates that the electronic device enters the power-on state from the power-off state, and the electronic device was previously in the power-off state. Accordingly, in an embodiment of the present invention, when the display of the electronic device is not compatible with the first signal type supported by the integrated graphics card, if the configuration register is a volatile register, the electronic device may re-execute the operation of obtaining the target setting statement each time the startup instruction is received. In this way, each time it is started, the value of the specified register bit in the configuration register corresponding to the display controller will be configured to the specified value based on the obtained target setting statement, thereby ensuring that the graphics card can output a display signal of the second signal type supported by the display, and ensuring that the display can display normally.

[0069] In the embodiment of the present invention, the display controller of the electronic device is reset to the default state each time it is powered on, so it needs to be reconfigured each time it is started. Specifically, the register type of the configuration register corresponding to the graphics card can be found from the preset register manual. If the queried register type indicates that the configuration register is a volatile register, then the electronic device can perform an operation of obtaining a target setting statement each time it is powered on, if it is determined that the display is not compatible with the first signal type (for example, it can detect whether the first specified position has the aforementioned compatibility mark to determine whether the display is compatible with the first signal type), and then correspondingly perform an operation of executing the target setting statement at startup. Correspondingly, the electronic device can receive the target setting statement input by the user to achieve the acquisition of the target setting statement. Alternatively, the user can input the target setting statement, and the electronic device can save the input target setting statement to the second specified position of the electronic device. Correspondingly, the electronic device can load the target setting statement from the second specified position each time to achieve the acquisition of the target setting statement. In this way, the user only needs to input once, without having to input the target setting statement multiple times, thereby improving the acquisition efficiency of the target setting statement. Among them, the specific address of the second specified position can be set as needed, and the embodiment of the present invention does not limit this. Exemplarily, the second designated location may be a storage location in a non-volatile storage medium, for example, the second designated location may be a storage location in a hard disk. Accordingly, a data read command may be used to read data from the second designated location in the hard disk to obtain a target setting statement.

[0070] In the embodiment of the present invention, if the configuration register is a volatile register, the target setting statement is re-acquired each time a startup instruction is received. In this way, it can be avoided that after the electronic device is shut down and powered off, the configuration register is restored to the default value, which causes the electronic device to be unable to output the display signal of the second signal type to the display through the graphics card after it is subsequently started again, thereby causing the problem of abnormal display.

[0071] Optionally, in an embodiment of the present invention, the target setting statement may include a first setting statement and / or a second setting statement. Accordingly, the step of executing the target setting statement at startup may specifically include:

[0072] Step 1021: When the electronic device enters the firmware startup phase, execute the first setting statement to control the designated register bit to remain at the designated value during the firmware running phase.

[0073] Step 1022, and / or, when the electronic device enters the system startup phase, executing the second setting statement to control the designated register bit to remain at the designated value during the system operation phase.

[0074] Among them, the startup process of the electronic device may include a firmware startup phase, a firmware running phase, an operating system startup phase, and an operating system running phase. Specifically, after the electronic device is powered on, the firmware can be started, and then enter the firmware startup phase. After the firmware startup is completed, the firmware running phase is entered. Exemplarily, the firmware in the embodiment of the present invention can be PMON firmware, wherein the PMON firmware is an open source software with some functions of the Basic Input / Output System (BIOS). In the firmware running phase, the hardware device can be initialized to provide the services required to start the operating system. Exemplarily, a boot loader can be loaded in the operating system startup phase to load the operating system kernel and other necessary system files through the boot loader, and then the operating system kernel is loaded into the memory, and the system services, device drivers and user space programs are initialized. Finally, the operating system running phase is entered.

[0075] Specifically, the first setting statement may be a command statement that can be executed in the firmware stage, and the second setting statement may be a command statement that can be executed in the operating system stage. In an embodiment of the present invention, the first setting statement may be executed when the electronic device enters the firmware startup stage to set the specified register bit of the configuration register to a specified value, thereby ensuring that the specified register bit is set to the specified value during the firmware operation stage, that is, controlling the specified register bit to remain at the specified value during the firmware operation stage. Further, when entering the system startup stage, the configuration register may be restored to the default value. Therefore, in an embodiment of the present invention, the second setting statement may be executed when the electronic device enters the system startup stage to set the specified register bit of the configuration register to a specified value, thereby ensuring that the specified register bit is set to the specified value during the system operation stage, that is, controlling the specified register bit to remain at the specified value during the system operation stage.

[0076] In the embodiment of the present invention, only the first setting statement may be obtained and executed, or only the second setting statement may be obtained and executed. It should be noted that if only the first setting statement is executed, it can only ensure that the graphics card outputs the display signal of the second signal type during the firmware running stage, that is, it can only ensure that the display of the electronic device can display normally during the firmware running stage. If only the second setting statement is executed, it can only ensure that the graphics card outputs the display signal of the second signal type during the system running stage, that is, it can only ensure that the display of the electronic device can display normally during the system running stage.

[0077] In the embodiment of the present invention, when the electronic device enters the firmware startup phase, the first setting statement is executed to control the specified register bit to remain at the specified value during the firmware operation phase. And, when the electronic device enters the system startup phase, the second setting statement is executed to control the specified register bit to remain at the specified value during the system operation phase. In this way, it can be ensured that the graphics card of the electronic device can output a display signal of the second signal type during both the firmware operation phase and the system operation phase, thereby ensuring that the display of the electronic device can display normally during both the firmware operation phase and the system operation phase, ensuring the display effect, and ensuring that the user can use it normally.

[0078] Optionally, in an embodiment of the present invention, the target setting statement includes a destination address and a preset register value; wherein the register value of the specified register bit included in the preset register value is the specified value, and the destination address is the corresponding address of the configuration register. Specifically, the destination address may be a configuration register address of a target signal interface, and the target signal interface is a signal interface currently connected between the graphics card and the display.

[0079] Correspondingly, the above-mentioned setting of the designated register bit of the configuration register corresponding to the display controller to the designated value may specifically include: writing the preset register value to the destination address to set the designated register bit to the designated value, and keeping the other register bits as default values. For a register bit, the register bit may have one or more default values ​​for use. Exemplarily, the default value of the register bit may be a conventionally used value predefined for the register bit, and the default value available for the register bit may be determined from the preset register manual, and the preset register value is defined for the target setting statement based on the default value and the designated value. That is, the preset register value may include the register value of the designated register bit and the register value of other register bits, while the register value of other register bits is the default value. Among them, the preset register value and the destination address are two command parameters in the target setting statement. By setting other register bits to default values, it is possible to avoid operation errors caused by mismatch of user-configured values.

[0080] In an embodiment of the present invention, a graphics card may have multiple signal interfaces, and one signal interface may correspond to one signal output. Exemplarily, a graphics card may have two HDMI signal interfaces (e.g., HDMI0 and HDMI1) and one video graphics array (VGA) signal interface. Correspondingly, the display controller (DisplayController, DC) of the graphics card may support two HDMI signal outputs and one VGA signal output. The signal interface currently connected to the display by the graphics card is the target signal interface. Exemplarily, the target signal interface may be HDMI0 or HDMI1. The preset register value may be defined as required, as long as the register value corresponding to the specified register bit is ensured to be the specified value. Specifically, one signal interface corresponds to one configuration register, and one configuration register may include N bits. The preset register value may correspond to an N-bit value, in which the register value corresponding to the specified register bit in the N-bit value is a specified value, and the values ​​of other register bits except the specified register bit are default values.

[0081] The configuration register corresponding to the display controller includes a configuration register of a signal interface. Since the signal interface currently connected between the graphics card and the display is the target signal interface, the configuration register of the target signal interface can be specifically set to ensure that the display signal output to the display conforms to the second signal type. Accordingly, by setting the destination address in the target setting statement, it can be ensured that the configuration register of the signal interface currently connected to the graphics card can be accurately set by executing the target setting statement.

[0082] Exemplarily, assuming that the signal interface currently connected between the graphics card and the display is HDMI0, the destination address defined in the target setting statement can be the configuration register address of HDMI0. The configuration register address defined in the target setting statement can be obtained by adding the base address of the DC controller to the offset address of the configuration register. The configuration register can also be called an HDMI control register, the register name of the configuration register can be HdmiinterfaceCtrl, the offset address of the configuration register of HDMI0 can be 0x1720, and the offset address of the configuration register of HDMI0 can be 0x1730.

[0083] Optionally, by setting different values ​​for the register bits, specific functions can be controlled. In an embodiment of the present invention, the specified register bit may include a packet enable bit (PacketEnable). Optionally, the instruction register bit may also include an audio enable bit (PacketEnable) and a leading guard band disable enable bit (VideoLGBDisable). Specifically, the packet enable bit may be the first bit of the configuration register, the audio enable bit may be the second bit of the configuration register, and the leading guard band disable enable bit may be the third bit of the configuration register. Among them, the packet enable bit is used to control the enabling of the data island packet. Specifically, when the packet enable bit is 0, it indicates prohibition, that is, the display signal output by the graphics card does not include the data island packet, and when the packet enable bit is 1, it indicates enabling. The audio enable bit is used to control the enabling of audio data. Specifically, when the audio enable bit is 0, it indicates prohibition, that is, audio data is not allowed to be generated, and when the audio enable bit is 1, it indicates enabling, that is, audio data is allowed to be generated. The disable enable bit of the leading monitoring segment is used to control the enable of the LGB. Specifically, when the disable enable bit of the LGB is 0, it indicates that the leading monitoring segment is allowed to be generated. When the disable enable bit of the LGB is 1, it indicates that the leading monitoring segment is not allowed to be generated.

[0084] In an embodiment of the present invention, the signal protocol of the first signal type and the signal protocol of the second signal type can be analyzed in advance to determine the difference between the two. Then, the designated register bit and the designated value are determined based on the difference. Taking HDMI signal and DVI signal as examples, based on the signal protocol of HDMI signal and the signal protocol of DVI signal, it can be determined that the difference between HDMI signal and DVI signal lies in the encoding and decoding protocol. Specifically, both HDMI signal and DVI signal adopt the Transition Minimized Differential Signaling (TMDS) encoding method, there is audio in HDMI signal, HDMI signal adds a data island period (dataisland period) during blanking period to transmit data island packet, while DVI signal does not transmit data island packet. Specifically, the data island packet is a data packet for carrying audio data and auxiliary data, the data island packet starts with a leading monitoring segment of two characters in length, audio data is added in the middle, and ends with a trailing guard band (TGB) of two characters in width. Among them, the leading monitoring segment is used to reliably determine the transition from control period to data period, and the trailing monitoring segment is used to reliably determine the conversion from data to control segment. That is, the leading monitoring segment, the suffix monitoring segment and the audio data constitute the data island packet.

[0085] Correspondingly, the register value of the packet enable bit included in the preset register value can be 0, so that the graphics card can be controlled not to generate a data island packet, and then the output display signal is controlled not to include a data island packet (that is, the display signal output itself conforms to the second signal type), so that the output display signal conforms to the DVI signal type and can be displayed normally by the DVI display. Further, the register value of the audio enable bit included in the preset register value can be 0, and the register value of the disable enable bit of the leading monitoring segment can be 1. In this way, the graphics card can be controlled not to generate audio data and not to generate a leading monitoring segment, thereby saving processing resources.

[0086] It should be noted that, when the register value of the packet enable bit is 0, that is, the graphics card is controlled not to generate a data island packet, even if the register value of the audio enable bit is 1, the register value of the disable enable bit of the leading monitor segment is 0, that is, the generation of audio data and the leading monitor segment is allowed. Since the audio data and the leading monitor segment are sent in the form of a data island packet, when the register value of the packet enable bit is 0 and the data island packet is not produced, the generated audio data and the leading monitor segment will not be used to generate a data island packet. Accordingly, no data island packet is sent to the display, so that the output display signal can comply with the DVI signal protocol, and the output display signal can be displayed normally by the DVI display.

[0087] In the embodiment of the present invention, when the disable enable bit of TGB is included, the value of the disable enable bit of TGB can be configured to 1 to control the graphics card not to generate the suffix monitoring segment, thereby further saving processing resources. Of course, in the case where TGB and LGB share a disable enable bit, by setting the disable enable bit of LGB to 1, the leading monitoring segment and the suffix monitoring segment can be controlled not to be generated.

[0088] Furthermore, when outputting an HDMI signal, that is, outputting a display signal of the first signal type, the packet enable bit, the audio enable bit, and the disable enable bit of the leading monitor segment can all be their respective default values, that is, the packet enable bit is 1, the audio enable bit is 1, and the disable enable bit of the leading monitor segment is 0, so that the graphics card can normally generate and send data island packets, thereby outputting an HDMI signal of the first signal type. After executing the target setting statement, the packet enable bit, the audio enable bit, and the disable enable bit of the leading monitor segment are configured from the default values ​​to 0, 0, and 1, respectively, thereby controlling the graphics card not to generate audio, leading monitor segment, and data island packets, thereby outputting a DVI signal of the second signal type.

[0089] Accordingly, when the register value of the packet enable bit included in the preset register value is set to 0, the register value of the audio enable bit is set to 0, and the register value of the disable enable bit of the leading monitoring segment is set to 1, the electronic device can output a display signal that does not include a data island packet to the display through the graphics card in response to the signal output instruction. The signal output instruction can be used to instruct the electronic device to output a display signal.

[0090] Of course, the configuration register may also include other register bits. For example, bit 0 of the configuration register may be an HDMI enable bit (InterfaceEnable), which is used to control the enablement of the HDMI interface. Specifically, when the HDMI enable bit is 0, it indicates prohibition, and when it is 1, it indicates enablement. Bits 4 to 7 may be video preamble length bits (VideoPreambleLength), which are used to indicate the length of the video preamble. The initial value of bits 4 to 7 may be 4'd8, which indicates binary: 1000. The 8th bit can be the Inter-Integrated Circuit PadSelect (I2CPadSel) bit, which is used to select whether to use the built-in I2C module or the general-purpose input / output (GPIO) through the software mode I2C function. Specifically, when the 2CPadSel bit is 0, it means using the GPIO through the software mode I2C function, and when the 2CPadSel bit is 1, it means using the built-in I2C module. The register bits other than the specified register bits can all be default values. It should be noted that the value of the 0th bit in the preset register value can be set to 1 to ensure that the HDMI interface is enabled and the HDMI signal can be output normally.

[0091] For example, Figure 2 is a schematic diagram of a configuration register provided by an embodiment of the present invention, such as Figure 2As shown, the electronic device includes two configuration registers corresponding to HDMI0 and HDMI1 respectively: configuration register a and configuration register b. Among them, configuration register a and configuration register b both include 9 register bits: bits 0 to 8. Among them, bits 1 to 3 are designated register bits, and bits 0 and 4 to 8 are other register bits. Assuming that the target signal interface is HDMI0, by executing the first setting statement, the values ​​of bits 1 to 3 of register a can be configured to be 0, 0, and 1 during the firmware running stage, and bits 0 and 4 to 8 are respectively default values. In this way, the graphics card can be controlled to output a display signal of the second signal type for the display during the firmware running stage, thereby ensuring that the old DVI display can display normally. By executing the second setting statement, the values ​​of bits 1 to 3 of register a can be configured to be 0, 0, and 1 during the system running stage, and bits 0 and 4 to 8 are respectively default values. In this way, the graphics card can be controlled to output a display signal of the second signal type for the display during the system running stage, thereby ensuring that the old DVI display can display normally. Of course, when the target signal interface is HDMI1, the configuration register b can be set in the same way, which will not be repeated here.

[0092] Specifically, the preset register value may also include register values ​​of other register bits, and the register values ​​of other register bits are default values. In this way, by executing the first setting statement, the preset register value defined in the first setting statement can be written to the destination address, and the default values ​​can be written to other register bits, thereby realizing control to set the specified register bit to the specified value during the firmware operation stage, and the other register bits are set to the default values ​​defined in the preset register value defined in the first setting statement, that is, the values ​​of other register bits remain at the default values. By executing the second setting statement, the preset register value defined in the second setting statement can be written to the destination address, and the default values ​​can be written to other register bits, thereby realizing control to set the specified register bit to the specified value during the system operation stage, and the other register bits are set to the default values ​​defined in the preset register value defined in the second setting statement, that is, the other register bits remain at the default values.

[0093] Exemplarily, the first setting statement may be a function call command applicable to the firmware, and the second setting statement may be a function call command applicable to the kernel. The first setting statement may be: write_reg((base+OF_HDMI_CTRL), 0x389). Wherein, 0x389 represents the preset register value in the first setting statement. When 0x389 is expressed as binary, the 1st to 3rd bits are 001 respectively, that is, the register value of the packet enable bit is 0, the register value of the audio enable bit is 0, and the register value of the leading monitor segment disable enable bit is 1. base+OF_HDMI_CTRL represents the destination address, where base represents the base address and OF_HDMI_CTRL represents the offset address. The first setting statement can be used to implement modifications in the firmware.

[0094] Further, the second setting statement can be: ls_mm_wreg(ldev, HDMI_CTRL_REG+reg_offset, 0x289). Among them, 0x289 represents the preset register value in the first setting statement. When 0x289 is expressed as binary, the 1st to 3rd bits are 001 respectively. The default value of the 8th bit of the preset register value in the first setting statement and the preset register value in the second setting statement is different. Specifically, the default value of the 8th bit of the preset register value in the first setting statement is 1, so as to control the use of the built-in I2C module during the firmware running stage. The default value of the 8th bit of the preset register value in the second setting statement is 0, so as to control the use of GPIO through the software mode I2C function during the system running stage. The ldev in the second setting statement is used to indicate the target signal interface, and can provide the base address of the target signal interface. HDMI_CTRL_REG+reg_offset represents the destination address.

[0095] In the embodiment of the present invention, executing the target setting statement can realize writing the preset register value to the destination address, so as to set the specified register bit to the specified value and keep the other register bits as the default value. In this way, by setting the specified register bit of the configuration register to the specified value, the graphics card is controlled to output a display signal that meets the signal type supported by the display, thereby avoiding the problem of abnormal display, ensuring the compatibility of the display, and improving the utilization rate of old displays, providing users with a variety of display solutions, and at the same time, increasing the advantages for the promotion of graphics cards that support the output of HDMI signal types.

[0096] Reference Figure 3 , shows a block diagram of a display configuration device provided by an embodiment of the present invention, which can be applied to electronic devices such as Figure 3 As shown, the display configuration device of the display may specifically include:

[0097] A first acquisition module 201 is used to acquire a target setting statement when the display is not compatible with a first signal type; the first signal type is a signal type currently supported by a display controller in the electronic device;

[0098] The execution module 202 is used to execute the target setting statement at startup to set the specified register bit of the configuration register corresponding to the display controller to a specified value; wherein, when the specified register bit is the specified value, the graphics card in the electronic device outputs a display signal of the second signal type to enable the display to display normally.

[0099] Optionally, the device further comprises:

[0100] A first output module, configured to output a test signal of the first signal type to the display via the graphics card;

[0101] The determination module is used to determine that the display is not compatible with the first signal type when the display does not respond to the test signal normally.

[0102] Optionally, the target setting statement includes a first setting statement and / or a second setting statement; the execution module 202 is specifically configured to:

[0103] When the electronic device enters the firmware startup phase, executing the first setting statement to control the designated register bit to remain at the designated value during the firmware running phase; and / or,

[0104] When the electronic device enters the system startup phase, the second setting statement is executed to control the designated register bit to remain at the designated value during the system operation phase.

[0105] Optionally, the target setting statement includes a destination address and a preset register value; the register value of the designated register bit included in the preset register value is the designated value, and the destination address is a corresponding address of the configuration register;

[0106] The execution module 202 is further specifically configured to:

[0107] The preset register value is written to the destination address to set the designated register bit to the designated value and keep other register bits at default values.

[0108] Optionally, the designated register bit includes a packet enable bit; wherein the register value of the packet enable bit included in the preset register value is 0.

[0109] Optionally, the designated register bit also includes an audio enable bit and a disable enable bit of the leading monitor segment; wherein, the register value of the audio enable bit included in the preset register value is 0, and the register value of the disable enable bit of the leading monitor segment is 1; accordingly, the device also includes: a second output module, which is used to respond to a signal output instruction, and can output a display signal that does not include a data island packet to the display through the graphics card.

[0110] Optionally, the device further comprises:

[0111] The second acquisition module is configured to reacquire the target setting statement each time a startup instruction is received if the configuration register is a volatile register.

[0112] In summary, in the display configuration device of the display provided by the embodiment of the present invention, when the display is not compatible with the first signal type, a target setting statement is obtained; the first signal type is the signal type currently supported by the display controller in the electronic device. The target setting statement is executed at startup to set the specified register bit of the configuration register corresponding to the display controller to a specified value; wherein, when the specified register bit is a specified value, the graphics card in the electronic device outputs a display signal of the second signal type so that the display can display normally. In this way, by setting the specified register bit of the configuration register corresponding to the display controller to a specified value, the graphics card can be controlled to output a display signal that conforms to the second signal type, so that the display can normally display the received display signal, thereby avoiding the problem of abnormal display of old displays.

[0113] Reference Figure 4 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 4 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus.

[0114] The processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the display configuration method of the display of the above embodiment. The executable instruction can form a program.

[0115] An embodiment of the present invention provides a machine-readable medium having instructions stored thereon, which, when executed by one or more processors, enables the processors to execute the display configuration method of the display of the aforementioned embodiment.

[0116] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0117] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0118] It should be noted that all actions of acquiring signals, information or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where they are located and with the authorization given by the owner of the corresponding device.

[0119] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0120] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0121] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0122] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0123] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0124] Moreover, the terms "include", "comprises" or any other variation thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or terminal device that includes the element.

[0125] The display configuration method of a display, a display configuration device of a display, an electronic device and a readable medium provided by the present invention are introduced in detail above. Specific examples are used herein to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A display configuration method for a display, characterized in that: Applied to electronic equipment, the method comprises: In the case where the display is not compatible with a first signal type, acquiring a target setting statement; the first signal type is a signal type currently supported by a display controller in the electronic device; The target setting statement is executed upon startup to set the designated register bit of the configuration register corresponding to the display controller to a designated value; wherein, when the designated register bit is the designated value, the graphics card in the electronic device outputs a display signal of the second signal type so that the display can display normally.

2. The method according to claim 1, characterized in that The method further comprises: Outputting the test signal of the first signal type to the display through the graphics card; In the event that the display does not normally respond to the test signal, it is determined that the display is not compatible with the first signal type.

3. The method according to claim 1, characterized in that The target setting statement includes a first setting statement and / or a second setting statement; executing the target setting statement at startup includes: When the electronic device enters the firmware startup phase, executing the first setting statement to control the designated register bit to remain at the designated value during the firmware running phase; and / or, When the electronic device enters the system startup phase, the second setting statement is executed to control the designated register bit to remain at the designated value during the system operation phase.

4. The method according to any one of claims 1 to 3, characterized in that: The target setting statement includes a destination address and a preset register value; the register value of the designated register bit included in the preset register value is the designated value, and the destination address is the corresponding address of the configuration register; The step of setting the designated register bit of the configuration register corresponding to the display controller to a designated value comprises: The preset register value is written to the destination address to set the designated register bit to the designated value and keep other register bits at default values.

5. The method according to claim 4, characterized in that The designated register bits include a packet enable bit; The register value of the packet enable bit included in the preset register value is 0.

6. The method according to claim 5, characterized in that The designated register bits also include an audio enable bit and a disable enable bit for the leading monitoring segment; The register value of the audio enable bit included in the preset register value is 0, and the register value of the disable enable bit of the leading monitoring segment is 1.

7. The method according to claim 1, characterized in that The method further comprises: If the configuration register is a volatile register, the target setting statement is re-acquired each time a startup instruction is received.

8. A display configuration device for a display, characterized in that: Applied to electronic equipment, the device comprises: A first acquisition module, configured to acquire a target setting statement when the display is not compatible with a first signal type; the first signal type is a signal type currently supported by a display controller in the electronic device; An execution module is used to execute the target setting statement at startup to set the specified register bit of the configuration register corresponding to the display controller to a specified value; wherein, when the specified register bit is the specified value, the graphics card in the electronic device outputs a display signal of the second signal type to enable the display to display normally.

9. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the device according to any one of claims 1 to 7.

10. A readable medium, characterized in that: Instructions are stored thereon, which, when executed by one or more processors, cause the processors to execute the apparatus according to any one of claims 1-7.

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