Memory and operating method thereof

By using data/address multiplexing lines in the memory access interface and adopting a fixed number of random access mode, the problem of insufficient access speed of existing memory is solved, and more efficient access speed and throughput are achieved.

CN119694365APending Publication Date: 2025-03-25GIGADEVICE SEMICON (BEIJING) INC
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Patent Information

Application Number
CN202311246230.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2023-09-25
Publication Date
2025-03-25

AI Technical Summary

Technical Problem

There are shortcomings in the access speed of existing memory, especially when processing multiple random access addresses, the interval between the two accesses is long, which affects efficiency.

Method used

By introducing data/address multiplexing lines into the access interface of the memory, a fixed number of random access mode is adopted to continuously receive and respond to the read and write operations of multiple random access addresses, and avoid inserting new access addresses during data input and output, reducing IO direction switching of the data/address multiplexing lines.

Benefits of technology

This method can significantly reduce the interval between two accesses, improve memory access speed, and in some cases further improve interface throughput.

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Abstract

The invention relates to a memory and an operating method thereof. The memory comprises a memory array and an access interface for externally accessing the memory array comprising at least one data / address multiplexing line for transmitting data and addresses. The method comprises the following steps: starting a specified fixed-number random access mode, and performing continuous read / write operation on a storage array in response to a plurality of received fixed-number random access addresses in the mode; sequentially and continuously receiving a preset fixed number of access addresses through the data / address multiplexing line; a control unit configured to sequentially and continuously output data read in response to the received access addresses via the data / address multiplexing line when the mode indicates a read operation, or sequentially and continuously receive data written in response to the received access addresses via the data / address multiplexing line when the mode indicates a write operation; and ending the mode by receiving an invalid chip enable signal. According to the scheme, the access speed of the memory can be increased.
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