Emission driver, gate driver and display device
By designing a boost circuit of the gate electrode transistor that receives the clock signal in the driver of the display device, the high power consumption problem caused by the clock signal is solved, the power consumption of the transmit driver and the gate driver is reduced, and the energy efficiency of the display device is improved.
CN119724108APending Publication Date: 2025-03-28SAMSUNG DISPLAY CO LTD
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Patent Information
- Application Number
- CN202411292763.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-27
- Filing Date
- 2024-09-14
- Publication Date
- 2025-03-28
AI Technical Summary
Technical Problem
In the existing display devices, the power consumption caused by the clock signal is large, resulting in an increase in the power consumption of the transmit driver and the gate driver, affecting the energy efficiency of the equipment.
Method used
A driver structure including a plurality of transmit stages and gate stages is designed, wherein each level of boost circuit includes transistors of gate electrodes receiving clock signals, reducing the load of clock signals, and reducing the power consumption of the driver by optimizing the structure of boost circuits.
Benefits of technology
It effectively reduces the power consumption of the transmit driver and gate driver and improves the energy efficiency performance of the display device.
✦ Generated by Eureka AI based on patent content.
Abstract
The invention discloses an emission driver, a gate driver and a display device. The transmit driver includes a plurality of transmit stages, and each of the plurality of transmit stages includes a boost circuit configured to boost a voltage of the control node. The boost circuit includes: a fifth transistor including a first electrode, a second electrode, and a gate electrode connected to a control node; a seventeenth transistor including a gate electrode configured to receive a first clock signal, a first electrode configured to receive a second low gate voltage, and a second electrode connected to the first electrode of the fifth transistor; and an eighteenth transistor including a gate electrode configured to receive a second clock signal having a phase different from that of the first clock signal, a first electrode configured to receive a high gate voltage, and a second electrode connected to the first electrode of the fifth transistor.
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