Control method and device for resistive random access memory array

By using three preset voltages for forming and assembling operations in the resistive variable memory array, the problems of peripheral circuit complexity and large area are solved, and higher integration and denser information storage are achieved.

CN119741953AActive Publication Date: 2025-04-01INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
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Patent Information

Application Number
CN202411713666.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-11-27
Publication Date
2025-04-01
Estimated Expiration
2044-11-27

AI Technical Summary

Technical Problem

In the prior art, the peripheral circuits of the resistive memory array are relatively complex and occupy a large chip area, resulting in a low degree of integration.

Method used

By molding and setting the resistive variable memory based on the first preset voltage, the second preset voltage and the third preset voltage, the structure of the voltage generation circuit is simplified, thereby reducing the complexity and area occupied by the peripheral circuit.

Benefits of technology

The voltage generation circuit and peripheral circuit structure are realized, which reduces chip area occupation and improves the integration of the resistive memory array.

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Abstract

The invention provides a control method and device for a resistive random access memory array, which can be applied to the technical field of microelectronics. The control method comprises the following steps: for each resistive random access memory in a resistive random access memory array, carrying out molding operation on the resistive random access memory based on a first preset voltage, a second preset voltage and a third preset voltage to obtain an activated resistive random access memory in an activated state; based on a first preset voltage and a second preset voltage, the activated-state resistive random access memory is subjected to setting operation, a first target resistive random access memory with the resistance value within a first preset range is obtained, the first preset voltage, the second preset voltage and the third preset voltage are generated by sub-circuits of a voltage generation circuit, and the resistance value of the first target resistive random access memory is within a second preset range; the first preset voltage, the second preset voltage and the third preset voltage are not equal.
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