On-chip power management system and power-on control method

Abstract

The present application relates to the field of integrated circuit technology, and discloses an on-chip power management system integrated in a wireless communication system chip; the system includes a first power switch, which connects a power supply and a universal input-output circuit in the system chip, and is used to control the power supply state of the universal input-output circuit; when the system chip is in a sleep state, the first power switch is controlled to power off the universal input-output circuit. The system powers off the universal input-output circuit by controlling the disconnection of the first power switch. In this way, leakage power consumption of the universal input-output circuit is avoided, and the energy consumption of the system chip is reduced. The present application also discloses a power-on control method for a wireless communication system chip.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, for example, to an on-chip power management system and a power-on control method. Background Art

[0002] At present, the power supply solutions of short-distance wireless communication SOC (System on a Chip, referred to as system chip) are basically compatible with the wide voltage design of IOT (Internet of Things) scenarios, and are compatible with the application scenarios of button batteries 2.0V~3.0V and lithium batteries 2.5V~4.25V. However, the wide voltage design usually requires the integration of a wide voltage DC buck converter with a higher load and a high-power LDO (Low-Dropout Regulator, linear regulator). The wide voltage compatibility design makes it difficult for the design of SOC to consider the low power consumption requirements and power signal crosstalk issues from the application solution level. Moreover, when the high frequency and bandwidth of the current high-speed communication SOC are high, it is difficult for the transceiver (Transceiver) to achieve good performance at low power consumption. The high data density caused by the wide bandwidth also makes it difficult to reduce the power consumption of the digital baseband (DBB, Digital Baseband Processor) of such communication SOC.

[0003] The current mainstream CPU (Central Processing Unit), Bluetooth and WiFi all operate on a 1.8V voltage platform. Figure 1 The wide voltage design of 1.65V to 3.6V is compatible with 1.8V voltage, but it cannot effectively cooperate with PMIC (Power Management Integrated Circuit) for power management, and needs to increase voltage domain conversion (Level shift) to communicate with other modules. The power consumption problem of Transceiver and DBB of high-frequency and high-speed communication SOC makes it difficult to balance the power consumption area and performance requirements of PMU (Power Management Unit) system design of such SOC.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0006] The embodiments of the present disclosure provide an on-chip power management system and a power-on control method to achieve power consumption reduction.

[0007] In some embodiments, the on-chip power management system is integrated into a wireless communication system chip, and the system includes: a first power switch, connecting a power supply and a general input / output circuit in the system chip, and used to control the power supply state of the general input / output circuit; when the system chip is in a sleep state, the first power switch is controlled to power off the general input / output circuit.

[0008] In some embodiments, the power-on control method for a wireless communication system chip includes:

[0009] The system chip is powered on, and a power-on reset module, a low-power reference circuit and a low-power linear regulator are enabled to supply power to the RC32K circuit and the always-on module, and the always-on module is enabled to operate under the RC32K clock; the always-on module sequentially enables the power switch, the switch power circuit, the bandgap reference circuit, the linear regulator of the 38M clock circuit, the linear regulator of the system clock phase-locked loop and the linear regulator of the digital operation processor under the RC32K clock; after the linear regulator works, the RC38M clock circuit and the XO38M clock circuit are sequentially enabled to enable the digital operation processor to configure the state of the system chip under the RC38M clock; the digital operation processor enables the system clock phase-locked loop under the RC38M clock, and after the clock of the system clock phase-locked loop works, the RC38M clock is switched to the clock of the system clock phase-locked loop, and the RC38M clock circuit is controlled to be disabled.

[0010] The on-chip power management system and power-on control method provided by the embodiments of the present disclosure can achieve the following technical effects:

[0011] In the disclosed embodiment, the power management system is integrated on the wireless communication system chip, that is, the system chip is added to the power management system. A first power switch is set between the universal input and output circuit of the system chip and the power supply. Therefore, when the system chip is in a low power consumption state, the universal input and output circuit is powered off by controlling the disconnection of the first power switch. In this way, leakage power consumption of the universal input and output circuit is avoided, and the energy consumption of the system chip is reduced.

[0012] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0014] Figure 1 It is a schematic diagram of a power supply structure of a system chip for short-distance communication in the prior art provided by an embodiment of the present disclosure;

[0015] Figure 2 is a schematic diagram of the structure of an on-chip power management system provided by an embodiment of the present disclosure;

[0016] Figure 3 is a schematic diagram of the structure of another on-chip power management system provided by an embodiment of the present disclosure;

[0017] Figure 4 is a schematic diagram of a power supply of an on-chip power management system provided by an embodiment of the present disclosure;

[0018] Figure 5 is a schematic diagram of multiple power supplies of an on-chip power management system provided by an embodiment of the present disclosure;

[0019] Figure 6 is a schematic diagram of the overall structure of an on-chip power management system provided by an embodiment of the present disclosure;

[0020] Figure 7 It is a schematic diagram of a structure in which CORE and DBB are independently powered in an on-chip power management system provided by an embodiment of the present disclosure;

[0021] Figure 8 It is a structural schematic diagram of clock domain division of an on-chip power management system provided by an embodiment of the present disclosure;

[0022] Fig. 9 It is a schematic diagram of the structure of voltage domain division of an on-chip power management system provided by the present disclosure;

[0023] Fig.10 is a schematic diagram of a power-on control method for a wireless communication system chip provided by the present disclosure;

[0024] Fig.11 This is a power-on timing diagram of a wireless communication system chip provided by the present disclosure. DETAILED DESCRIPTION

[0025] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0026] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0027] In the embodiments of the present disclosure, the terms "upper", "lower", "inside", "middle", "outside", "front", "back" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. These terms are mainly intended to better describe the embodiments of the present disclosure and their embodiments, and are not intended to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction. Moreover, in addition to being used to indicate directions or positional relationships, some of the above terms may also be used to indicate other meanings. For example, the term "upper" may also be used to indicate a certain dependency or connection relationship in certain circumstances. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0028] In addition, the terms "disposed", "connected", and "fixed" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0029] Unless otherwise stated, the term "plurality" means two or more.

[0030] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0031] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0032] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0033] Combination Figure 2 As shown, the embodiment of the present disclosure provides an on-chip power management system integrated in a wireless communication system chip, including a first power switch Power SW1. The first power switch Power SW1 is connected to a power supply and a general input output circuit GPIO in the system chip, and is used to control the power supply state of the general input output circuit GPIO; when the system chip is in a sleep state, the first power switch is controlled to power off the general input output circuit GPIO.

[0034] Here, for the on-chip power management system of mobile phones and wearable devices, the power supply voltage of the general input and output circuit GPIO is generally 1.8V, and the power consumption is relatively high. In particular, when the system chip is in a low-power state, the operation of the general input and output circuit GPIO will cause high power consumption, and the power consumption of the system chip cannot be reduced. Therefore, the embodiment of the present disclosure adds a first power switch Power SW1 between the general input and output circuit GPIO and the power supply of the system chip. By controlling the switching state of the first power switch Power SW1, the state of the general input and output voltage is controlled. When the system chip is in a low-power state (the low-power state includes the sleep state and the deep sleep state), the system chip and the external chip only perform wake-up communication. At this time, the general input and output circuit GPIO does not need to be powered, and the first power switch Power SW1 is controlled to be disconnected, thereby cutting off the power supply to the input and output circuit. In this way, the general input and output circuit is not turned on in a low-power state, thereby effectively reducing the energy consumption of the system chip.

[0035] The on-chip power management system provided by the embodiment of the present disclosure is adopted, and the power management system is integrated on the wireless communication system chip, that is, the system chip is added to the power management system. A first power switch is set between the universal input and output circuit of the system chip and the power supply. Therefore, when the system chip is in a low power consumption state, the universal input and output circuit is powered off by controlling the disconnection of the first power switch. In this way, leakage power consumption of the universal input and output circuit is avoided, and the energy consumption of the system chip is reduced.

[0036] Combination Figure 3Optionally, the on-chip power management system further includes a second power switch Power SW2, a third power switch Power SW3, and a fourth power switch Power SW4. The second power switch Power SW2, the third power switch Power SW3, and the fourth power switch Power SW4 are respectively connected to the power supply and the programmable storage unit EFUSE, the flash storage unit FLASH, and the short-term storage unit Rentention Memory.

[0037] When the system chip is in a low power state, the third power switch Power SW3 and the fourth power switch Power SW4 are controlled to be disconnected to power off the flash memory unit FLASH and the short-term storage unit Rentention Memory; and / or, after the programmable storage unit EFUSE is burned, the second power switch Power SW2 is controlled to be disconnected to power off the programmable storage unit EFUSE.

[0038] Here, the system chip includes some modules that need to be powered by a 1.8V (i.e., first voltage power supply) power supply. In order to avoid leakage power consumption caused by the power supply of these modules in a low power consumption state, a power switch is set. The power supply state of these modules is controlled separately by a switching power supply circuit. As an example, in a low power consumption state, the system chip and the external chip only perform wake-up communication. At this time, the unused flash memory storage unit FLASH, short-term storage unit Rentention Memory and other circuits / modules can be powered off to save leakage power consumption. That is, the third power switch and the fourth power switch are controlled to be disconnected. As another example, the power switch used for burning the programmable storage unit EFUSE with a 1.8V power demand has a slow power-on to meet the burning power-on requirement of EFUSE. After the burning is completed, the corresponding second power switch is no longer turned on.

[0039] In addition, the modules / circuits connected to the low-power domain through power switches include input / output modules, flash memory units, short-term memory units, and programmable memory units. The number of power switches corresponds to the number of modules. That is, if all four of the above modules are available, there are four power switches; each power switch controls the on / off state of a module.

[0040] Combination Figure 4 and Figure 5 Optionally, the on-chip power management system further includes a first switching power circuit DC_DC_1 and a second switching power circuit DC_DC_2.

[0041] The first switching power supply circuit DC_DC_1 is used to convert a first voltage power supply into a second voltage power supply; the second switching power supply circuit DC_DC_2 is used to convert the first voltage power supply into a third voltage power supply.

[0042] Among them, when powered by one voltage power supply, the first switching power supply circuit and the second switching power supply circuit respectively power the various modules of the system chip, and the first voltage power supply is one voltage power supply; when powered by multiple voltage power supplies, the first switching power supply circuit and the second switching power supply circuit or multiple voltage power supplies are selected according to needs to power each module.

[0043] Here, the power supply mode of the on-chip power management system includes a single voltage power supply and a plurality of voltage power supplies. Since the CPU of a mobile phone or wearable device usually works at a 1.8V voltage platform, the power supply voltage is generally 1.8V when a single voltage power supply is used (that is, the first voltage power supply can be 1.8V). Figure 4 . Since the power supply voltage required by each model / circuit in the system chip is different, some modules / circuits require a voltage lower than 1.8V. Therefore, a switching power supply circuit is used to convert the power supply voltage to obtain a lower voltage. More specifically, each module / circuit in the system chip also requires voltages of 1.2V and 0.8V. Therefore, in the embodiment of the present disclosure, a first switching power supply circuit and a second switching power supply circuit are set.

[0044] When one voltage power supply is powered, the first switching power supply circuit converts the first voltage power supply into the second voltage power supply to power the linear regulator in the system chip. The second switching power supply circuit converts the first voltage power supply into the third voltage power supply to power the internal modules of the system chip, such as the digital module. The digital module has high power consumption and low requirements on the stability of the power supply. Using the switching power supply circuit to power it helps to reduce power consumption. Among them, the first voltage power supply is 1.8V, the second voltage power supply is 1.1V, and the third voltage power supply is 0.8V.

[0045] In the case of multiple voltage power supplies, the power supply includes a first voltage power supply, a second voltage power supply and / or a third voltage power supply, such as Figure 5 . In this way, each voltage power supply can be selected to power each module, or a high-efficiency switching power supply circuit can be used to convert the first voltage power supply into the power supply required by each module. For example, when the load is high, the switching power supply circuit can be selected for power supply; when the load is low, multiple voltage power supplies can be used for independent power supply. When each voltage power supply is independently powered, the state of each voltage power supply can be controlled based on the needs of the system chip. In addition, it can be understood that the switching power supply circuit can include a first switching power supply circuit or a second switching power supply circuit. As an example, Figure 7 , the digital module can be independently powered by only the second switch power supply circuit, that is, the second switch unit is connected to the external capacitor interface for 0.8V power supply.

[0046] In addition, when applied in other fields, single power supply voltage and multi-power supply voltage are set based on actual needs.

[0047] Optionally, an external capacitor ext_cap is provided at the interface between the switch power supply circuit and each voltage power supply. In this way, the voltage is filtered to reduce voltage fluctuations, thereby reducing interference and noise to ensure stable operation of the system. In some embodiments, a magnetic bead is also provided at the interface to isolate the power supply to avoid interference from other circuits.

[0048] Optionally, the on-chip power management system further includes a bandgap reference circuit BANDGAP, which is connected to the output end of the switching power supply circuit and is used to provide a reference voltage and / or a reference current for the non-low power consumption module.

[0049] Here, in terms of current flow, the bandgap reference circuit is arranged after the switching power supply circuit. That is, the current of the power supply is provided to the bandgap reference circuit after passing through the switching power supply circuit. In this way, when the system chip is in a low power consumption state, the switch of the bandgap reference circuit can be controlled by controlling the on-off state of the switching power supply circuit. Thus, the problem of leakage and static power consumption of the bandgap reference circuit can be avoided.

[0050] In addition, the bandgap reference circuit in the embodiment of the present disclosure provides a reference voltage and / or a reference current for modules / circuits other than the always-on module (i.e., the AON module). The AON module, also known as a low-power module, refers to a module that always remains active during the operation of the system chip and is not powered off in the sleep or deep sleep state. The AON module includes an always-on controller AON_DIG, a wake-up input and output AON_IO, a low-power bandgap reference BGP_LP, a low-power linear regulator LDO_LP, and a short-term storage unit Retention Memory. Modules other than the AON module are high-power modules. The reference voltage and / or reference current of the AON module is provided by the low-power bandgap reference BGP_LP.

[0051] Combination Figure 5 and 6 Optionally, the on-chip power management system further includes: an off-chip capacitor type linear regulator and a non-off-chip capacitor type linear regulator.

[0052] There are multiple off-chip capacitor-type linear regulators for supplying power to digital modules and power amplifiers PA in non-low-power modules.

[0053] There are multiple linear regulators without external capacitors, which are used to supply power to analog modules, radio frequency modules and clock modules in non-low power modules.

[0054] The switching state of the linear regulator is controlled to control the corresponding module to be turned off or on, and the power supply is a multi-voltage power supply.

[0055] In the present disclosure, Figure 6 As shown in the figure, the linear regulator LDO includes an off-chip capacitor type (note ext_cap in the figure) and a non-off-chip capacitor type. Among them, the off-chip capacitor type linear regulator is mainly used to power digital modules and power amplifiers to meet the stable power supply requirements of high-power consumption and high transient response modules. The non-off-chip capacitor type linear regulator powers analog modules (such as analog units in the transmitting channel circuit and the receiving channel circuit), RF modules (such as RF phase-locked loop circuit RF_PLL) and clock modules (such as 38M clock modules), etc., to meet the power supply requirements of these modules. Multiple linear regulators work independently, that is, when the corresponding power supply module does not need to supply power, the corresponding linear regulator can be controlled to power off (that is, by controlling the enable signal of the linear regulator, the linear regulator is not enabled to achieve power off), avoiding leakage and increasing power consumption. And the design of distributed linear regulators can avoid the problem of signal crosstalk between power supplies on the one hand, and on the other hand, the load capacity requirements of each linear regulator are reduced, making the linear regulator easy to design. The corresponding linear regulator can be adjusted based on the requirements of each module or circuit to achieve low power consumption and low noise.

[0056] In addition, the off-chip capacitor type linear regulator is mainly used to power digital modules and power amplifiers. For wearable devices, the power supply of the digital module of the system chip is generally 0.8V. Therefore, the off-chip capacitor type linear regulator voltage is connected to the second switching power supply circuit, or to the demand power supply in the multi-voltage power supply. Similarly, the non-off-chip capacitor type linear regulator powers the analog modules, RF modules and clock modules in the non-low-power modules. The power supply requirement of these modules is generally 1.1V~1.8V, so the non-off-chip capacitor type linear regulator is connected to the first switching power supply circuit to power the analog modules and RF modules. In this way, when the linear regulator is powered off, the power-off control can also be performed through the switching power supply circuit. In addition, Figure 5 LDO ARRAY means LDO array, which includes multiple LDOs.

[0057] Furthermore, combined with Fig. 9 The voltage required for each module in the present disclosure is explained. In the figure, area ① is the high voltage area, and its supply voltage is 1.8V. Area ② is the variable voltage area, and the voltage value range is 1.1V to 1.8V. The modules / circuits in this area only include the bandgap reference circuit (BANDGAP) and the linear regulator. Area ③ is the low voltage area, and the voltage value is 0.8V.

[0058] Optionally, the linear regulator without external capacitor is determined according to the corresponding load capacity and has the same FVF (Feedback Voltage Folding, flip voltage follower) structure. Here, the linear regulator without external capacitor uses low power consumption and sets the power supply of the linear regulator based on the load capacity. Thereby meeting the power supply requirements of different modules and achieving a balance between different loads, different areas and performances. By using the same FVF structure, the design of linear regulators with different load capacities can be reused, simplifying the design process.

[0059] Optionally, the on-chip power management system also includes a high-precision digital-to-analog converter (GPADC) for detecting the voltage of each linear regulator. Here, the output voltage of the linear regulator is detected by the high-precision digital-to-analog converter to determine whether the linear regulator is working properly. This enables real-time monitoring and self-regulation of the internal power supply, improving the reliability and stability of the system.

[0060] Optionally, the digital module includes a digital baseband DBB and a digital operation processor CORE, and an off-chip capacitor-type linear regulator supplies power to the digital baseband DBB and the digital operation processor CORE respectively.

[0061] Here, the digital module mainly includes the digital baseband DBB and the digital operation processor CORE, which are independently powered by an off-chip capacitor-type linear regulator (i.e. Figure 6 LDO_DBB and LDO_CORE in the MCU). This allows the digital processor to get rid of the high-power digital baseband operation (the digital baseband has high power consumption because it needs to process 500M bandwidth data). In this way, the digital processor can be used as the main control chip of the microcontroller to avoid the high power consumption problem caused by ultra-wideband (UWB). In this way, when the system chip is used as the main control chip or slave chip, the power supply solution can be adjusted from the application level to reduce power consumption.

[0062] As an example, when the DBB and Transceiver of a high-speed communication SOC consume high power, the high-power Transceiver and DBB can be powered off when the UWB chip is not transmitting or receiving. This allows the CORE to run at extremely low power consumption, allowing the system chip (i.e. SOC) to get rid of BLE (Bluetooth Low Energy) as the main control chip.

[0063] Optionally, the digital baseband DBB and the digital operation processor CORE are independently powered by a switching power supply circuit, or are independently powered by an external capacitor connected to a third voltage power supply (see Figure 7). Here, in the case of lower power consumption requirements, such as when applied to wearable devices, power supply through a switching power supply circuit or a third voltage power supply helps to reduce power consumption and is highly efficient.

[0064] Optionally, the on-chip power management system further includes an RC clock; when the system chip is powered on, the control clock circuit that always turns on the control module and the software running module is the RC clock circuit.

[0065] Here, the clocks of the low-power module and the non-low-power module are further separated, that is, the clock domain includes the RC clock and the XO clock. That is, when the system chip is powered on, the RC clock circuit (including the RC32K circuit and / or the RC38M circuit) is used. The RC clock circuit can start quickly, thereby achieving a fast startup of the power domain and a fast response of the switching power circuit, so as to achieve precise control of power consumption in different states. Optionally, when the system chip is powered on, the control clock circuit of the control module that is always turned on is the RC32K circuit; the control clock circuit of the software running module is the RC38M circuit.

[0066] In addition, when the system chip is working normally, the XO clock (including XO32K and / or XO38M) is used. After the system chip is stable, the XO clock provides an accurate clock signal to achieve more precise power consumption control.

[0067] In addition, in the embodiment of the present disclosure, the always-on control module is different from the always-on module. Figure 8 As shown in the figure, the always-on control module is the area of ​​the dotted box, and the other areas are software control modules. Among them, the always-on control module mainly includes a switching power supply circuit, a power switch, a bandgap reference circuit, an always-on controller AON_DIG, a low-power bandgap reference BGP_LP, a low-power linear regulator LDO_LP, etc.

[0068] Based on the above description, it can be known that in the embodiments of the present disclosure, the power supply of the low-power module and the non-low-power module is separated through the design of the power switch, the switching power supply circuit, the linear regulator, the clock circuit, etc. When the system chip is in a low-power state (such as the system chip is in sleep mode or deep sleep mode, etc.), the power supply of the high-power power domain can be cut off, and the low-power domain ensures the operation of the low-power module. In this way, when the wireless communication system chip is not in the transceiver working state, low-power applications can be realized. Furthermore, the power consumption of the power supply scheme is adjusted from the system level to achieve power consumption reduction.

[0069] In addition, the states of a power management system for a wireless communication system chip are described.

[0070] OFF state: shutdown state, the system chip is completely powered off.

[0071] Power on state: The intermediate process of the system chip from the OFF state to the IDLE state after the system chip is powered on.

[0072] IDLE state: The system chip is in the ready state. At this time, the digital operation processor (hereinafter referred to as CORE) works under the system clock (XO clock), the software starts running, and can enter other states according to the software configuration.

[0073] SLEEP state: The low-power modules and short-term storage units (hereinafter referred to as Retention Memory) in the system chip run at extremely low power consumption, and some status data are stored in Retention Memory; wait for the system chip to be awakened, and enter the IDLE state after awakening; among them, if the application requires RTC timing, the XO32K clock is also in working state.

[0074] DEEP SLEEP state: Retention Memory, XO32K and RC32K clocks are all turned off, and can only wait for external wake-up.

[0075] Transceiver state: The system chip is powered on and can receive and transmit RF signals.

[0076] Slave state: The system chip retains the external high-speed communication and DBB running state, and its own CORE enters the sleep state. The state control is controlled by the external master (the external master can be BLE for IOT applications or the CPU of wearable devices);

[0077] Master state: The system chip acts as the master control device, the CORE can run independently, and the DBB is turned on when the SOC needs to work; usually only the CORE is running as the software running core of the entire system.

[0078] Based on the above states, it can be seen that the system chip in the embodiment of the present disclosure can be freely adjusted to be used as a master chip or a slave chip for different applications. The low power module and the conventional module are powered separately to achieve the lowest power consumption adjustment under different application scenarios.

[0079] Based on the aforementioned power management system for wireless communication system chips, combined with Fig.10 The present disclosure provides a power-on control method for a wireless communication system chip, the method comprising:

[0080] S101, the system chip is powered on to enable the power-on reset module, the low-power reference circuit and the low-power linear regulator, to supply power to the RC32K circuit and the always-on module, and to enable the always-on module so that the always-on module runs under the RC32K clock.

[0081] S102, the always-on module sequentially enables the power switch, the switch power circuit, the bandgap reference circuit, the linear regulator of the 38M clock circuit, the linear regulator of the system clock phase-locked loop, and the linear regulator of the digital operation processor under the clock of RC32K.

[0082] S103, after the linear regulator works, the always-on module enables the RC38M clock circuit and the XO38M clock circuit in sequence, so that the digital operation processor configures the state of the system chip under the RC38M clock.

[0083] S104, the digital operation processor enables the system clock phase-locked loop under the RC38M clock, and after the clock of the system clock phase-locked loop works, switches the RC38M clock to the clock of the system clock phase-locked loop, and controls the RC38M clock circuit to be disabled.

[0084] Here, after the power supply of the system chip is powered on, the power-on reset module POR, the low-power reference circuit and the low-power linear regulator are enabled. The power-on reset module POR detects the power supply voltage. After the power supply voltage is detected and the voltage of the low-power reference circuit is stable, the low-power linear regulator supplies power to the always-on controller AON_DIG and the RC32K circuit, and then enables the RC32K circuit. After the RC32K circuit outputs the clock signal, the clock signal is transmitted to the always-on controller. As a result, the digital circuit of the always-on module (i.e., the always-on controller) runs under the RC32K clock.

[0085] The digital circuit of the always-on module (i.e., the always-on controller) enables the power switch, the switching power supply circuit, the bandgap reference circuit, the linear regulator of the 38M clock circuit (including the RC38M circuit and the XO38M circuit), the linear regulator of the system clock phase-locked loop, and the linear regulator of the digital operation processor in sequence under the RC32K clock. Among them, the switching power supply circuit and the bandgap reference circuit are enabled, and the switching bandgap energy converts the low-power power domain into a variable voltage domain, i.e., a high-power power domain, to power the subsequent bandgap reference circuit. Thus, the bandgap reference circuit works. The 38M clock circuit, the system clock phase-locked loop, and the linear regulator of the digital operation processor are enabled respectively to power the 38M clock circuit, the system clock phase-locked loop, and the digital operation processor.

[0086] After the linear regulator works normally, the RC38M circuit and the XO38M circuit are enabled. Because the RC38M circuit responds very quickly, when the RC38M circuit outputs a clock signal, the digital operation processor CORE is controlled to work under the RC38M clock. While waiting for the XO38M circuit to output a clock signal, the digital operation processor CORE runs to configure the state of the system chip. Among them, the state of configuring the system chip includes enabling FLASH and GPIO (enabling the power switch to power FLASH and GPIO in the previous text) so that the digital operation processor CORE can communicate with FLASH and external chips. Then read the data in FLASH and configure the system state one by one. And store the preset states such as the default value of the system clock phase-locked loop SYSPLL that has been configured in advance in the register.

[0087] After detecting that the clock of the XO38M circuit is established, the system clock phase-locked loop is enabled. Among them, the linear regulators of the system clock phase-locked loop SYSPLL include two, namely LDO_SYSPLL_ANA and LDO_SYSPLL_VCO. After the clock of the system clock phase-locked loop is established, the digital operation processor CORE switches from the RC38M clock to the clock of the system clock phase-locked loop, and controls the RC38M circuit to be disabled. In this way, the system chip enters the operation under the high-speed clock. After the system chip switches the clock, the RC38M circuit is controlled to be disabled. That is, the RC38M clock is turned off, which on the one hand avoids the energy consumption of the RC38M circuit, and on the other hand avoids the RC38M clock interfering with the XO38M clock. After the system chip runs at the high-speed clock, the entire software system runs. The system chip enters the idle state.

[0088] In addition, the digital operation processor controls whether the XO32K circuit is enabled according to the software configuration. Specifically, in the case of a cold start (i.e., the first power-on startup to the IDLE state), the digital operation processor controls the XO32K circuit to be enabled. In the case of a hot start (i.e., returning from the SELLP state to the IDEL state), the always-on controller determines the application environment according to the configuration information, and then configures whether to enable the XO32K circuit.

[0089] In this way, when the system chip is powered on, the RC clock is used for fast startup. Then, after the high-precision XO clock is established, the system clock phase-locked loop is enabled. Then the RC clock is switched to the clock of the system clock phase-locked loop for precise clock timing and timing. In this way, the power domain can be quickly started and the power consumption in different states can be accurately controlled. In addition, when the system chip is powered on, only the low-power control area works. And at this stage, the always-on controller of the system chip controls each module in the low-power control area. Then the software control area starts to work and the software of the system chip controls each module in this area. In this way, it helps to reduce the power consumption of the system chip.

[0090] In addition, in order to avoid the CORE being in an uncertain state when powered on and causing a large current draw, the linear regulator of the CORE is started after the linear regulators of the RC38M and XO38M are enabled for a first time period, wherein the first time period may be a clock time period.

[0091] After the linear regulator of the CORE is established, the RC38M circuit and the XO38M circuit are enabled at the same time. Specifically, the RC38M circuit and the XO38M circuit can be enabled at the rising edge of the linear regulator of the CORE. Alternatively, the RC38M circuit and the XO38M circuit can be enabled after waiting for one clock cycle after the linear regulator of the CORE is established.

[0092] Optionally, the always-on module of the system chip enables a power switch, including: enabling power switches corresponding to the input-output module and the flash memory storage unit.

[0093] Here, after the digital operation processor CORE runs, the state of the system chip is configured, including enabling FLASH and GPIO to communicate with external chips. Therefore, before enabling FLASH and GPIO, it is necessary to ensure the power supply of these two modules, that is, to enable the power switches corresponding to the input and output modules and the flash memory storage unit.

[0094] Optionally, after the system chip enables the digital operation processor to configure the state of the system chip under the RC38M clock, it also includes: the digital operation processor of the system chip configures whether to enable the regulated power supply and digital baseband of the digital baseband according to the operating state of the chip.

[0095] As mentioned above, when the UWB chip is not transmitting or receiving, the digital baseband DBB is powered off. Therefore, during hot start, whether to enable the regulated power supply and digital baseband of the digital baseband can be configured based on the operating state of the system chip. Specifically, when the system chip is in the transmitting and receiving state and the slave state, the regulated power supply and digital baseband of the digital baseband are enabled. When the system chip is in the master control state, the regulated power supply and digital baseband of the digital baseband are enabled when the system chip is working. When the system chip is not working or in other states, the regulated power supply and digital baseband of the digital baseband are not enabled. In this way, power consumption is reduced.

[0096] The above power-on control method describes the main nodes of the power-on sequence. Fig.11 ), the power-on control method is described in detail.

[0097] At T0: the power supply is powered on, the power-on reset circuit POR of the system chip detects the power supply voltage and enables the low-power bandgap reference circuit. After the output voltage of the low-power bandgap reference circuit is stable, the low-power linear regulator is enabled to supply power to the subsequent RC32K circuit and the always-on controller AON_DIG. After the output voltage of the low-power linear regulator is stable, the RC32K circuit is enabled.

[0098] Time T1: After the clock detection circuit detects the clock signal output by the RC32K circuit, it releases the reset signal of the always-on controller AON_DIG and transmits the clock to the always-on controller AON_DIG; AON_DIG starts to operate under the RC32K circuit.

[0099] Between T1 and T2, the controller AON_DIG is always turned on to read the value in OTP (the relevant configuration in OTP is pre-burned according to the application) to determine whether to enable XO32K and the switching power supply circuit (DC-DC-1 and DC-DC-2) based on the application environment.

[0100] Time T2: Enable XO32K and switching power supply circuit.

[0101] Between T2 and T3, the process waits for the switch power circuit to be established. After the detection circuit detects that the switch power circuit is established, the DC-DC_STB signal is sent to the always-on controller AON_DIG.

[0102] Time T3: AON_DIG receives the signal of the voltage establishment of the switching power supply circuit, namely the DC-DC_STB signal, and waits for one clock cycle.

[0103] Time T4: AON_DIG enables the bandgap reference BANDGAP circuit (wherein, the voltage establishment time of the BANDGAP circuit is about 1us to 5us, which does not exceed one clock cycle of RC32K).

[0104] At T5: the voltage of the BANDGAP circuit has been established, and AON_DIG enables the linear regulator of the 38M clock (i.e., LDO_38M_CLK) and the LDO of the system clock phase-locked loop SYSPLL (where the establishment time of several LDOs at T5 is about 10us to 20us, which will not exceed one clock cycle of RC32K). Wait for one clock cycle.

[0105] At T6: Enable the LDO of CORE; at this time, the LDO of the 38M clock and the LDO of the SYSPLL have been established. Enable XO_38M and RC_38M at the same time on this rising edge (or wait for one clock cycle before enabling the XO_38M and RC_38M clocks). Here, when the system chip is powered on for the first time, the LDO of the CORE is enabled while the LDO of the DBB is enabled. In the case of a hot start, whether to enable the LDO of the DBB and the DBB is configured based on the status of the system chip.

[0106] Time T7: The clock detection circuit detects that RC38M is established.

[0107] Time T8: The reset signal of System is released, and CORE starts to work under the RC38M clock; CORE controls the remaining circuits.

[0108] Between T8 and T9: CORE first enables FLASH and GPIO under RC38M clock, so that CORE can communicate with FLASH and external chips; then read the data in FLASH and configure the system status one by one. Then store the preset status such as the default value of SYSPLL configured in advance in the register. Wait for XO38M clock to be established. XO38M clock usually takes about 200us to 2ms, during which time CORE configures the system status.

[0109] Time T9: The signal XO38M_CLK_STB established by the XO38M clock is detected.

[0110] At T10: CORE enables SYSPLL and transmits the pre-configured SYSPLL configuration to SYSPLL, waiting for the SYSPLL clock to be established (where the input clock of SYSPLL is the XO38M clock).

[0111] Time T11: After detecting that the SYSPLL clock is established, the CORE starts to hold the status and store it in the cache.

[0112] At T12: the system chip switches the RC38M clock to the SYSPLL clock. The SYSPLL clock of this system is 499.2MHz, and the CORE is at a 4-divided 124.8MHz clock. The system chip enters the normal high-speed clock operation.

[0113] When the system completes the clock switching, the RC38M enable signal is pulled down to turn off the RC38M clock. After the system enters the high-speed clock, the entire software system starts running and the chip enters the idle (i.e. IDLE) state. The subsequent RF phase-locked loop circuit RF_PLL, the transmitting channel circuit TX, the receiving channel circuit RX, and the LDO power supply of the auxiliary high-precision digital-to-analog converter GPADC are all configured by the software according to the state requirements.

[0114] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. An on-chip power management system, characterized in that: Integrated in wireless communication system chip; the system includes: A first power switch is connected to a power supply and a universal input-output circuit in the system chip, and is used to control a power supply state of the universal input-output circuit; when the system chip is in a low power consumption state, the first power switch is controlled to power off the universal input-output circuit.

2. The on-chip power management system according to claim 1, characterized in that: Also includes: A second power switch, a third power switch and a fourth power switch are connected to the power supply and the programmable storage unit, the flash memory storage unit and the short-term storage unit respectively; When the system chip is in a low power consumption state, controlling the third power switch and the fourth power switch to be turned off to power off the flash memory storage unit and the short-term storage unit; And / or, after the programming of the programmable storage unit is completed, the second power switch is controlled to be disconnected to power off the programmable storage unit.

3. The on-chip power management system according to claim 1, characterized in that: Also includes: A first switching power supply circuit, used for converting a first voltage power supply into a second voltage power supply; A second switching power supply circuit, used for converting the first voltage power supply into a third voltage power supply; Among them, when the power supply is a voltage power supply, the first switching power supply circuit and the second switching power supply circuit respectively power the various modules of the system chip, and the first voltage power supply is the one voltage power supply; or, when the power supply is a plurality of voltage power supplies, the switching power supply circuit or the plurality of voltage power supplies are selected according to demand to power the various modules.

4. The on-chip power management system according to claim 3, characterized in that: Also includes: The bandgap reference circuit is connected to the output end of the switching power supply circuit and is used to provide a reference voltage and / or a reference current for modules other than the always-on module in the system chip.

5. The on-chip power management system according to claim 1, characterized in that: Also includes: A plurality of off-chip capacitor-type linear regulators for supplying power to digital modules and power amplifiers in the system chip; A plurality of linear regulators without external capacitors, used for supplying power to analog modules, radio frequency modules and clock circuits in the system chip; The switching state of the linear regulator is controlled to control the corresponding module to be turned off or on.

6. The on-chip power management system according to claim 5, characterized in that: The digital module includes a digital baseband and a digital operation processor, and the off-chip capacitor type linear regulator supplies power to the digital baseband and the digital operation processor respectively.

7. The on-chip power management system according to any one of claims 1 to 6, characterized in that: Also includes: RC clock circuit; When the system chip is powered on, the clocks of the always-on module and the software running module of the system chip are RC clocks.

8. A power-on control method for a wireless communication system chip, characterized in that: The on-chip power management system according to any one of claims 1 to 7, the method comprising: The system chip is powered on, the power-on reset module, the low-power reference circuit and the low-power linear regulator are enabled, the RC32K circuit and the always-on module are powered, and the always-on module is enabled so that the always-on module runs under the RC32K clock; The always-on module sequentially enables the power switch, the switching power supply, the bandgap reference circuit, the linear regulator of the 38M clock circuit, the linear regulator of the system clock phase-locked loop, and the linear regulator of the digital operation processor under the clock of the RC32K; After the linear regulator works, the RC38M clock circuit and the XO38M clock circuit are enabled in sequence, so that the digital operation processor configures the state of the system chip under the RC38M clock; The digital operation processor enables the system clock phase-locked loop under the RC38M clock, and after the clock of the system clock phase-locked loop works, switches the RC38M clock to the clock of the system clock phase-locked loop, and controls the RC38M clock circuit to be disabled.

9. The power-on control method according to claim 8, characterized in that: The enabling power switch comprises: Enable the power switches corresponding to the input and output modules and the flash storage unit.

10. The power-on control method according to claim 8 or 9, characterized in that: After the digital operation processor configures the state of the system chip under the RC38M clock, the method further includes: According to the operating status of the system chip, configure whether to enable the regulated power supply and digital baseband of the digital baseband.

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