An ultra-wideband latency transceiver chip operating in the 2-18 GHz range

Abstract

This invention discloses an ultra-wideband delay transceiver chip operating in the 2-18 GHz frequency band, applied in the field of radio frequency microwave integrated circuit technology. Addressing the high-frequency gain roll-off problem inherent in transceiver chips, this invention employs a shared-leg architecture where the transmitting and receiving modules share two driver amplifiers and an 80 ps delay unit. It includes a single-pole double-throw switch, a low-noise amplifier, a driver amplifier, a power amplifier, a delay unit, and a resistor-capacitor attenuation compensation network to compensate for additional delay attenuation, thereby resolving the additional insertion loss problem under different delay states. Simultaneously, an inductor-resistor gain equalizer is used to compensate for gain roll-off. Ultimately, this chip achieves a delay of 5 ps per unit delay and a maximum delay of 315 ps within the 2-18 GHz operating frequency band, while also exhibiting good switching time and good in-band gain flatness. The receiving channel input has a 1 dB compression better than -10 dBm and a gain better than -2 dB, while the transmitting channel output has a 1 dB compression better than 2 dBm and a gain better than 2 dB.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency microwave integrated circuit technology, and specifically relates to a broadband delay multifunctional chip. Background Technology

[0002] In recent years, with the widespread application of phased array technology in military radar and wireless communication systems, phased array systems with amplitude and phase control have become a core technology and have received increasing attention. The transceiver front-end (TLD) is a key component of a phased array system, responsible for switching RF signals between transmission and reception, and adjusting amplitude and phase. Traditional phased array antenna systems generally use phase shifters as the key module of the transceiver components. This system suffers from the problem of effective delay time varying with the operating frequency, leading to beam skewing in broadband signals. Replacing the phase shifter with a TTD can provide a constant delay response and compensate for dispersion over a wide bandwidth, alleviating the aforementioned problems in broadband systems such as high-resolution imaging radar. Therefore, the TTD has become a key module in broadband phased array antenna systems. On the other hand, due to the effects of numerous passive components such as inductors and capacitors, high-frequency gain roll-off is an unavoidable problem for transceiver chips. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention proposes an ultra-wideband latency transceiver chip operating in the 2-18GHz range. It adopts a shared-leg architecture where the transmitting and receiving modules share two driver amplifiers and an 80ps delay unit, thus realizing a multi-functional latency chip capable of switching between transmitting and receiving.

[0004] The technical solution adopted in this invention is as follows: an ultra-wideband latency transceiver chip operating in the 2-18GHz range, comprising a first receiving path, a second receiving path, a first transmitting path, a second transmitting path, and a common path; the first receiving path is connected to the second receiving path through the common path, and the first transmitting path is connected to the second transmitting path through the common path.

[0005] The antenna is connected to either the input terminal of the first receiving path or the output terminal of the second transmitting path via a first single-pole double-throw switch; the common path input terminal is connected to either the output terminal of the first receiving path or the output terminal of the first transmitting path via a second single-pole double-throw switch; the common path output terminal is connected to either the input terminal of the second transmitting path or the input terminal of the second receiving path via a third single-pole double-throw switch; the serial communication interface (COM) is connected to either the input terminal of the first transmitting path or the output terminal of the second receiving path via a fifth single-pole double-throw switch.

[0006] The first receiving path includes a low-noise amplifier and a first 160ps delay unit connected in sequence.

[0007] The second receiving path includes a first 5ps delay unit, a first gain equalizer, a first 10ps delay unit, a first driver amplifier, a second gain equalizer, a first 40ps delay unit, a third gain equalizer, and a first 20ps delay unit connected in sequence.

[0008] The first transmission path includes a second 20ps delay unit, a fourth gain equalizer, a second 40ps delay unit, a fifth gain equalizer, a second driver amplifier, a second 10ps delay unit, a sixth gain equalizer, and a second 5ps delay unit connected in sequence.

[0009] The second-end transmission path includes a second 160ps delay unit and a power amplifier connected in sequence.

[0010] The common path includes the seventh gain equalizer, the third driver amplifier, the eighth gain equalizer, the 80ps delay unit, the fourth driver amplifier, and the ninth gain equalizer, which are connected in sequence.

[0011] The beneficial effects of this invention are as follows: The ultra-wideband delay transceiver chip of this invention adopts a shared-leg architecture where the transmitting and receiving modules share two driver amplifiers and an 80ps delay unit. It includes single-pole double-throw switches (SPDT1, SPDT2, SPDT3, SPDT4), a low-noise amplifier (LNA), a driver amplifier (DA), a power amplifier (PA), a delay unit (True-Time Delayer, TTD), and a resistor-capacitor attenuation compensation network (included in the delay unit) to compensate for additional delay attenuation, thereby solving the problem of additional insertion loss under different delay states. Simultaneously, an inductor-resistor gain equalizer is used to compensate for gain roll-off. Ultimately, this chip can achieve a delay of 5ps per unit and a maximum delay of 315ps within the 2-18GHz operating frequency band, while also exhibiting good switching time and good in-band gain flatness. The receiving channel input has a 1dB compression better than -10dBm and a gain better than -2dB. The transmitting channel output has a 1dB compression better than 2dBm and a gain better than 2dB. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the circuit architecture of the present invention.

[0013] Figure 2 This is the schematic diagram of a four-stage distributed amplifier unit circuit.

[0014] Figure 3 This is the circuit schematic of a gain equalizer.

[0015] Figure 4This is a schematic diagram of a coupled all-through network circuit.

[0016] Figure 5 This is a schematic diagram of a single-pole double-throw switch circuit. Detailed Implementation

[0017] To facilitate understanding of the technical content of this invention by those skilled in the art, the following description, in conjunction with the accompanying drawings, further illustrates the invention.

[0018] The specific structure of the chip of the present invention is as follows: Figure 1 As shown, the receiving channel includes, in sequence: a single-pole double-throw (SPDT) switch, a low-noise amplifier (LNA), a 160ps delay unit, a gain equalizer, a driver amplifier (DA), a gain equalizer, an 80ps delay unit, a driver amplifier (DA), a gain equalizer, a single-pole double-throw (SPDT) switch, a 5ps delay unit, a gain equalizer, a 10ps delay unit, a driver amplifier (DA), a gain equalizer, a 40ps delay unit, a gain equalizer, a 20ps delay unit, and a single-pole double-throw (SPDT) switch; the transmitting channel is similar to the receiving channel, wherein:

[0019] (1) The low noise amplifier (LNA), driver amplifier (DA), and power amplifier (PA) all adopt a distributed amplifier structure, which are used to amplify the input signal to improve the system linearity, compensate the system gain, and amplify the output signal power, respectively.

[0020] For a distributed amplifier, the parasitic capacitance Cin at the input terminal of the CMOS transistor is connected in series with the on-chip inductor Lg to form the gate input artificial transmission line; the parasitic capacitance Cout at the output terminal of the CMOS transistor is connected in series with the on-chip inductor Ld to form the drain output artificial transmission line; the gate input and drain output artificial transmission lines are coupled through the transconductance of the CMOS transistor to amplify the input signal. A CMOS transistor circuit with this function is called a gain unit circuit. Figure 2As shown, the gain unit in this invention employs a stacked structure of three transistors M1, M2, and M3. Its output voltage swing is three times that of the common-source structure and 1.5 times that of the cascode structure, significantly improving output power. Resistors R1, R2, and R3 form a voltage divider network to provide gate voltage bias for M2 and M3, while the gate voltage bias for M1 is provided by an external switch control circuit. C1 and C2 are bypass capacitors used to remove stray currents. Lg1, Lg2, Lg3, Lg4, and Lg5, along with the transistor gate input parasitic capacitance, form the gate transmission line; Ld1, Ld2, Ld3, Ld4, and Ld5, along with the transistor drain output parasitic capacitance, form the drain transmission line, achieving good matching and thus bandwidth expansion. One end of the peaking inductor Ld is connected to VDD, and the other end is connected to the drain of M3 in the second-stage gain unit, avoiding gain roll-off issues. Ld1 and Lg5 are each terminated by a 50-ohm resistor Rd and Rg, respectively. Rd and Rg are then terminated by a large capacitor Cd and Cg grounded, thus achieving good port matching. The input and output ports are each connected to a DC blocking capacitor Cin and Cout, respectively, to isolate DC signals, resolve DC offset and DC coupling issues, and improve signal transmission quality.

[0021] Due to resistive parasitics between the gain units and on-chip inductors in practical applications, a attenuation effect occurs. Therefore, the gain of the distributed amplifier does not increase indefinitely with the increase of the number of cascaded gain units. Based on this characteristic and the relevant requirements of this invention, the distributed amplifier in this invention adopts a four-stage cascaded gain unit configuration. Simulation verification shows that in the 2-18GHz frequency band, the distributed amplifier has a gain greater than 15dB, a noise figure less than 4dB, an input / output port return loss better than 10dB, and an output P-1dB greater than 12dBm.

[0022] (2) The gain equalizer uses a resistor-capacitor-inductor network to improve the roll-off slope of insertion loss in delay chips. For example... Figure 3 As shown, resistor Re1 is connected in parallel with inductor Ce1, and the other ends of Re2 and Re3 are connected to the inductor and the parallel network of Re1 and Ce1. One end of the inductor is grounded. This gain amplifier has a higher insertion loss at low frequencies than at high frequencies, which is the opposite of the insertion loss trend of the delay chip. Therefore, the problem of excessive insertion loss slope of the delay chip can be solved simply by adjusting the parameters of each component in the circuit.

[0023] (3) The 160ps, 80ps, 40ps, 20ps, 10ps and 5ps delay units all adopt the following basic structure: Figure 4The diagram shows an All-Pass Network (APN) unit. A passive all-pass network delay unit is a second-order all-pass filter composed of two capacitors and two inductors, with mutual inductance between the inductors. This circuit achieves a good trade-off between delay and bandwidth, and features intrinsic input-output matching. All delay units in this invention employ this structure; different delay amounts can be achieved by changing the number of cascaded units according to the required delay specifications.

[0024] (4) The single-pole double-throw switch (SPDT) adopts Figure 5 In the structure shown, the gates of M1 and M2 are connected to the substrate via large resistors Rg and Rb, and their drains are connected to each other. The gates of M3 and M4 are connected to the substrate via large resistors Rg and Rb, and their drains are connected to the sources of M1 and M2, respectively. The sources of M3 and M4 are grounded, and their gates are connected to the gate resistor branches of M2 and M1, respectively, via resistor Rg. Port1, Port2, and Port3 serve as signal input / output terminals, each connected to an inductor and then led out. Vctr1 and Vctr2 serve as control voltage terminals, connected to the gates of M1 and M2 via resistor Rg, respectively. When Vctr1 is high and Vctr2 is low, transistors M1 and M4 are turned on, while transistors M2 and M3 are turned off. In this case, the single-pole double-throw (SPDT) switch circuit forms a signal path from Port1 to Port2. When Vctr1 is low and Vctr2 is high, transistors M1 and M4 are turned off, while transistors M2 and M3 are turned on. In this case, the SPDT insertion loss is better than 1.2 dB, and the input return loss is better than 25 dB.

[0025] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the scope of the claims of the invention.

Claims

1. An ultra-wideband latency transceiver chip operating in the 2-18 GHz range, characterized in that, It includes a first receiving path, a second receiving path, a first transmitting path, a second transmitting path, and a common path; the first receiving path is connected to the second receiving path through the common path, and the first transmitting path is connected to the second transmitting path through the common path. The antenna is connected to the input terminal of the first receiving path or the output terminal of the second transmitting path via a first single-pole double-throw switch; the common path input terminal is connected to the output terminal of the first receiving path or the output terminal of the first transmitting path via a second single-pole double-throw switch; and the common path output terminal is connected to the input terminal of the second transmitting path or the input terminal of the second receiving path via a third single-pole double-throw switch. The serial communication interface is connected to the input terminal of the first transmitting path or the output terminal of the second receiving path via a fourth single-pole double-throw switch. The first receiving path includes a low-noise amplifier and a first 160ps delay unit connected in sequence. The second receiving path includes a first 5ps delay unit, a first gain equalizer, a first 10ps delay unit, a first driver amplifier, a second gain equalizer, a first 40ps delay unit, a third gain equalizer, and a first 20ps delay unit connected in sequence. The first transmission path includes a second 20ps delay unit, a fourth gain equalizer, a second 40ps delay unit, a fifth gain equalizer, a second driver amplifier, a second 10ps delay unit, a sixth gain equalizer, and a second 5ps delay unit connected in sequence. The second-end transmission path includes a second 160ps delay unit and a power amplifier connected in sequence. The common path includes the seventh gain equalizer, the third driver amplifier, the eighth gain equalizer, the 80ps delay unit, the fourth driver amplifier, and the ninth gain equalizer, which are connected in sequence. The first 160ps delay unit, the first 5ps delay unit, the first 10ps delay unit, the 40ps delay unit, the first 20ps delay unit, the second 20ps delay unit, the first 40ps delay unit, the second 40ps delay unit, the second 10ps delay unit, the second 5ps delay unit, the second 160ps delay unit, and the 80ps delay unit are all implemented using magnetically coupled all-pass network units; The magnetically coupled all-pass network unit specifically includes: a fourth capacitor, a fifth capacitor, a fifth inductor, and a sixth inductor; the first terminal of the fourth capacitor serves as the input terminal of the magnetically coupled all-pass network unit, the first terminal of the fourth capacitor is connected to the first terminal of the fifth inductor, the second terminal of the fifth inductor is connected to the first terminal of the fifth capacitor, the second terminal of the fifth capacitor is grounded, the second terminal of the fourth capacitor serves as the output terminal of the magnetically coupled all-pass network unit, the second terminal of the fourth capacitor is connected to the first terminal of the sixth inductor, and the second terminal of the sixth inductor is connected to the first terminal of the fifth capacitor.

2. The ultra-wideband latency transceiver chip operating in the 2-18 GHz range according to claim 1, characterized in that, The low-noise amplifier, the first driver amplifier, the second driver amplifier, the third driver amplifier, the fourth driver amplifier, and the power amplifier all adopt a distributed amplifier structure.

3. The ultra-wideband latency transceiver chip operating in the 2-18 GHz range according to claim 2, characterized in that, The distributed amplifier structure specifically employs a four-stage cascaded gain unit, with each gain unit implemented using a CMOS transistor. Specifically: the parasitic capacitance at the input terminal of the CMOS transistor is connected in series with the on-chip inductor at the input terminal to form a gate input artificial transmission line; the parasitic capacitance at the output terminal of the CMOS transistor is connected in series with the on-chip inductor at the output terminal to form a drain output artificial transmission line; the gate input artificial transmission line and the drain output artificial transmission line are coupled through the transconductance of the CMOS transistor to amplify the input signal.

4. The ultra-wideband latency transceiver chip operating in the 2-18 GHz range according to claim 3, characterized in that, Each gain unit specifically includes: a first transistor, a second transistor, and a third transistor stacked together; The gate voltage bias of the first transistor is provided by an external switch control circuit; It also includes a voltage divider network consisting of a first resistor, a second resistor, and a third resistor, used to provide gate voltage bias for the second transistor and the third transistor.

5. The ultra-wideband latency transceiver chip operating in the 2-18 GHz range according to claim 4, characterized in that, The first to eighth gain equalizers all use a resistor-capacitor-inductor network, specifically including: a fifth resistor, a sixth resistor, a seventh resistor, a third capacitor, and a fifth inductor; the first terminal of the fifth resistor is connected to the first terminal of the third capacitor, and the second terminal of the fifth resistor is connected to the second terminal of the third capacitor. The first terminal of the fifth resistor serves as the input terminal of the gain equalizer. The first terminal of the fifth resistor is also connected to the first terminal of the sixth resistor, and the second terminal of the sixth resistor is connected to the first terminal of the fifth inductor. The second terminal of the fifth inductor is grounded. The first terminal of the fifth inductor is also connected to the first terminal of the seventh resistor, and the second terminal of the seventh resistor is connected to the second terminal of the fifth resistor. The second terminal of the fifth resistor serves as the output terminal of the gain equalizer.

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