An indirect measurement clock compensation device suitable for use in a distributed data acquisition system
By using indirect measurement methods and dynamic phase compensation algorithms, the clock synchronization problem of traditional direct measurement algorithms under high precision and low ADC sampling rate conditions is solved, realizing high-precision phase difference measurement and synchronization of each node in a distributed data acquisition system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2025-04-30
- Publication Date
- 2026-06-12
AI Technical Summary
Traditional direct phase difference measurement algorithms struggle to synchronize the sampling clocks of each sub-node in high-precision and low ADC sampling rate scenarios, and cannot capture rapidly changing phases. They also suffer from limitations in error and real-time performance.
An indirect measurement method is adopted, which uses a signal source, a power divider and a distributed data acquisition system to indirectly measure the phase difference through an optical fiber transmission link and a phase difference measurement module, and achieves high-precision clock synchronization between nodes through a dynamic phase compensation algorithm.
It achieves high-precision phase difference measurement and clock synchronization, which is suitable for scenarios with limited ADC sampling rates, improves sampling clock synchronization performance, and reduces error and real-time requirements.
Smart Images
Figure CN120454908B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the technical field of distributed data acquisition systems, and more specifically, relates to an indirect measurement clock compensation device suitable for distributed data acquisition systems. Background Technology
[0002] In modern industry and scientific research, the demand for high-precision, large-scale data acquisition is showing a continuous upward trend. However, traditional centralized data acquisition systems, due to their limited number of sampling channels, require multiple systems to operate simultaneously as the number of sampling signals increases, leading to reduced real-time performance and flexibility. Distributed data acquisition systems, with their highly flexible architecture and efficient resource allocation mechanisms, have become a key solution to meet this demand.
[0003] For distributed data synchronous acquisition systems, a crucial aspect is achieving synchronization of the sampling clocks of each child node. Achieving phase synchronization during the sampling clock synchronization process presents significant challenges. In the initial stages of a distributed data acquisition system's operation, if synchronizing the sampling clocks is difficult, then accurately measuring the phase difference between the sampling clocks of the child node system using relevant algorithms, and controlling the phase difference within a minimal range through effective phase compensation algorithms, has become a focal point of research in this field.
[0004] Traditional direct phase difference measurement algorithms have the following drawbacks:
[0005] 1. If the phase difference of the sampling clock is directly measured, then when the sampling clock frequency is F, according to the Nyquist sampling theorem, a sampling rate of 2F is required to acquire the signal without distortion. Therefore, it is not suitable for scenarios where the ADC sampling rate is limited.
[0006] 2. Direct measurement methods mostly require instruments such as oscilloscopes, and each measurement takes hundreds of microseconds, making it impossible to capture rapidly changing phases. Furthermore, due to the limited accuracy of the mathematical measurement functions of oscilloscopes, they are not suitable for high-precision phase difference measurement scenarios.
[0007] 3. Direct measurement methods require synchronous sampling by multi-channel high-speed ADCs, and clock jitter and skew introduce additional errors. Furthermore, data processing relies on high-speed DSPs or FPGAs, limiting real-time performance.
[0008] In summary, the direct phase difference measurement algorithm is difficult to apply to high-precision phase difference measurement scenarios, and it is also difficult to meet the application scenarios with low ADC sampling rates. Summary of the Invention
[0009] The purpose of this invention is to overcome the shortcomings of the prior art and provide an indirect measurement clock compensation device suitable for distributed data acquisition systems. By indirectly measuring the high-precision phase difference, the device ensures the synchronization accuracy of the sampling clock of each sub-node data acquisition system.
[0010] To achieve the above-mentioned objectives, the present invention provides an indirect measurement clock compensation device suitable for distributed data acquisition systems, characterized in that it comprises: a signal source, a power divider, and a distributed data acquisition system;
[0011] The signal source generates an analog input signal, which is then converted into n input signals by a 1:n power divider and input to the acquisition module of each sub-node data acquisition system.
[0012] The distributed acquisition system includes a master node data processing system and n child node data acquisition systems;
[0013] In the master node data processing system, an analog clock signal is first generated by a high-precision clock source, and then the analog clock signal is converted into a digital optical signal by an electro-optic modulator. The optical signal is converted into n optical signals by a 1:n optical splitter and input to each child node data acquisition system.
[0014] In each sub-node data acquisition system, the photoelectric modulator converts the optical signal into an electrical signal, and then sends the electrical signal as an external reference clock source to the clock module;
[0015] Each clock module generates a corresponding sampling clock signal based on the clock signal input from an external reference clock source. Then, under the sampling clock signal, it controls the sampling module to acquire the input signal, resulting in n sampling signals, denoted as x1, x2, ..., xn. i ,…,x n x i This represents the sampling signal from the acquisition module in the data acquisition system of the i-th child node;
[0016] The n sampling signals are transmitted to the phase difference measurement module of the master node data processing system through the optical fiber transmission link. Then, the phase difference between x1 and the other n-1 sampling signals is calculated using the first sampling signal x1 as the reference signal.
[0017] The master node data processing system then sends the measured phase difference back to the phase adjustment module of each child node data acquisition system. The phase adjustment module then adjusts the delay parameter according to the phase difference value, thereby delaying the input clock of the child node data acquisition system and outputting a synchronized clock signal.
[0018] The objective of this invention is achieved as follows:
[0019] This invention provides an indirect measurement clock compensation device suitable for distributed data acquisition systems. First, each sub-node data acquisition system transmits its acquired waveform signal to the master node data processing system via an optical fiber link. Then, a phase difference indirect measurement algorithm is used to achieve high-precision measurement of the sampling clock phase difference between each node, and a synchronous dynamic phase compensation algorithm is used to achieve high-precision clock synchronization between each node.
[0020] Meanwhile, the indirect measurement clock compensation device for distributed data acquisition systems of the present invention also has the following beneficial effects:
[0021] (1) This invention abandons the traditional hardware manual phase adjustment method and uses an indirect measurement method, that is, instead of directly measuring the sampling clock, it measures the phase difference of the data collected under the sampling clock, and sends the measured phase difference to the dynamic phase compensation module. The phase is adjusted according to the two key parameters of the minimum measured phase difference of the system and the phase compensation step value, so that the phase difference of each sampling clock is maintained at a certain accuracy value.
[0022] (2) The present invention cleverly uses an indirect measurement method to measure the phase difference with high precision, and uses a dynamic phase compensation algorithm to perform phase compensation, so that the accuracy of the phase difference value is maintained near a certain value, which greatly improves the sampling clock synchronization performance.
[0023] (3) The present invention adopts an indirect measurement method, which is different from the direct measurement method. When the sampling clock frequency is F, according to the Nyquist sampling theorem, the sampling rate needs to be 2F to collect the signal without distortion. Therefore, this method is more suitable for scenarios with limited ADC sampling rates. Attached Figure Description
[0024] Figure 1 This is a diagram of an indirect measurement clock compensation device applicable to a distributed data acquisition system according to the present invention;
[0025] Figure 2 This is a schematic diagram of the phase difference measurement module.
[0026] Figure 3 This is a schematic diagram of the phase adjustment module structure;
[0027] Figure 4 This is a simulation test diagram of the phase difference measurement algorithm. Detailed Implementation
[0028] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.
[0029] Example
[0030] Figure 1 This is a diagram of an indirect measurement clock compensation device applicable to a distributed data acquisition system according to the present invention.
[0031] In this embodiment, as Figure 1 As shown, the present invention provides an indirect measurement clock compensation device suitable for a distributed data acquisition system, comprising: a signal source, a power divider, and a distributed acquisition system;
[0032] like Figure 1 As shown, the signal source generates an analog input signal, which is then converted into four input signals by a 1:4 power divider and input to the acquisition module of each sub-node data acquisition system.
[0033] The distributed acquisition system consists of a master node data processing system and four child node data acquisition systems.
[0034] The master node data processing system includes a high-precision clock source that provides clock signals to the child node data acquisition system, as well as an electro-optic conversion circuit composed of an electro-optic modulator and an optical splitter; it also includes a phase difference measurement module for measuring phase difference.
[0035] like Figure 2 As shown, the phase difference measurement module includes a cos-sin module, a multiplication module, an addition / subtraction module, and an angle calculation module cascaded together, used to measure the phase difference between two signals.
[0036] In this embodiment, each sub-node data acquisition system has the same structure, including: an optoelectronic modulator, a clock module, an acquisition module, and a phase adjustment module;
[0037] Among them, such as Figure 3 As shown, the phase adjustment module includes: a control module, a delay line control unit, and an IDELAYE3 cascade unit.
[0038] In the master node data processing system, an analog clock signal is first generated by a high-precision clock source, and then the analog clock signal is converted into a digital optical signal by an electro-optic modulator. The optical signal is converted into four optical signals by a 1:4 optical splitter and input to each child node data acquisition system.
[0039] In each sub-node data acquisition system, the photoelectric modulator converts the optical signal into an electrical signal, and then sends the electrical signal as an external reference clock source to the clock module;
[0040] Each clock module generates a corresponding sampling clock signal based on the clock signal input from an external reference clock source. Then, under the sampling clock signal, it controls the sampling module to acquire the input signal, resulting in n sampling signals, denoted as x1, x2, x3, x4.
[0041] The four sampling signals are transmitted to the phase difference measurement module of the master node data processing system through an optical fiber transmission link. Then, the phase difference between x1 and the other three sampling signals is calculated using the first sampling signal x1 as the reference signal.
[0042] In this embodiment, sampling signal x1 and sampling signal x2 are used as examples for explanation, as follows:
[0043] Assuming the signal acquired by the sub-node data acquisition system is a cosine signal, where the reference signal x1(t) = cos(2πf0t + θ1), the signals acquired by other sub-node data acquisition systems have the same frequency magnitude but different phase. x2(t) = cos(2πf0t + θ2) is taken and entered into the phase difference measurement module for phase difference measurement.
[0044] When x1 and x2 enter the cos-sin module for Hilbert filtering transformation, orthogonal signals y1 and y2 are generated, denoted as y1(t) = sin(2πf0t + θ1) and y2(t) = sin(2πf0t + θ2).
[0045] The cos-sin module takes x1, x2, y1, and y2 as inputs to the multiplication module and calculates x1x2, x1y2, y1x2, and y1y2 respectively.
[0046] z1(t)=x1(t)*x2(t)=cos(2πf0t+θ1)*cos(2πf0t+θ2)
[0047] z2(t)=y1(t)*y2(t)=sin(2πf0t+θ1)*sin(2πf0t+θ2)
[0048] z3(t)=x1(t)*y2(t)=cos(2πf0t+θ1)*sin(2πf0t+θ2)
[0049] z4(t)=y1(t)*x2(t)=sin(2πf0t+θ1)*cos(2πf0t+θ2)
[0050] Then calculate x1x in the addition / subtraction module. i +y1y i ,x1y i -y1x i ,Right now:
[0051] m1(t) = z4(t) - z3(t)
[0052] =sin(2πf0t+θ1)*cos(2πf0t+θ2)-cos(2πf0t+θ1)*sin(2πf0t+θ2)
[0053] m1(t) = z2(t) + z1(t)
[0054] =sin(2πf0t+θ1)*sin(2πf0t+θ2)+cos(2πf0t+θ1)*cos(2πf0t+θ2)
[0055] Finally, the phase difference Δθ2 is calculated in the angle calculation module.
[0056]
[0057] Similarly, the phase differences Δθ3 and Δθ4 between x1,x3 and x1,x4 can be calculated respectively.
[0058] The master node data processing system then transmits the measured phase difference back to the phase adjustment module of each slave node data acquisition system. The control module in the phase adjustment module uses a PID control algorithm to proportionally and derivatively adjust the phase difference value, thereby dynamically converting the phase difference value into a delay line control signal. The specific adjustment formula is as follows:
[0059]
[0060] Where τ[i] represents the phase difference Δθ i The converted delay line control signal, T i K is the reference clock input to the data acquisition system of the i-th child node. p For proportional gain, K d For differential gain, K p =0.5, K d =0.02;
[0061] Next, the delay line control signal is processed by the delay line control unit to obtain the signal delay module tap value:
[0062]
[0063] Among them, f ref τ represents the reference clock frequency. step For single-tap delay of the signal delay module;
[0064] Finally, the cascaded signal delay module unit adjusts the input clock of the sub-node data acquisition system according to the tap value of the signal delay module of each delay line control signal, thereby outputting a synchronized clock signal.
[0065] In this embodiment, a 5-level IDELAYE3 cascade structure is adopted. The cascaded modules are dynamically instantiated using the Generate Statement in Hardware Description Language (HDL). The number of cascaded modules is defined by parameter N. The IDATAIN and DATAOUT ports of each module are automatically connected. By modifying the phase control word, the phase difference between the two signals is gradually reduced. Measurement continues until the phase difference between the two signals decreases to 1.9 ps, at which point the corresponding radian value is calculated to be 0.000122. Figure 4 As can be seen, the simulation test result is 0.0001220703125, and the measurement accuracy is 0.05763%. Therefore, the minimum phase difference that this indirect phase difference measurement algorithm can measure satisfies the minimum resolution of the system.
[0066] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.
Claims
1. An indirect measurement clock compensation device suitable for distributed data acquisition systems, characterized in that, include: Signal source, power divider, and distributed data acquisition system; The signal source generates an analog input signal, which is then converted into n input signals by a 1:n power divider and input to the acquisition module of each sub-node data acquisition system. The distributed data acquisition system includes a master node data processing system and n child node data acquisition systems; In the master node data processing system, an analog clock signal is first generated by a high-precision clock source, and then the analog clock signal is converted into a digital optical signal by an electro-optic modulator. The optical signal is converted into n optical signals by a 1:n optical splitter and input to each child node data acquisition system. In each sub-node data acquisition system, the photoelectric modulator converts the optical signal into an electrical signal, and then sends the electrical signal as an external reference clock source to the clock module; Each clock module generates a corresponding sampling clock signal based on the clock signal input from an external reference clock source. Then, under the sampling clock signal, it controls the sampling module to acquire the input signal, resulting in n sampling signals, denoted as x1, x2, ..., xn. i ,…,x n x i This represents the sampling signal from the acquisition module in the data acquisition system of the i-th child node; The n sampling signals are transmitted to the phase difference measurement module of the master node data processing system through the optical fiber transmission link. Then, the phase difference between x1 and the other n-1 sampling signals is calculated using the first sampling signal x1 as the reference signal. The master node data processing system then sends the measured phase difference back to the phase adjustment module of each child node data acquisition system. The phase adjustment module then adjusts the delay parameter according to the phase difference value, thereby delaying the input clock of the child node data acquisition system and outputting a synchronized clock signal.
2. The indirect measurement clock compensation device for a distributed data acquisition system according to claim 1, characterized in that, The master node data processing system includes a high-precision clock source that provides clock signals to the child node data acquisition system, and an electro-optic conversion circuit composed of an electro-optic modulator and an optical splitter; it also includes a phase difference measurement module for measuring phase difference. The phase difference measurement module includes a cos-sin module, a multiplication module, an addition / subtraction module, and an angle calculation module cascaded together, used to measure the phase difference between two signals.
3. The indirect measurement clock compensation device for a distributed data acquisition system according to claim 1, characterized in that, The data acquisition systems of the n sub-nodes have the same structure, including: a photoelectric modulator, a clock module, an acquisition module, and a phase adjustment module; The phase adjustment module includes a control module, a delay line control unit, and an IDELAYE3 cascade unit.
4. The indirect measurement clock compensation device for a distributed data acquisition system according to claim 1, characterized in that, The phase difference measurement module measures the phase difference using the following method: (4.1) Combine the sampled signal x1 with the sampled signal x i The cos-sin module performs Hilbert filtering to generate orthogonal signals y1, y2. i Where i = 2, 3, ..., n; (4.2) The cos-sin module converts the input signals x1 and x2 into a single signal. i Orthogonal signals y1, y i Input them together into the multiplication module to calculate x1x separately. i ,x1y i y1x i y1y i ; (4.3) Calculate x1x in the addition / subtraction module i +y1y i ,x1y i -y1x i ; (4.4) Calculate in the angle calculation module Thus, the phase difference Δθ can be calculated. i .
5. The indirect measurement clock compensation device for a distributed data acquisition system according to claim 1, characterized in that, The method by which the phase adjustment module adjusts the delay parameter based on the phase difference is as follows: (5.1) The phase difference value is dynamically converted into a delay line control signal through the control module; The phase difference is adjusted proportionally and derivatively using a PID control algorithm. The adjustment formula is as follows: Where τ[i] represents the phase difference Δθ i The converted delay line control signal, T i K is the reference clock input to the data acquisition system of the i-th child node. p For proportional gain, K d This is the differential gain; (5.2) The delay line control signal is processed by the delay line control unit to obtain the IDELAYE3 tap value: Among them, f ref τ represents the reference clock frequency. step For IDELAYE3 single tap delay; (5.3) The IDELAYE3 cascade unit adjusts the input clock of the sub-node data acquisition system according to the IDELAYE3 tap value of each delay line control signal, thereby outputting a synchronized clock signal.