IQ generator for a mixer
By designing an IQ generator that does not include a synthesizer and a divide-by-2 circuit, and using a delay path and calibration circuit to generate phase-quadrature signals, the problems of large area and high power consumption of traditional IQ generators are solved, realizing a low-power and small-area IQ generator suitable for high-frequency wireless communication.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MEDIATEK SINGAPORE PTE LTD
- Filing Date
- 2021-01-08
- Publication Date
- 2026-06-12
AI Technical Summary
Traditional IQ generators, which include a synthesizer with twice the carrier frequency and a divide-by-2 circuit, occupy a large chip area and increase power consumption, especially at high frequencies.
An IQ generator without synthesizer and 2-way divider circuit is designed. It generates phase-orthogonal I and Q signals through delay path and calibration circuit, and uses the output signal of test tone generator for phase adjustment. Low power consumption and small area are achieved through delay unit.
A low-power and small-chip-area IQ generator was achieved, reducing power consumption and making it suitable for high-frequency wireless communication, especially improving the efficiency of channel availability checking in the dynamically frequency-selected WiFi band.
Smart Images
Figure CN113098400B_ABST
Abstract
Description
Technical Field
[0001] This application generally relates to IQ generators. Background Technology
[0002] Wireless communication devices are typically deployed in wireless communication systems to provide communication services such as voice, multimedia, data, broadcasting, and messaging. In wireless communication devices such as mobile phones, IQ generators can provide quadrature signals represented by in-phase (I) and quadrature (Q) components. Summary of the Invention
[0003] It provides an IQ generator with lower power consumption and smaller die area.
[0004] Some embodiments relate to a signal generator for generating phase-orthogonal signals. The signal generator includes: a delay path configured to generate a signal from an input signal at a carrier frequency; and calibration circuitry configured to provide a control signal to the delay path based at least in part on the signal. The signal generator operates at a frequency less than twice the carrier frequency.
[0005] In some embodiments, the input signal of the carrier frequency comes from a test tone generator.
[0006] In some embodiments, the input signal of the carrier frequency includes the output signals of the test tone generator at two different phases.
[0007] In some embodiments, the input signal of the carrier frequency includes the output signal of the test tone generator at the same phase.
[0008] In some embodiments, the output signal of the test tone generator includes a pair of differential signals in the same phase.
[0009] In some embodiments, the delay path includes one or more delay units configured to adjust the transconductance of the respective delay unit based at least in part on a control signal from a calibration circuit.
[0010] In some embodiments, a delay unit in one or more delay units includes: a pair of transistors receiving an input signal of a carrier frequency, a back-to-back inverter coupled to the pair of transistors, and a delay unit; the delay unit is connected in series with the pair of transistors and is configured to adjust the transconductance of the delay unit at least in part based on a control signal from a calibration circuit.
[0011] In some embodiments, the calibration circuit includes a comparator configured to compare the average pulse width of a signal and to provide a control signal based at least in part on the comparison.
[0012] Some embodiments relate to a signal generator for generating phase-orthogonal signals. The signal generator includes one or more delay paths and calibration circuitry. The delay paths include input nodes for receiving an input signal at a carrier frequency and output nodes for providing the signal. The calibration circuitry includes input nodes for receiving the signal and output nodes for providing control signals to the one or more delay paths. The signal generator operates at a frequency less than twice the carrier frequency.
[0013] In some embodiments, the input signal of the carrier frequency comes from a test tone generator.
[0014] In some embodiments, the input signal at the carrier frequency includes a pair of differential signals in the same phase.
[0015] In some embodiments, one or more delay paths include a single delay path, and the output node of the calibration circuit provides a corresponding control signal to the single delay path.
[0016] In some embodiments, a single delay path includes multiple delay units controlled by corresponding control signals.
[0017] In some embodiments, the input signal of the carrier frequency has a 50% duty cycle, and the single delay path includes circuitry for receiving a signal with a 50% duty cycle and providing a signal with a 25% duty cycle.
[0018] In some embodiments, the input signal of the carrier frequency includes a first output signal of the test tone generator at a first phase and a second output signal of the test tone generator at a second phase different from the first phase.
[0019] In some embodiments, one or more delay paths include a first delay path for testing a first output signal of a tone generator and a second delay path for testing a second output signal of a tone generator.
[0020] In some embodiments, the output node of the calibration circuit is a first output node of the calibration circuit. The control signal is a first control signal. The first control signal is provided to the first delay path. The calibration circuit includes a second output node that provides a second control signal to the second delay path.
[0021] In some embodiments, the calibration circuit includes a direct current (DC) filter, which includes the input node of the calibration circuit.
[0022] Some embodiments relate to receiver circuitry. Receiver circuitry includes: a low-noise amplifier configured to receive and amplify an input signal at a carrier frequency; a test tone generator configured to generate a tone signal at the carrier frequency; a signal generator configured to generate phase-quasi-phase signals from the tone signal at the carrier frequency generated by the test tone generator; and a mixer configured to receive the amplified input signal and the signal.
[0023] In some embodiments, the receiver circuitry includes a switch coupled between the output node of the low-noise amplifier and a test tone generator. This switch is activated when a tone signal at the carrier frequency is used to suppress sideband signals relative to the carrier frequency.
[0024] The signal generator for generating phase-orthogonal signals in this embodiment of the invention does not require a synthesizer that generates signals at twice the carrier frequency, thus reducing power consumption.
[0025] These techniques can be used alone or in any suitable combination. The foregoing overview is provided by way of illustration and is not intended to be limiting. Attached Figure Description
[0026] The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component shown in the various figures is represented by the same numbers. For clarity, not every component is labeled in every figure. In the figures:
[0027] Figure 1 This is a schematic diagram of a 5GHz WiFi band with WiFi channels and radar-WiFi dynamic frequency selection (DFS) co-channel.
[0028] Figure 2 This is a schematic diagram of a DFS receiver according to some embodiments.
[0029] Figure 3 This is a block diagram of an IQ generator according to some embodiments, which receives input from a testtone generator (TTG) and outputs to a mixer.
[0030] Figure 4A , Figure 4B This is a schematic diagram of an IQ generator according to some embodiments, which receives multiple phase outputs of a TTG as inputs and outputs them to a mixer.
[0031] Figure 5 According to some embodiments Figure 4A and Figure 4B Timing diagrams for the TTG and IQ generators.
[0032] Figure 6 According to some embodiments Figure 4A and Figure 4B Timing diagrams for the TTG and IQ generators.
[0033] Figure 7 This is a schematic diagram of an IQ generator according to some embodiments, which receives a single-phase differential output of a TTG as input and outputs it to a mixer.
[0034] Figure 8 According to some embodiments Figure 7 Timing diagrams for the TTG and IQ generators. Detailed Implementation
[0035] This paper describes an IQ generator with lower power consumption and smaller die area. The inventors have recognized and acknowledged that conventional IQ generators consist of a synthesizer operating at twice the carrier frequency and a divide-by-2 circuit configured to convert the output of the synthesizer at twice the carrier frequency into a quadrature signal at the carrier frequency. The synthesizer, for example, an LC-based voltage-controlled oscillator (VCO), occupies a large die area and increases the cost of the chip including the IQ generator. In addition to occupying extra chip area, both the synthesizer and the divide-by-2 circuit, operating at twice the carrier frequency, consume significant power. This problem becomes even more pronounced when the carrier frequency increases to, for example, 6 GHz using 801.11ax or 801.11ac.
[0036] The inventors have developed an IQ generator with low power consumption and a small die area, thus eliminating the need for a synthesizer to generate a signal at twice the carrier frequency. In some embodiments, the IQ generator can be configured without any synthesizer and divide-by-2 circuitry.
[0037] In some embodiments, the IQ generator can be configured to convert one or more phase outputs of the test tone generator into phase-quadrature I and Q signals. In some embodiments, the IQ generator can receive a single-phase differential output of the test tone generator as input. In some embodiments, the IQ generator can receive multiple phase outputs of the test tone generator as input.
[0038] In some embodiments, the IQ generator may include one or more delay paths configured to generate I and Q signals. In some embodiments, the IQ generator may include a single delay path configured to receive one of the differential outputs of a test tone generator. In some embodiments, the IQ generator may include multiple delay paths configured to receive corresponding phase outputs of the test tone generator. In some embodiments, each delay path may receive a corresponding control signal such that the generated I and Q signals are orthogonal in phase. In some embodiments, the delay path may include at least two delay units configured to adjust the transconductance of the delay units based on the control signal.
[0039] In some embodiments, the IQ generator may include a calibration circuit configured to compare the average waveform bandwidth of the I signal with the average waveform bandwidth of the Q signal, and to provide one or more control signals to one or more delay paths such that the I signal and the Q signal are orthogonal in phase.
[0040] IQ generators may be included in applications used for Dynamic Frequency Selection (DFS). According to DFS, when operating in frequency ranges requiring DFS (including, for example, 5250-5350 and 5470-5725 MHz), WiFi transceivers (such as nxn MIMO transceivers) can identify co-channels where radar signals are present, in order to avoid using such channels occupied by radar signals. Figure 1A 5GHz WiFi band 100 is shown, which may include WiFi channels with bandwidth depending on the protocol used to access the channels. In the example shown, the channels in the first row (e.g., channels 36, 100, and 149 with center frequencies of 5180MHz, 5500MHz, and 5745MHz, respectively) have a bandwidth of 20MHz; the channels in the second row (e.g., channels 38, 102, and 151 with center frequencies of 5190MHz, 5510MHz, and 5755MHz, respectively) have a bandwidth of 40MHz; the channels in the third row (e.g., channels 42, 106, and 155 with center frequencies of 5210MHz, 5530MHz, and 5775MHz, respectively) have a bandwidth of 80MHz; and the channels in the fourth row (e.g., channels 50 and 114 with center frequencies of 5250MHz and 5570MHz, respectively) have a bandwidth of 160MHz. Some WiFi channels may also be occupied by radar signals, and are referred to as radar-WiFi DFS co-channels (e.g., channels 52-144 in the first row, channels 54-142 in the second row, channels 58-138 in the third row, and channels 50 and 114 in the fourth row). While DFS applications in WiFi systems improve system throughput, DFS enables WiFi transceivers to perform Channel Availability Check (CAC), which identifies WiFi channels without radar signals. When a radar signal is detected in a channel being used by the WiFi transceiver, the WiFi transceiver can switch to one of the WiFi channels identified by CAC as having no radar signal. Figure 1 TDWR is short for Terminal Doppler Weather Radar.
[0041] WiFi transceivers for DFS can include an IQ generator that provides quadrature signals to the mixer. (Figure) Figure 2 A schematic diagram of a DFS receiver 200 according to some embodiments is depicted. The DFS receiver 200 can receive an RF input signal RFin at a carrier frequency at an input node 202. The DFS receiver 200 may include a low noise amplifier (LNA) 204 configured to amplify the RF input signal while ensuring the signal-to-noise ratio of the RF input signal. Although the LNA shown is a single-ended cascaded LNA with integrated input matching and inductive source degeneration, any suitable LNA can be used.
[0042] DFS receiver 200 may include a test tone generator (TTG) 210 configured to generate a tone signal at a carrier frequency. The TTG 210 can be coupled to mixer 206 via switch 216. Although the shown switch is connected to the LNA output, this connection can be made at any LNA input. Although the shown mixer is a current-mode single-balanced passive I / Q mixer, any suitable mixer can be used. During WiFi link establishment, switch 216 can be turned on so that the tone signal generated by TTG 210 can be used for calibration and to suppress sideband signals relative to the carrier frequency. After the WiFi link is established, switch 216 can be turned off.
[0043] TTG 210 can be coupled to IQ generator 208. TTG 210 can send the output of one or more of its carrier frequencies to IQ generator 208. IQ generator 208 can be configured to convert the output of TTG 210 into quadrature signals (e.g., I+, I-, Q+, Q-) and provide the quadrature signals to mixer 206.
[0044] The DFS receiver 200 may include a transimpedance amplifier (TZA) and a low-pass filter (LPF) 212, which can be configured to drive an analog-to-digital converter (ADC) 214 for a successive-approximation-register (SAR) signal. In one embodiment, the SAR ADC may have a dynamic range of 65 dB and use a sampling frequency of 32 MHz per second. In some embodiments, the TZA+LPF 212 may be configured to have a fixed bandwidth (e.g., 80 MHz) such that a scan of the entire WiFi band can be completed within a desired time (e.g., 6 minutes). When a radar signal is detected in any fixed-bandwidth channel, the digital filter can divide the detected band containing the radar signal into multiple bands with smaller bandwidths (e.g., the 80 MHz band can be divided into four 20 MHz bands). The radar signal is then determined to be in one of the bands with smaller bandwidths. This configuration can save scanning time.
[0045] Figure 3This is a block diagram of portion 300 of a DFS receiver (e.g., DFS receiver 200). Portion 300 of the DFS receiver may include an IQ generator 208 that receives input from a TTG 210 and outputs to a mixer 206. The TTG 210 may include a ring oscillator 318, a buffer 320, and a feedback circuit 322. The output signal 324 of the buffer 320 may be fed back to the oscillator 318 via the feedback circuit 322. The feedback circuit 322 may be configured to detect the phase and frequency of the output signal 324 and generate a control signal 332 for the oscillator 318 based on the detected phase and frequency of the output signal 324. The ring oscillator 318 may be a TTG ICO (Current Control Oscillator), the buffer 320 may be an ICO_BUF, and the feedback circuit 322 may be an MMD (Multi-Modulus Frequency Divider) + PFD (Phase Frequency Detector).
[0046] IQ generator 208 can be configured to receive output signal 324 of TTG 210. IQ generator 208 may include a delay path 302 and calibration circuitry 304. Delay path 302 may include a delay buffer 306, IQ delay circuitry 308, duty cycle adjustment circuitry 310, and mixer buffer 312. IQ delay circuitry 308 may receive a signal from delay bufferry 306, which may receive output signal 324 of TTG 210. IQ delay circuitry 308 can be configured to generate IQ signal 326, which may be substantially orthogonal in phase. The duty cycle of IQ signal 326 is similar to the duty cycle of output signal 324 of TTG 210, for example, a 50% duty cycle as shown.
[0047] Duty cycle adjustment circuit 310 can be configured to modify the duty cycle of IQ signal 326 to generate IQ signal 328. IQ signal 328 can be amplified by mixer buffer 312 to IQ signal 330, which can be provided to mixer 206. IQ signals 328 and 330 can have duty cycles suitable for mixer 206 and / or suitable for calibration circuit 304. In the example shown, IQ signals 328 and 330 have a 25% duty cycle, reduced from the 50% duty cycle of IQ signal 326. Providing IQ signals with a 25% duty cycle to mixer 206 and calibration circuit 304 can reduce signal overlap during mixer operation.
[0048] The calibration circuit 304 may include a DC filter 314 and a low-power comparator operational amplifier 316. The DC filter 314 may be configured to provide the average pulse width (Vavg+ / -) of the IQ signal 330 to the comparator 316. The comparator 316 may be configured to generate a control signal 336, which is provided to the IQ delay circuit 308 such that the IQ delay circuit 308 can adjust its transconductance to keep the IQ signal 330 within the target phase error.
[0049] In some embodiments, the IQ generator may receive a single-phase differential output of the TTG as input. Figure 4A , Figure 4B A portion 400 of a DFS receiver is depicted, which may include an IQ generator 420 configured to receive a single-phase differential output (e.g., IN, INb) of a TTG 418 as input and provide an IQ signal 422 to a mixer 426. Figure 5 and Figure 6 Timing diagrams of TTG 418 and IQ generator 420 according to some embodiments are depicted.
[0050] The TTG 418 can generate multiple phase signals at carrier frequencies such as CK1, CK2, and CK3. In some embodiments, the TTG 418 can have a differential configuration, and each phase signal can include a pair of differential signals (e.g., IN and INb of CK3). Although some of the multiple phase signals such as CK1 and CK3 may have a phase difference close to 90 degrees, these signals may have large phase errors, such as... Figure 5 The shadowed edges of CK1, CK2, and CK3 in the image are shown, therefore they cannot provide a sufficient signal-to-noise ratio.
[0051] The IQ generator 420 can be configured to generate IQ signals with low phase error, for example, in Figure 5 The sharp edges of I and Q are shown in the diagram. The IQ generator 420 may include a delay path 402 and a calibration circuit 404. The delay path 402 may include a pair of delay buffers 406 configured to receive one of a pair of differential signals IN, INb, respectively. The delay path 402 may include a pair of I delay circuits 408A and 408B configured to receive one of the outputs of the pair of delay buffers 406, respectively, and provide a pair of differential I signals (e.g., 50% I+, 50% I-, possibly referring to a pair of differential I signals with a 50% duty cycle). The delay path 402 may include a pair of Q delay circuits 408C and 408D configured to receive one of the outputs of the pair of delay buffers 406, respectively, and provide a pair of differential Q signals (e.g., 50% Q+, 50% Q-).
[0052] One of the pair of I-delay circuits 408A, 408B and the pair of Q-delay circuits 408C, 408D can receive a control signal Vctrl, which can be configured to adjust the transconductance of the pair of delay circuits such that the IQ signals 422 are orthogonal in phase. In the illustrated example, each of the pair of I-delay circuits 408A and 408B includes a delay unit 424. The delay unit 424 may include a pair of transistors 424A, 424B sharing the same gate voltage, which can be the output of the pair of delay buffers 406 or the output of another delay unit. The delay unit 424 may include a pair of back-to-back inverters 424C, 424D coupled to the outputs of the pair of transistors 424A, 424B for phase matching. The delay unit 424 may include a delay unit 424E controlled by the control signal Vctrl. Although the shown delay unit 424E has one transistor, a delay unit may include one or more transistors. Although five delay units are shown, it should be understood that the I or Q delay circuit can include any suitable number of delay units, for example, at least two delay units. The number of delay units can be selected based on, for example, the carrier frequency. The higher the carrier frequency, the fewer delay units may be required.
[0053] Delay path 402 may include duty cycle adjustment circuitry 410, configured to receive a differential I signal pair (e.g., 50% I+, 50% I-) and a differential Q signal pair (e.g., 50% Q+, 50% Q-), modify the duty cycle of the differential I and Q signal pairs, and provide a new pair of differential I signals (e.g., 25% I+, 25% I-) and a new pair of differential Q signals (e.g., 25% Q+, 25% Q-). Duty cycle adjustment circuitry 410 may include four NAND gates (AD) configured to provide a new pair of differential I signals (e.g., 25% I+, 25% I-) and a new pair of differential Q signals (e.g., 25% Q+, 25% Q-). In the example shown, NAND gate A provides 25% I+ based on 50% I- and 50% Q+. NAND gate B provides 25% I- based on 50% I+ and 50% Q-. NAND gate C provides 25% Q+ based on 50% I+ and 50% Q+; NAND gate D provides 25% Q- based on 50% I- and 50% Q-.
[0054] The calibration circuit 404 can be configured to generate a control signal Vcrtl that is fed back to the delay path 402. The calibration circuit 404 can include a DC filter 414 and a low-power comparator operational amplifier 416. The DC filter 414 can be configured to generate the average pulse widths Vavg1 of a pair of new differential I signals (e.g., 25% I+, 25% I-) and the average pulse widths Vavg2 of a pair of new differential Q signals (e.g., 25% Q+, 25% Q-). The low-power comparator operational amplifier 416 can be configured to generate the control signal Vctrl based on the average pulse widths Vavg1 and Vavg2. The calibration circuit 404 can modify the value of the control signal Vctrl until the average pulse widths Vavg1 and Vavg2 are equal to each other. When T1 = T2, compared with T1 < T2 or T1 > T2, the equalization of the average pulse widths Vavg1 and Vavg2 makes the IQ signals orthogonal in phase, as Figure 6 shown, where T1 represents the pulse width of Q and T2 represents the pulse width of I.
[0055] In some embodiments, the IQ generator can receive multiple phase outputs of the TTG as inputs. Figure 7 Depicts a portion 700 of a DFS receiver, which can include an IQ generator 720 configured to receive multiple phase outputs (e.g., CK1, CK3) of a TTG 718 as inputs and provide IQ signals 722 to a mixer 706. Figure 8 Depicts Figure 7 a timing diagram of the IQ generator of
[0056] The IQ generator 720 can include delay paths 702I, 702Q for respective phase outputs of the TTG 718. The delay paths 702I, 702Q can be configured to convert the multiple phase outputs of the TTG 718 into orthogonal signals (e.g., I, Q). In some embodiments, the delay paths 702I, 702Q can be configured to be similar to Figure 4A and Figure 4B the delay path 402 in
[0057] The IQ generator 720 may include a calibration circuit 704, which may include a DC filter 714 and a comparator 716. The DC filter 714 may be configured to average the pulse widths of the IQ signals and / or generate a voltage V_comp representing the difference between the average pulse width of the I signal and the average pulse width of the Q signal. The comparator 716 may be configured to provide control signals Vt_I and Vt_Q to the delay paths 702I and 702Q, respectively, based on the output of the DC filter 714. As the calibration circuit 704, the calibration circuit 704 may modify the values of the control signals Vt_I and Vt_Q until the I and Q signals have equal average pulse widths.
[0058] Various changes can be made to the illustrative structures shown and described herein. For example, an IQ generator is described in conjunction with WiFi technology. An IQ generator can be used in conjunction with any suitable technology. As a specific example of a possible variation, an IQ generator can be used in conjunction with cellular technology.
[0059] The various aspects of the apparatus and techniques described herein can be used individually, in combination, or in various arrangements not specifically discussed in the embodiments described above. Therefore, their application is not limited to the details and arrangements of the components shown in the foregoing description or in the accompanying drawings. For example, an aspect described in one embodiment can be combined in any way with aspects described in other embodiments.
[0060] The terms “approximately,” “substantially,” and “approximately” can be used in some embodiments to mean within ±20% of the target value, in some embodiments within ±10% of the target value, in some embodiments within ±5% of the target value, and in some embodiments within ±2% of the target value.
[0061] The use of ordinal terms such as “first,” “second,” and “third” in claims to modify claim elements does not indicate any priority, precedence, or order of one claim element relative to another, or the order of execution of methods in time, but is only used to distinguish one claim element with the same name from another element with the same name (but using ordinal terms) to distinguish multiple claim elements.
[0062] Similarly, the wording and terminology used herein are for descriptive purposes and should not be considered limiting. The use of “including,” “contains,” or “has,” “includes,” “involves,” and variations thereof in this document is intended to cover the items listed thereafter and their equivalents, as well as other items.
Claims
1. A signal generator for generating signals with orthogonal phase, characterized in that: The signal generator includes a delay path, which includes: A pair of delay buffers, including a first delay buffer and a second delay buffer, the first delay buffer being configured to receive one of a pair of single-phase differential signals of a carrier frequency, and the second delay buffer being configured to receive the other of the pair of single-phase differential signals of the carrier frequency; A pair of I delay circuits, including a first I delay circuit and a second I delay circuit, are configured to receive the output of the first delay buffer and the output of the second delay buffer, respectively, and provide a pair of differential I signals with a duty cycle of 50%. A pair of Q-delay circuits, including a first Q-delay circuit and a second Q-delay circuit, are configured to receive the output of the first delay buffer and the output of the second delay buffer, respectively, and provide a pair of differential Q signals with a duty cycle of 50%. The duty cycle adjustment circuit is configured to receive the pair of differential I signals and the pair of differential Q signals with a duty cycle of 50%, and to provide a pair of differential I signals and a pair of differential Q signals with a duty cycle of 25%.
2. The signal generator according to claim 1, characterized in that, The differential signal of the single phase at the carrier frequency comes from the test tone generator.
3. The signal generator according to claim 1, further comprising: The calibration circuit includes an input node that receives the pair of differential I signals with a duty cycle of 25% and the pair of differential Q signals with a duty cycle of 25%. The calibration circuit is configured to compare the average pulse width of the pair of differential I signals with a duty cycle of 25% and the average pulse width of the pair of differential Q signals with a duty cycle of 25%, and to provide control signals to the delay path based at least in part on the comparison.
4. The signal generator according to claim 3, characterized in that, The calibration circuit includes a DC filter, and the DC filter includes the input node of the calibration circuit.
5. The signal generator according to claim 1, further comprising: The calibration circuit, the I-delay circuit or the Q-delay circuit, includes one or more delay units configured to adjust the transconductance of the delay units at least in part based on control signals from the calibration circuit.
6. The signal generator according to claim 5, characterized in that, The delay units in the one or more delay units include: A pair of transistors receive a signal at the carrier frequency. Back-to-back inverters, coupled to the pair of transistors, and A delay unit, connected in series with the pair of transistors, is configured to adjust the transconductance of the delay unit at least in part based on a control signal from the calibration circuit.
7. A receiver circuit, characterized in that, include: A low-noise amplifier is configured to receive an input signal at a carrier frequency and amplify the input signal; A test tone generator is configured to generate a tone signal at the carrier frequency; The signal generator according to any one of claims 1-6, wherein the tone signal of the carrier frequency is the differential signal of the pair of single phases of the carrier frequency in any one of claims 1-6; as well as A mixer configured to receive the amplified input signal and the pair of differential I signals with a duty cycle of 25% and the pair of differential Q signals with a duty cycle of 25%.
8. The receiver circuit according to claim 7, characterized in that, include: A switch is coupled between the output node of the low-noise amplifier and the test tone generator; The switch is turned on when the tone signal of the carrier frequency is used to suppress the sideband signal relative to the carrier frequency.