A data read-write method and device based on cooperation of DDR and SPI interfaces

Abstract

The application discloses a data read-write method and device based on cooperation of DDR and SPI interfaces, and the method comprises the following steps: acquiring state data sets of the interfaces, data transmission priority requirements, real-time bus access states and system timing coordination requirements; performing load evaluation according to the state data sets to obtain a classification result, combining the data transmission priority requirements to calculate the emergency degree of bus access, and obtaining a priority sequence; performing time slice allocation according to the priority sequence and the real-time bus access states to obtain an access right allocation scheme; executing the access right allocation scheme to generate a resource conflict resolution strategy; performing task re-allocation according to the resource conflict resolution strategy and the system timing coordination requirements to obtain a read-write task re-allocation result; monitoring the read-write task re-allocation result to obtain interface state change information, and performing optimization according to the read-write task re-allocation result and the interface state change information to obtain a multi-interface cooperative working configuration.

Description

Technical Field

[0001] This invention relates to the field of collaborative data interface reading and writing technology, and in particular to a data reading and writing method and apparatus based on collaborative DDR and SPI interfaces. Background Technology

[0002] Currently, in modern electronic systems, high-speed data processing and storage technologies have become core components of information processing architecture, and their performance directly determines the overall operating efficiency and responsiveness of the system. With the widespread deployment of data-intensive applications such as cloud computing, big data analytics, and real-time control, the demand for data processing systems that work collaboratively across multiple interfaces has increased significantly. These systems need to simultaneously process multiple types of data streams from different data sources, while maintaining stable storage and access performance while ensuring high-speed transmission.

[0003] In a current technology, common data processing schemes treat data streams from different interfaces as independent modules, lacking a unified state management and coordination mechanism. There is no effective state tracking or information sharing capability between interfaces, and bus access permission allocation strategies often rely on static configuration or fixed priority rules, which cannot adapt to dynamically changing load demands. When data traffic surges or interface load distribution becomes uneven, existing systems are prone to resource contention and access conflicts, leading to data processing sequence disruptions and increased response latency.

[0004] Existing technologies have the problem of being unable to perform dynamic priority scheduling and bus access optimization based on the real-time status of the interface. Summary of the Invention

[0005] This invention provides a data read / write method and apparatus based on the collaborative use of DDR and SPI interfaces to solve the problem in the prior art that dynamic priority scheduling and bus access optimization cannot be performed based on the real-time status of the interface.

[0006] Firstly, to address the aforementioned technical problems, this invention provides a data read / write method based on the coordinated use of DDR and SPI interfaces, comprising:

[0007] Obtain the status data set of each interface, data transmission priority requirements, real-time bus access status, and system timing coordination requirements.

[0008] Based on the cache occupancy rate characteristics and queue length change characteristics in the state data set, threshold judgment and trend analysis are performed to complete the load assessment and obtain the interface load level classification results.

[0009] Based on the classification results and the data transmission priority requirements, the urgency of bus access is calculated and priority scheduling is performed to obtain the priority ranking sequence of the interfaces.

[0010] Based on the priority sorting sequence and the real-time bus access status, time slices are allocated to obtain a bus access permission allocation scheme.

[0011] The access permission allocation scheme is executed, and the data transmission status of each interface is extracted during the execution process to generate performance indicators. Based on the performance indicators, resource contention is detected and a resource conflict resolution strategy is generated.

[0012] Based on the resource conflict resolution strategy and the system timing coordination requirements, tasks are reallocated to obtain the read / write task reallocation results.

[0013] Monitor the running status of the interface corresponding to the read / write task reassignment result, obtain interface status change information, and dynamically optimize the priority parameters based on the read / write task reassignment result and the interface status change information to obtain the optimized multi-interface collaborative working configuration.

[0014] Preferably, the step of performing threshold judgment and trend analysis based on the cache occupancy characteristics and queue length change characteristics in the state data set to complete the load assessment and obtain the interface load level classification result includes:

[0015] Based on the cache occupancy information in the status data set, the cache occupancy of each interface is compared with a preset occupancy threshold.

[0016] If the cache utilization rate exceeds a preset utilization rate threshold, the interface is marked as a potentially high-load interface, and a preliminary interface list is obtained;

[0017] Based on the processing queue length data in the preliminary interface list, the changing trend of queue length is detected within a continuous sampling period to obtain a high-load candidate list;

[0018] Based on the high load candidate list, calculate the load assessment score, determine the interface load level based on the load assessment score, and generate load level classification data;

[0019] In the load level classification data, an abnormal status identifier is recorded for the interface that is determined to be in a high load state, and the interface load level classification result is obtained.

[0020] Preferably, the step of calculating the urgency of bus access and performing priority scheduling based on the classification results and data transmission priority requirements to obtain the priority ranking sequence of the interfaces includes:

[0021] Based on the load assessment score in the classification results and the data transmission priority requirements, the data processing latency of each interface is extracted to obtain the data processing latency;

[0022] If the data processing delay exceeds a preset processing delay threshold, the interface corresponding to the delay exceeding the preset processing delay threshold is marked as an emergency scheduling object, and an emergency scheduling list is obtained.

[0023] Based on the emergency dispatch list, each interface is scored for the urgency of bus access, an adjusted weight value is generated, and temporary priority is determined according to the weight value from high to low.

[0024] Based on the temporary priority sorting, the bus resource allocation status is dynamically adjusted to obtain an updated resource allocation scheme, and the response speed of each interface is evaluated based on the updated resource allocation scheme.

[0025] If the response speed does not reach the preset response speed threshold, a bus resource allocation ratio correction operation is performed to obtain the interface priority sorting sequence.

[0026] Preferably, the step of allocating time slices based on the priority sorting sequence and the real-time bus access status to obtain a bus access permission allocation scheme includes:

[0027] Based on the priority sorting sequence and the real-time bus access status, the access conditions of high-priority interfaces are determined, and a temporary permission allocation list is generated when the preset idle conditions are met.

[0028] For the temporary permission allocation list, the access time slices are dynamically adjusted, and an adjusted time slice allocation table is generated in combination with preset allocation rules;

[0029] Based on the time slice allocation table, the bus access permissions are checked and the time slice allocation is corrected to obtain the permission allocation record;

[0030] Based on the permission allocation record, the bus status and interface request information are continuously tracked, and the permission allocation scheme is optimized to obtain the bus access permission allocation scheme.

[0031] Preferably, the step of executing the access permission allocation scheme, extracting the data transmission status of each interface during execution, generating performance indicators, and detecting resource contention and generating resource conflict resolution strategies based on the performance indicators includes:

[0032] The access permission allocation scheme is executed, the data transmission performance of each interface is extracted, and performance indicators are generated.

[0033] Based on the performance indicators, analyze the resource contention between interfaces and the data flow conflict records to detect whether there are multiple interfaces simultaneously requesting access to the same storage area;

[0034] When an access conflict is detected, a resource contention analysis report is generated, and the conflicting interfaces are sorted according to preset conflict judgment rules to form a temporary access control scheme.

[0035] Based on the aforementioned temporary access control scheme, the resource allocation ratio is adjusted to obtain the updated allocation record;

[0036] Based on the performance changes of the update allocation record tracking interface, determine whether the conflict has been completely resolved and generate a resource conflict resolution strategy.

[0037] Preferably, the step of reallocating tasks according to the resource conflict resolution strategy and the system timing coordination requirements to obtain the read / write task reallocation result includes:

[0038] Based on the resource conflict resolution strategy and the system timing coordination requirements, the current workload and processing capacity of each interface are analyzed, and interfaces whose processing capacity exceeds the preset saturation threshold are marked as high-load interfaces, and an interface load distribution mapping table is generated.

[0039] Based on the interface load distribution mapping table, the data queue to be processed of the high-load interface is split into tasks, and read and write tasks with divisible characteristics are extracted to obtain a set of task packages to be transferred.

[0040] Based on the set of tasks to be transferred, idle interfaces are matched to identify transferable tasks and establish task transfer paths to form a task redistribution scheme.

[0041] Based on the task redistribution scheme, the task migration is performed, and the task allocation status record is updated after the migration is completed to obtain the read / write task redistribution result.

[0042] Preferably, the step of monitoring the interface running status corresponding to the read / write task reassignment result, obtaining interface status change information, and dynamically optimizing priority parameters based on the read / write task reassignment result and the interface status change information to obtain an optimized multi-interface collaborative working configuration includes:

[0043] Based on the load fluctuation data and status change records of the read / write task redistribution result monitoring interface, a list of interfaces to be optimized and interface status change information are obtained.

[0044] Extract the current access permission allocation data from the list of interfaces to be optimized, and re-evaluate the priority weights based on the current access permission allocation data to generate an updated priority ranking table;

[0045] Based on the priority sorting table and the interface status change information, the access permissions of high-load interfaces are adjusted, and an adjustment permission allocation scheme is formed.

[0046] The proposed adjustment permission allocation scheme is applied to the interface collaborative work process, and load fluctuations are monitored to obtain an optimized multi-interface collaborative work configuration.

[0047] Secondly, the present invention provides a data read / write device based on DDR and SPI interface collaboration, comprising:

[0048] The data acquisition module is used to acquire the status data set of each interface, data transmission priority requirements, real-time bus access status, and system timing coordination requirements.

[0049] The load assessment module is used to perform threshold judgment and trend analysis based on the cache occupancy rate characteristics and queue length change characteristics in the status data set, complete the load assessment, and obtain the interface load level classification results.

[0050] The priority sorting module is used to calculate the urgency of bus access and perform priority scheduling based on the classification results and the data transmission priority requirements, so as to obtain the priority sorting sequence of the interfaces.

[0051] The access permission module is used to allocate time slices according to the priority sorting sequence and the real-time bus access status to obtain the bus access permission allocation scheme.

[0052] The resource conflict module is used to execute the access permission allocation scheme, extract the data transmission status of each interface during the execution process, generate performance indicators, and detect resource contention and generate resource conflict resolution strategies based on the performance indicators.

[0053] The task allocation module is used to reallocate tasks according to the resource conflict resolution strategy and the system timing coordination requirements, and obtain the read and write task reallocation results.

[0054] The collaborative configuration module is used to monitor the running status of the interface corresponding to the read / write task reassignment result, obtain interface status change information, and dynamically optimize priority parameters based on the read / write task reassignment result and the interface status change information to obtain the optimized multi-interface collaborative working configuration.

[0055] Thirdly, the present invention also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the data read / write method based on DDR and SPI interface coordination described in any one of the above.

[0056] Fourthly, the present invention also provides a computer-readable storage medium comprising a stored computer program, wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to perform the data read / write method based on DDR and SPI interface coordination described above.

[0057] Compared with the prior art, the present invention has the following beneficial effects:

[0058] (1) This invention collects the operating status of each interface in real time under the collaborative environment of DDR and SPI interfaces, and establishes a dynamic evaluation mechanism by combining cache occupancy rate, processing queue length and data transmission priority requirements, so that the system can accurately reflect the transient changes in interface load. Compared with the scheduling method with fixed priority and lack of state awareness in the prior art, this method can adjust the scheduling order in a timely manner when the interface load changes suddenly or the task piles up, ensuring that high-priority interfaces always get a suitable bus access opportunity, thereby significantly reducing the latency risk of high-priority tasks and improving the real-time performance of key data channels and the overall system throughput.

[0059] (2) This invention introduces a performance-driven resource contention detection mechanism, which can quickly identify concurrent access conflicts of multiple interfaces to the same storage area after access permission allocation is executed, and dynamically generate resource conflict resolution strategies based on contention intensity and task urgency. This strategy can not only respond quickly after a conflict occurs, but also reallocate tasks in conjunction with system timing requirements during resource reallocation. This ensures that high-load interfaces are relieved of pressure in a timely manner while avoiding long-term idleness of low-load interface resources, achieving efficient utilization of bus bandwidth and storage channels, and improving the stability and continuous processing capability of the system in a high-concurrency environment.

[0060] (3) After task redistribution is completed, this invention continues to monitor interface status changes and incorporates load fluctuations and historical performance data into the priority weight reassessment process. This allows permission adjustments to no longer rely solely on static policies but to automatically optimize based on dynamic changes in interface status. Through this cyclical feedback mechanism, the system can maintain the rationality of priority policies and the balance of collaborative configurations during long-term operation, effectively reducing bottlenecks caused by load imbalances and ensuring stable operation of multi-interface collaborative work and continuous optimization of overall response performance. Attached Figure Description

[0061] Figure 1 This is a schematic diagram of the data read / write method based on DDR and SPI interface collaboration provided in the first embodiment of the present invention;

[0062] Figure 2 This is a schematic diagram of the data read / write device structure based on DDR and SPI interface collaboration provided in the second embodiment of the present invention. Detailed Implementation

[0063] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0064] Reference Figure 1 The first embodiment of the present invention provides a data read / write method based on the coordinated use of DDR and SPI interfaces, including the following steps:

[0065] S11, obtain the status data set of each interface, data transmission priority requirements, real-time bus access status and system timing coordination requirements.

[0066] S12, based on the cache occupancy rate characteristics and queue length change characteristics in the state data set, perform threshold judgment and trend analysis, complete load assessment, and obtain the interface load level classification result;

[0067] S13, Based on the classification results and the data transmission priority requirements, calculate the urgency of bus access and perform priority scheduling to obtain the priority ranking sequence of the interfaces;

[0068] S14. Based on the priority sorting sequence and the real-time bus access status, time slices are allocated to obtain a bus access permission allocation scheme.

[0069] S15, execute the access permission allocation scheme, extract the data transmission status of each interface during the execution process, generate performance indicators, and detect resource contention and generate resource conflict resolution strategies based on the performance indicators;

[0070] S16. Based on the resource conflict resolution strategy and the system timing coordination requirements, the tasks are reallocated to obtain the read / write task reallocation result.

[0071] S17, monitor the interface running status corresponding to the read / write task reassignment result, obtain interface status change information, and dynamically optimize the priority parameters based on the read / write task reassignment result and the interface status change information to obtain the optimized multi-interface collaborative working configuration.

[0072] In step S11, it is necessary to obtain the status data set of each interface, data transmission priority requirements, real-time bus access status, and system timing coordination requirements, including:

[0073] In a specific embodiment, the system first needs to acquire the status data set of each interface, data transmission priority requirements, real-time bus access status, and system timing coordination requirements. Specifically, the interface status data set reflects the workload and resource usage of the DDR and SPI interfaces in the current cycle, including parameters such as cache utilization, processing queue length, data transmission rate, and response latency. To achieve real-time data acquisition, a status acquisition module is set in the interface controller in this embodiment. This module obtains relevant data by periodically reading the counter register and status flag bits, and stores the acquisition results in a shared status buffer with a sampling period of 10ms. For example, in a certain acquisition, the cache utilization of the DDR interface is 72%, the queue length is 128, the data transmission rate is 1.6GB / s, and the response latency is 50ns, while the cache utilization of the SPI interface is 45%, the queue length is 64, the data transmission rate is 80MB / s, and the response latency is 150ns. These data are summarized to form the interface status data set for that cycle.

[0074] Based on this, the system further acquires data transmission priority requirements to reflect the different tasks' demands for data latency and bandwidth. Priorities can be predefined as multi-level configurations during system initialization, such as levels 1 to 5, where 1 is the highest priority. In this embodiment, when an image acquisition task and a log storage task simultaneously occupy the SPI interface, the former is marked as priority 1 and processed first in the scheduler, while the latter is marked as priority 4 and executed later, thus satisfying the service quality requirements of different tasks.

[0075] The system also needs to acquire bus access status in real time to reflect bus occupancy and wait queue length. This status can be read directly from the status register in the bus arbiter. For example, when the bus is occupied by a DDR interface and the bandwidth utilization rate is 70%, the arbiter will return an "occupied" status, along with information about the interfaces requesting access in the wait queue. This information is used in the subsequent priority scheduling process to determine whether access permissions can be immediately allocated to high-priority interfaces.

[0076] Finally, system timing coordination requirements need to be determined to maintain the synchronization of multi-interface data streams within the frame period or sampling period. For example, in a real-time video processing system, the timing coordination requirement is that each frame transmission must be completed within 33ms and the inter-frame time deviation must not exceed 5ms. When the SPI interface latency is detected to exceed this range, the system will dynamically adjust the resource allocation ratio of the DDR and SPI interfaces in subsequent scheduling stages to ensure the overall frame synchronization and timing consistency of the processing. By comprehensively acquiring the above four types of information, the system establishes a baseline for the operational status of multi-interface collaborative work, providing accurate input data for subsequent load assessment, priority scheduling, and time slice allocation.

[0077] In step S12, based on the cache occupancy characteristics and queue length change characteristics in the state data set, threshold judgment and trend analysis are performed to complete the load assessment and obtain the interface load level classification results, including:

[0078] Based on the cache occupancy information in the status data set, the cache occupancy of each interface is compared with a preset occupancy threshold.

[0079] If the cache utilization rate exceeds a preset utilization rate threshold, the interface is marked as a potentially high-load interface, and a preliminary interface list is obtained;

[0080] Based on the processing queue length data in the preliminary interface list, the changing trend of queue length is detected within a continuous sampling period to obtain a high-load candidate list;

[0081] Based on the high load candidate list, calculate the load assessment score, determine the interface load level based on the load assessment score, and generate load level classification data;

[0082] In the load level classification data, an abnormal status identifier is recorded for the interface that is determined to be in a high load state, and the interface load level classification result is obtained.

[0083] In a specific embodiment, the system needs to determine whether the cache utilization rate exceeds a preset threshold based on the interface status data set obtained in step S11, and perform a comprehensive evaluation in conjunction with the trend of queue length changes, thereby obtaining the interface load classification result. Specifically, the cache utilization rate information in the status data set is first compared against a threshold. Cache utilization rate refers to the percentage of currently used space in the interface cache area relative to the total cache capacity, used to measure the current storage pressure of the interface. The system is designed to preset a threshold, such as 80%. When the cache utilization rate of an interface reaches or exceeds this threshold, the system marks the interface as a potentially high-load interface and forms a preliminary interface list. In this embodiment, if the DDR interface cache utilization rate is 85% and the SPI interface cache utilization rate is only 50%, the DDR interface will be added to the preliminary list, while the SPI interface will not be included in subsequent detection.

[0084] Based on this, the system continuously samples the processing queue length data of each interface in the initial interface list to determine the trend of queue length changes. Queue length reflects the number of data tasks currently waiting to be processed by the interface. When the queue length continuously increases over multiple sampling periods, it indicates that the processing pressure on the interface is constantly increasing. In this embodiment, the system sets the sampling period to 10ms and collects queue length data for five consecutive periods. If the queue length of the DDR interface gradually increases from 100 to 200 without a significant decrease, then the interface is identified as a high-load candidate interface and added to the high-load candidate list.

[0085] Subsequently, the system calculates a load assessment score based on the high-load candidate list. This score is jointly determined by the cache utilization rate and the queue length change trend, and can be calculated using a weighted method, for example, a cache utilization rate weight of 0.6 and a queue length change trend weight of 0.4. In the embodiment, if the DDR interface cache utilization rate is 85% (score 0.85 × 0.6 = 0.51) and the queue length growth trend index is 0.8 (score 0.8 × 0.4 = 0.32), then its comprehensive load assessment score is 0.83, corresponding to a high load level.

[0086] Finally, the system generates load level classification data based on the load assessment score, identifying interfaces of high, medium, and low load levels respectively. It also records anomaly flags for interfaces determined to be in a high-load state for subsequent scheduling. In this embodiment, the DDR interface is determined to be high-load and marked with an anomaly flag, while the SPI interface is marked as low-load. Through this series of assessment steps, the system generates interface load level classification results, providing a basis for subsequent priority scheduling.

[0087] It's important to note that the preset cache utilization threshold is primarily used to distinguish whether an interface is in a potentially high-load state. This threshold is determined based on the interface cache capacity, historical data access patterns, and the system's tolerable latency range. For example, during the design phase, multiple stress tests might determine 80% as the critical value; that is, when the interface cache usage exceeds 80% of its total capacity, the interface is considered to have a high-load risk. In specific applications, if a DDR interface has a total cache capacity of 256MB, and real-time monitoring shows its utilization rate reaches 85% (approximately 218MB), the system immediately marks this interface as a potentially high-load interface and initiates the subsequent queue trend detection process. If an SPI interface has a total cache capacity of 32MB and a real-time utilization rate of 50% (approximately 16MB), this interface will not trigger a high-load flag. This threshold setting balances the capacity characteristics of different interfaces with system stability, ensuring that subsequent load assessments have a unified standard and engineering feasibility.

[0088] In step S13, based on the classification results and data transmission priority requirements, the urgency of bus access needs to be calculated and priority scheduling performed to obtain the interface priority ranking sequence, including:

[0089] Based on the load assessment score in the classification results and the data transmission priority requirements, the data processing latency of each interface is extracted to obtain the data processing latency;

[0090] If the data processing delay exceeds a preset processing delay threshold, the interface corresponding to the delay exceeding the preset processing delay threshold is marked as an emergency scheduling object, and an emergency scheduling list is obtained.

[0091] Based on the emergency dispatch list, each interface is scored for the urgency of bus access, an adjusted weight value is generated, and temporary priority is determined according to the weight value from high to low.

[0092] Based on the temporary priority sorting, the bus resource allocation status is dynamically adjusted to obtain an updated resource allocation scheme, and the response speed of each interface is evaluated based on the updated resource allocation scheme.

[0093] If the response speed does not reach the preset response speed threshold, a bus resource allocation ratio correction operation is performed to obtain the interface priority sorting sequence.

[0094] In one specific embodiment, the data processing latency of each interface is first extracted and calculated by combining the load assessment score in the load level classification results and the priority requirements of the tasks. Data processing latency refers to the time required for an interface to complete the transmission from receiving a data request, and is composed of the buffer queuing time and the bus arbitration delay. In this embodiment, the load assessment score of the DDR interface is 0.85, and its corresponding image acquisition task priority is 1, resulting in a calculated processing latency of 4ms; while the load assessment score of the SPI interface is 0.5, and its corresponding log task priority is 3, resulting in a processing latency of 12ms.

[0095] When the system determines that the data processing latency of a certain interface exceeds a preset latency threshold, it marks that interface as an emergency scheduling object, creating an emergency scheduling list. The preset latency threshold can be set according to the application scenario. For example, in a high-speed video processing scenario, the threshold is set to 8ms. When the latency of the SPI interface is 12ms, it is included in the emergency scheduling object, while the DDR interface remains in normal status because its latency is below the threshold. The emergency scheduling list is used as input for subsequent bus access urgency scoring.

[0096] After generating the emergency dispatch list, the system scores the urgency of bus access based on the interface information in the list and calculates adjusted weight values. The scoring process considers both the severity of interface load and the real-time requirements of task priorities, ultimately forming a temporary priority ranking. In this embodiment, the SPI interface, due to its high latency and relatively low task priority, has its weight increased to 0.7 in the emergency scoring, while the DDR interface maintains its weight of 0.9, resulting in a temporary ranking of DDR first, followed by SPI.

[0097] In this embodiment, the weighting calculation of the bus access urgency score adopts a multi-index weighted summation method, linearly combining three key indicators: interface load score, task real-time score, and cache usage score. The calculation formula is as follows:

[0098] Total weight = Interface load score × 0.5 + Task real-time performance score × 0.3 + Cache usage score × 0.2.

[0099] Among them, the interface load score is calculated based on the current task queue length and average processing rate of the interface, ranging from 0 to 1; the task real-time score is set according to the priority of task type, with high real-time tasks taking a value close to 1 and low real-time tasks taking a value close to 0; the cache usage score is calculated by the ratio of the interface cache usage rate to a preset threshold, and when the cache usage rate is close to or exceeds 80%, the score approaches 1.

[0100] For example, in a scheduling scenario, if the SPI interface has a load score of 0.8 (severe task backlog), a real-time score of 0.5 (low real-time tasks), and a cache usage score of 0.6, then the total weight is 0.8×0.5 + 0.5×0.3 + 0.6×0.2 = 0.67, rounded to 0.7. Meanwhile, if the DDR interface has a load score of 0.9, a real-time score of 0.9, and a cache usage score of 0.8, then the total weight is 0.9×0.5 + 0.9×0.3 + 0.8×0.2 = 0.88, rounded to 0.9. Using this method, the system can accurately reflect the urgency of interface access under the combined effect of multiple indicators, providing a basis for subsequent temporary priority ranking.

[0101] Subsequently, the system dynamically adjusts the bus resource allocation status according to the temporary priority sorting, generates an updated resource allocation scheme, and evaluates the response speed of each interface under the scheme. If the evaluation results show that the response speed does not reach the preset response speed threshold, for example, if it is set to 5ms but the SPI interface is still 7ms, the system will further adjust the resource allocation ratio, such as increasing the time slice ratio allocated to the SPI interface to 30%, in order to balance the overall response performance.

[0102] Through the aforementioned iterative adjustments and corrections, the system ultimately generates a priority ranking sequence for the interfaces, providing a clear scheduling basis for subsequent time slice allocation steps. This priority ranking not only considers the current interface load and task importance but also comprehensively evaluates dynamically changing access conflicts and response characteristics, ensuring that bus resources can be rationally allocated in high-concurrency scenarios with multiple interfaces.

[0103] It should be noted that the processing latency threshold is used to determine whether an interface task needs to be added to the emergency scheduling list. This threshold is determined based on the interface type, task real-time requirements, and historical performance data. For example, in a high-speed video processing system, to ensure frame synchronization, the processing latency threshold is set to 8ms. When the system detects a DDR interface processing latency of 6ms, it maintains normal scheduling because it is below the threshold; however, if the SPI interface processing latency is 12ms, exceeding the 8ms threshold, it is immediately marked as an emergency scheduling object and enters the subsequent bus access urgency scoring stage. By limiting this threshold, it is possible to prevent all interfaces from entering an emergency scheduling state, ensuring that resource scheduling is concentrated on the objects that require the highest priority processing.

[0104] It should be noted that the response speed threshold is used to verify whether the interface response performance meets the standards after dynamically adjusting the resource allocation scheme. This threshold is set with reference to the system's real-time performance indicators and interface characteristics. For example, in industrial control applications, to ensure imperceptible latency for critical data during bus switching, the response speed threshold can be set to 5ms. After the updated resource allocation scheme is applied, if the DDR interface response speed is 3ms, it is considered to meet the performance requirements; if the SPI interface response speed is 7ms, exceeding the preset 5ms threshold, a secondary resource allocation ratio correction is triggered, increasing the SPI interface time slice to 30% to reduce its latency. This judgment and correction mechanism ensures that resource allocation optimization is not only based on priority ranking but also continuously verifies actual performance.

[0105] In step S14, time slices need to be allocated based on the priority sorting sequence and the real-time bus access status to obtain a bus access permission allocation scheme, including:

[0106] Based on the priority sorting sequence and the real-time bus access status, the access conditions of high-priority interfaces are determined, and a temporary permission allocation list is generated when the preset idle conditions are met.

[0107] For the temporary permission allocation list, the access time slices are dynamically adjusted, and an adjusted time slice allocation table is generated in combination with preset allocation rules;

[0108] Based on the time slice allocation table, the bus access permissions are checked and the time slice allocation is corrected to obtain the permission allocation record;

[0109] Based on the permission allocation record, the bus status and interface request information are continuously tracked, and the permission allocation scheme is optimized to obtain the bus access permission allocation scheme.

[0110] In one specific embodiment, the access conditions for high-priority interfaces are first determined by combining the priority ranking sequence and the real-time bus access status. The priority ranking sequence reflects the importance and urgency of the interface in the current cycle, while the real-time bus access status indicates whether the bus is idle or occupied, as well as the currently occupied interface identifier and bandwidth utilization. In this embodiment, the bus access status is updated periodically by the bus arbitrator, for example, by reading the status register every 5ms. If the register shows that the bus occupancy rate is less than 20% and no high-priority interface is transmitting, the system determines that it is in an allocable state. When it is detected that the DDR interface is ranked first in the priority and the bus is idle, the system immediately generates a temporary permission allocation list, which records the task identifier, bandwidth requirement, and expected occupancy duration of the interface.

[0111] After generating a temporary permission allocation list, the system dynamically adjusts access time slices. A time slice is the basic unit of bus scheduling, used to limit the maximum duration each interface can occupy within a scheduling cycle. Preset allocation rules are determined based on interface priority and task type; for example, a minimum occupancy rate of 40% may be specified for high-priority interfaces, 20% for medium-priority interfaces, and 10% for low-priority interfaces. In a typical scheduling scenario, if the DDR interface bandwidth requirement is 80%, the SPI interface requires 30%, and the total available system bandwidth is 100%, then the system allocates 60% to the DDR interface, 20% to the SPI interface, and reserves 20% as a burst buffer to prevent new high-priority requests from occurring in subsequent cycles.

[0112] After the initial time slice allocation is completed, the system needs to verify and correct bus access permissions based on the adjusted time slice allocation table. The verification includes three aspects: first, checking for violations of minimum guarantee rules, such as the allocation ratio of low-priority interfaces not being lower than 5%; second, checking for delays in high-priority interfaces due to insufficient resources; and third, assessing whether the allocation ratio leads to excessively low bus utilization or excessively high risk of sudden conflicts. If the verification results show that the allocation ratio of a certain interface cannot meet its minimum performance requirements—for example, an SPI interface allocation of 20% results in a response time exceeding 7ms, while the system's preset response time upper limit is 5ms—the system will automatically adjust the time slice ratio, increasing the SPI interface allocation to 30% while simultaneously reducing the allocation ratio of low-priority interfaces.

[0113] After generating the corrected permission allocation record, the system continuously tracks the bus status and interface request information, and dynamically optimizes the allocation scheme based on the monitoring results. The continuous tracking process is implemented through a status acquisition module, with the acquisition cycle synchronized with the scheduling cycle; for example, interface status data is updated every 10ms. If a sudden drop in the load of an interface is detected, or a new high-priority task is added to the request queue, the system will recalculate the priority ranking and reallocate time slices in the next scheduling cycle. In this embodiment, in a scenario where multiple interfaces concurrently write to storage, after the DDR interface completes its current task, it releases bandwidth, and the length of the SPI interface's pending queue immediately increases. In the next cycle, the system increases its priority weight and adjusts its time slice to 40% to ensure that its response latency remains within the set range.

[0114] Through the above steps, the system ultimately generates a bus access permission allocation scheme that comprehensively considers priority, real-time bus status, and resource utilization. This scheme not only ensures the real-time performance of high-priority tasks but also avoids long-term starvation of low-priority interfaces through dynamic adjustments, while improving the overall bus utilization efficiency and system stability under sudden loads.

[0115] It should be noted that the preset idle condition is used to determine whether the current bus can be immediately allocated to a high-priority interface. This condition is set by comprehensively considering factors such as bus bandwidth utilization, the status of currently executing tasks, and the length of the waiting queue. During the design phase, a bandwidth utilization threshold, such as 20%, is determined through performance testing. That is, when the bus utilization is below 20% and no high-priority tasks are executing, the bus is considered to be in an idle state. Furthermore, it is required that there are no pending requests with higher priorities in the waiting queue to avoid reverse resource allocation. In the embodiment, if the arbitrator detects that the DDR interface has completed its task, the bus utilization has dropped to 15%, and there are only low-priority SPI requests in the waiting queue, the system considers the idle condition met and can immediately allocate permissions to the DDR interface or the next high-priority task, achieving a rapid response. It should also be noted that the preset allocation rules are used to guide the minimum or maximum bandwidth ratio that different priority interfaces can obtain during time slice allocation. The rules are set based on interface characteristics and task real-time requirements; for example, the minimum time slice ratio for high-priority interfaces can be defined as 40%, for medium-priority interfaces as 20%, and for low-priority interfaces as 10%. In addition, maximum percentage limits can be specified, such as no single interface exceeding 70% of the total bandwidth, to reserve resources for handling sudden requests. In the embodiment, when the DDR interface is marked as high priority and the current bandwidth requirement is 80%, the system allocates 60% of the time slice according to the rules; when the SPI interface is marked as medium priority and the requirement is 30%, it allocates 20% of the time slice; the remaining 20% ​​of the time slice is reserved as a dynamic buffer to compensate for newly entered high-priority tasks or resolve sudden conflicts in the next scheduling cycle. This allocation method satisfies the real-time requirements of critical tasks while ensuring the basic transmission needs of low-priority tasks and the flexible scheduling capability of bus resources.

[0116] In step S15, the access permission allocation scheme needs to be executed, and during the execution process, the data transmission status of each interface is extracted to generate performance indicators. Based on the performance indicators, resource contention is detected and a resource conflict resolution strategy is generated, including:

[0117] The access permission allocation scheme is executed, the data transmission performance of each interface is extracted, and performance indicators are generated.

[0118] Based on the performance indicators, analyze the resource contention between interfaces and the data flow conflict records to detect whether there are multiple interfaces simultaneously requesting access to the same storage area;

[0119] When an access conflict is detected, a resource contention analysis report is generated, and the conflicting interfaces are sorted according to preset conflict judgment rules to form a temporary access control scheme.

[0120] Based on the aforementioned temporary access control scheme, the resource allocation ratio is adjusted to obtain the updated allocation record;

[0121] Based on the performance changes of the update allocation record tracking interface, determine whether the conflict has been completely resolved and generate a resource conflict resolution strategy.

[0122] First, the system initiates bus scheduling according to the time slice allocation table output in step S14, and monitors the performance parameters of each interface in real time during task execution to generate performance metrics. These performance metrics mainly include three aspects: data transfer rate (e.g., MB / s or GB / s), interface response latency (i.e., the time from sending an access request to completing data transfer), and cache occupancy change rate (reflecting the dynamic changes in interface cache pressure). These data are collected in real time through the counting register and status flags inside the interface controller and written to the performance monitoring buffer at fixed intervals (e.g., 5ms or 10ms). Taking a typical application as an example, after obtaining 60% time slice allocation, the DDR interface has a data transfer rate of 1.4GB / s and a latency of 40ns, while the SPI interface has a transfer rate of 70MB / s and a latency of 180ns at 20% time slice allocation. These data are directly used as the basic input for subsequent conflict detection.

[0123] After obtaining performance metrics, the system further analyzes resource contention between interfaces and data flow conflict records. Resource contention is primarily determined based on the memory address range accessed by the interfaces and the request timestamp. For example, if multiple interfaces access the same or overlapping memory address range within the same time window (e.g., DDR and SPI simultaneously requesting the 0x2000–0x4000 range), an access conflict is considered to exist. To avoid false positives, the system sets conflict determination thresholds; for example, an address overlap ratio exceeding 50% and a duration exceeding 2ms are considered a valid conflict. Furthermore, the system also incorporates latency changes and rate drops from performance metrics as auxiliary criteria for conflict determination. For instance, if an interface experiences a latency increase exceeding 30% and a rate drop exceeding 20%, the conflict is considered to have a real impact on system performance.

[0124] It should be noted that the address overlap ratio is calculated by performing intersection and union operations on the storage address ranges requested by each interface within the same time window. The system first extracts the request address ranges of the conflicting interfaces, calculates the length of their overlapping interval, and then compares this length with the overall request interval length to quantify the degree of overlap. The overall request interval can be based on the union length of the request intervals of the two interfaces or the request length of the main high-priority interface, chosen flexibly according to the application scenario. The calculation formula is: Address overlap ratio = Overlapping interval length ÷ Baseline interval length × 100%.

[0125] Furthermore, the time window is used to determine the persistence of overlapping accesses. That is, only when multiple interfaces continuously access the same or overlapping memory address ranges within the same monitoring period is the overlap counted as a valid conflict. For example, if the overlap ratio exceeds 50% in two consecutive sampling periods (1ms per period), the conflict is confirmed; otherwise, if the overlap only occurs momentarily, it is considered invalid.

[0126] For example, the DDR interface request range is 0x2000–0x4000 (8KB), the SPI interface request range is 0x3000–0x5000 (8KB), the intersection of the two is 0x3000–0x4000 (4KB), and the union length is 12KB. Therefore, the overlap ratio = 4KB ÷ 12KB = 33%. When this ratio exceeds the preset 50% threshold within 2ms, the system will mark this as a valid conflict event and record it in the conflict log for subsequent priority adjustment.

[0127] When an access conflict is detected, the system generates a resource contention analysis report. This report details the identifier of the conflicting interface, the conflicting storage area, the duration of the conflict, and its impact on performance metrics. Based on this report, the system sorts the conflicting interfaces according to preset conflict judgment rules, forming a temporary access control scheme. The preset conflict judgment rules comprehensively consider interface task priority, current load level, and the degree of conflict impact. For example, in a video processing scenario, if the DDR interface belongs to a high-priority real-time task while the SPI interface belongs to a low-priority background storage task, and the latency of the DDR interface increases by more than 50% during the conflict, the temporary management scheme will prioritize ensuring access to the DDR interface and appropriately reduce the time slice ratio of the SPI interface to mitigate the impact of the conflict.

[0128] Subsequently, the system adjusts the bus resource allocation ratio based on the temporary access permission management scheme and generates updated allocation records. A gradual adjustment strategy can be adopted during the adjustment process, such as adjusting by no more than 10% of the total time slice each time, to avoid excessive allocation fluctuations that could cause system instability. In this embodiment, when the SPI interface is determined to be of low priority due to a conflict, its time slice ratio is reduced from 20% to 15%, while the time slice ratio of the DDR interface is increased from 60% to 65%, with the remaining time slices used to buffer future burst requests.

[0129] Finally, after updating the allocation records, the system continuously tracks interface performance changes to determine whether the conflict has been completely resolved. If conflict indicators (such as latency recovering to below a preset threshold or a conflict rate below 5%) indicate that resource contention has been eliminated, a final resource conflict resolution strategy is generated and written to the system scheduling log for subsequent optimization reference. If the conflict remains unresolved, the system will continue to optimize the allocation ratio in the next scheduling cycle until a stable state is reached. Through this process, the system achieves real-time detection and dynamic resolution of conflicts while executing the permission allocation scheme, enabling bus resources to maintain an efficient and fair allocation state under high concurrency conditions with multiple interfaces.

[0130] It should be noted that the preset conflict determination rule is used to identify whether multiple interfaces simultaneously requesting bus or storage areas constitute a valid resource conflict, and provides a basis for conflict sorting and subsequent resource adjustments. This rule combines multiple indicators such as the storage address overlap ratio, request time overlap duration, latency increase ratio, and data rate decrease magnitude to ensure that the determination result accurately reflects the actual conflict while avoiding misjudgments due to instantaneous fluctuations. Specifically, the system first compares the storage address ranges requested by each interface. If the overlap ratio exceeds 50% and the duration exceeds 2ms, it is initially marked as a potential conflict. Then, performance indicators are further analyzed. If the average latency of the marked interface during this time period increases by more than 30% compared to the baseline latency, and the data transfer rate decreases by more than 20%, then the conflict is confirmed. For example, in a multi-interface access process, the DDR interface and the SPI interface simultaneously request the address range 0x2000–0x4000, with the overlap region accounting for 60% of the total request range, and the conflict lasting for 3ms. Upon detecting the conflict, the system found that the DDR interface latency increased from the baseline of 40ns to 60ns (a 50% increase), and the SPI interface speed decreased from 80MB / s to 60MB / s (a 25% decrease). These conditions met the dual thresholds for latency and speed in the decision-making rules. Therefore, the system confirmed a resource conflict and included it in the resource contention analysis report for subsequent priority ranking and time slice adjustment. This decision-making rule allows the system to accurately distinguish between normal bandwidth fluctuations and conflict events that genuinely affect task timing, thereby improving the targeting and efficiency of conflict handling.

[0131] In step S16, task reallocation needs to be performed according to the resource conflict resolution strategy and the system timing coordination requirements to obtain the read / write task reallocation result, including:

[0132] Based on the resource conflict resolution strategy and the system timing coordination requirements, the current workload and processing capacity of each interface are analyzed, and interfaces whose processing capacity exceeds the preset saturation threshold are marked as high-load interfaces, and an interface load distribution mapping table is generated.

[0133] Based on the interface load distribution mapping table, the data queue to be processed of the high-load interface is split into tasks, and read and write tasks with divisible characteristics are extracted to obtain a set of task packages to be transferred.

[0134] Based on the set of tasks to be transferred, idle interfaces are matched to identify transferable tasks and establish task transfer paths to form a task redistribution scheme.

[0135] Based on the task redistribution scheme, the task migration is performed, and the task allocation status record is updated after the migration is completed to obtain the read / write task redistribution result.

[0136] In one specific embodiment, the system first performs a joint analysis of the real-time workload and processing capacity of each interface. Workload refers to the current number of tasks and cache usage on the interface, while processing capacity refers to the amount of data the interface can process per unit time and its response rate. The system obtains the interface's load percentage (e.g., 85%, 40%) and bandwidth utilization (e.g., 1.6GB / s or 80MB / s) through a real-time acquisition module and compares it with a preset saturation threshold. The saturation threshold is set based on the interface's maximum bandwidth, cache capacity, and historical stress test data; for example, the saturation threshold for a DDR interface can be set to 80%, and for an SPI interface, it can be set to 70%. When an interface load exceeds this threshold, the system marks it as a high-load interface and generates an interface load distribution mapping table. This mapping table lists the current load status, remaining processing capacity, and cache availability for each interface; for example, DDR interface load 85%, SPI interface load 40%, and control interface load 20%, thus providing a visual basis for task reallocation.

[0137] After generating the mapping table, the system needs to perform task splitting on the pending data queue of the high-load interface. The core of task splitting lies in identifying read and write tasks that can be migrated independently, ensuring that task transfer does not disrupt data consistency or dependencies. Specifically, this involves analyzing the address range and dependency identifiers of each task in the task queue to filter out independent data block tasks. For example, in a real-world scenario, the DDR interface queue contains 100 write tasks, 60 of which are independent 4MB data blocks. The system splits these 60 tasks into 6 task packages, each containing 10 tasks, as migration candidates.

[0138] After a task packet is generated, the system matches the task packet set with idle interfaces. The matching process includes three steps: First, calculating the remaining bandwidth and processing capacity of the idle interface, for example, 40MB / s remaining for the SPI interface and 25MB / s remaining for the control interface; second, verifying task type compatibility, for example, the SPI interface supports block-level writes but not high-speed burst access tasks; third, confirming whether the cache capacity is sufficient to receive the task packets, for example, the SPI interface cache is 32MB, which can simultaneously accommodate two sets of 4MB task packets. After matching is completed, the system determines the target interface for the transferable task and establishes a task transfer path. The transfer path can be implemented through the internal bus or DMA channel to avoid occupying the main bus bandwidth.

[0139] It should be noted that the selection of the task transfer path is dynamically determined based on parameters such as task packet size, transmission real-time performance, and main bus utilization. Specifically, when the task packet data volume is large (e.g., a single packet exceeds 8MB) or when high real-time requirements are needed, the system prioritizes point-to-point transmission via the DMA channel. The DMA channel has independent transmission capabilities and can complete large-scale data transfer in the background without consuming main bus bandwidth, making it suitable for high-concurrency or high-throughput task scenarios. Conversely, when the task packet size is small (e.g., less than 1MB) or when the system's current main bus utilization is low (below 30%), tasks can be transferred directly via the internal bus to reduce path switching and DMA initialization overhead, achieving fast scheduling.

[0140] For example, in a task migration, if the task packet generated by the DDR interface is 12MB and the system detects that the main bus occupancy rate has reached 70%, the system directly calls the DMA channel to complete the migration. However, if the task packet generated by the SPI interface is only 2MB and the main bus occupancy rate is less than 20%, the system selects the internal bus path to complete the transmission, achieving low-latency and fast transfer. Through the above dynamic determination method, the system maximizes the utilization of hardware resources while ensuring transmission efficiency and reduces performance bottlenecks caused by improper path selection.

[0141] After matching is complete, the system will perform task migration based on the task redistribution scheme. A packet-by-packet transmission strategy is used during migration to prevent sudden bus congestion caused by migrating too many tasks at once. After each task packet migration is completed, the system immediately updates the task allocation status record, including metrics such as the current number of tasks, cache utilization, and estimated response time for high-load and idle interfaces. For example, after migrating 6 sets of task packets, the task load on the DDR interface drops from 100 to 40, and the load decreases to 60%; the task load on the SPI interface increases to 70, and the load rises to 65%. This means that the overall load changes from a single concentrated point to a balanced distribution, and the response time of each interface returns to within the timing coordination requirements.

[0142] Finally, the system outputs the new read / write task redistribution results and passes them as input to the next step, S17, for further dynamic optimization of priority parameters. Through this process, the system not only resolves the resource imbalance problem caused by conflicts but also establishes a foundation for continuous adjustment, enabling subsequent scheduling to automatically optimize interface collaboration based on real-time load changes.

[0143] It should be noted that the saturation threshold is used to determine whether the interface load has reached a high-load state, thereby triggering task reallocation. The threshold is set by comprehensively considering the interface's maximum bandwidth capacity, cache capacity, task type characteristics, and the system's tolerable latency, and is determined through experimental testing and analysis of historical operating data. The setting process first involves gradually increasing the interface load in an experimental environment and monitoring its response latency and data packet loss rate. When the latency shows a significant increase (e.g., exceeding 20% ​​of the baseline value) or the cache usage approaches full capacity, this point is used as the threshold reference.

[0144] For example, in a hybrid interface system, the DDR interface has a bandwidth of 1.6GB / s and a cache capacity of 256MB. Testing revealed that when its load exceeded 80%, the latency increased from 40ns to 60ns, significantly increasing the risk of cache overflow. Therefore, its saturation threshold was set to 80%. The SPI interface has a bandwidth of 80MB / s and a cache capacity of 32MB. Testing showed that when its load exceeded 70%, the latency increased from 150ns to 250ns. Therefore, its saturation threshold was also set to 70%. In actual operation, when the interface load exceeds this threshold, the system marks it as a high-load interface and prioritizes task splitting and reallocation. Interfaces with loads below this threshold can participate in load balancing as task receivers. This threshold setting method ensures that the judgment criteria match the interface characteristics, avoiding premature or delayed task migration that could lead to resource waste or performance degradation.

[0145] It should be noted that the task splitting strategy is used to divide the task queue of high-load interfaces according to independence and granularity, so that some tasks can be safely migrated to other idle interfaces for execution without disrupting the original task order and data consistency. The splitting strategy is mainly based on three criteria: the independence of task data blocks, the dependencies between tasks, and the matching between the task block size and the target interface cache capacity.

[0146] Specifically, the system first scans the task queue of high-load interfaces to extract task identification information and data block address ranges. Tasks with independent data blocks (such as non-overlapping address ranges or no synchronization dependencies between data blocks) can be directly considered as splittable objects. If there are dependencies between tasks (such as sequential write requirements or checksum binding), a marking mechanism is used to group dependent tasks for processing, ensuring that tasks in the same group are not split into different interfaces. Secondly, the system sets the splitting granularity based on the cache capacity of the target interface. For example, if the SPI interface cache capacity is 32MB and the single task block of the high-load DDR interface is 4MB, then 8 task blocks can be migrated at once without exceeding the cache limit.

[0147] For example, in one scheduling scenario, the DDR interface task queue contains 100 4MB write tasks. Of these, 60 tasks have independent addresses and no data synchronization requirements. Based on the strategy, these can be split into 6 task packets, each containing 10 tasks. After splitting, these 6 task packets serve as migrateable units for subsequent task transfer matching and path planning. This strategy ensures that the granularity of task migration adapts to the target interface's cache and bandwidth conditions without disrupting the logical continuity of task execution.

[0148] It should be noted that the implementation of the task transfer path refers to the technical process of transferring task packets from a high-load interface to a target idle interface. The key is to avoid causing additional impact on the main bus and to ensure the integrity and timing controllability of task transmission.

[0149] Path establishment is divided into two modes: direct bus transfer mode and DMA internal channel transfer mode. In bus transfer mode, the high-load interface directly requests access to the bus through the bus arbitrator and writes the task packet to the target interface buffer. However, this mode consumes system bus bandwidth and is suitable for low-frequency or small task packet transfers. In DMA internal channel transfer mode, the system uses an independent DMA controller to establish a point-to-point transmission channel between memory and the interface, realizing background data transfer of tasks without occupying the main bus. This is suitable for large-scale task migrations or high real-time applications.

[0150] For example, in a migration operation, a high-load task on the DDR interface is split into six task packets. Four of these are transferred to the SPI interface via the DMA channel, while the remaining two are transferred to the control interface via the direct bus. The transfer rate in DMA mode can reach 200MB / s, consuming minimal CPU resources after migration. In contrast, the transfer rate in direct bus mode is approximately 80MB / s, suitable for scenarios requiring rapid processing of a small number of remaining tasks. After migration, the system immediately updates the task allocation status, including the new task location, interface load ratio, and subsequent timing predictions, providing input for the next step of dynamic priority optimization.

[0151] Through the above-mentioned splitting and transfer path strategy, the system can distribute the pressure of high-load interfaces to other available interfaces without affecting the integrity and real-time performance of tasks, thereby achieving dynamic load balancing and continuous performance optimization in a multi-interface environment.

[0152] In step S17, it is necessary to monitor the interface running status corresponding to the read / write task reassignment result, obtain interface status change information, and dynamically optimize the priority parameters based on the read / write task reassignment result and the interface status change information to obtain the optimized multi-interface collaborative working configuration, including:

[0153] Based on the load fluctuation data and status change records of the read / write task redistribution result monitoring interface, a list of interfaces to be optimized and interface status change information are obtained.

[0154] Extract the current access permission allocation data from the list of interfaces to be optimized, and re-evaluate the priority weights based on the current access permission allocation data to generate an updated priority ranking table;

[0155] Based on the priority sorting table and the interface status change information, the access permissions of high-load interfaces are adjusted, and an adjustment permission allocation scheme is formed.

[0156] The proposed adjustment permission allocation scheme is applied to the interface collaborative work process, and load fluctuations are monitored to obtain an optimized multi-interface collaborative work configuration.

[0157] In one specific embodiment, the system first continuously monitors the interface based on the task redistribution results, recording its load fluctuation data and status change records. The load fluctuation data reflects the changes in processing pressure of the interface over multiple sampling periods, such as the rate of increase or decrease in queue length; the status change records reflect whether the interface frequently switches load levels, such as a sudden increase from low load to high load. Therefore, the system sets the monitoring period to 10ms and uses the status acquisition module to statistically analyze the changes in interface cache utilization and processing speed in real time. In this embodiment, the DDR interface's load dropped from 85% to 60% after task migration, but then rebounded to 75% within the following 50ms, with a fluctuation exceeding 15%, thus it was included in the list of interfaces to be optimized.

[0158] It should be noted that interface status change information refers to the dynamic changes obtained by continuously monitoring the operating status of each interface after the read / write task redistribution is completed. This information reflects the fluctuations in interface load and performance over a period of time. This information is not a static parameter at a single moment, but rather a change magnitude and trend calculated based on multi-period sampling. It mainly includes the magnitude of load changes, changes in cache utilization, the rate of increase or decrease in task queue length, and records of interface state transitions from low load to high load or from idle to busy. During implementation, the system uses a load monitoring module to collect interface operating data at a fixed sampling period (e.g., 10ms) and compares it with the baseline state after task redistribution. When the change magnitude exceeds a preset threshold (e.g., 15%) or shows a continuous upward trend within the continuous sampling period, interface status change information is generated. This information serves as an important basis for dynamic adjustment in subsequent priority weight reassessment. For example, when the SPI interface load increases from 40% to 70% within 50ms, the system will mark it as an object to be optimized and appropriately increase its weight in the new priority ranking table to prevent further deterioration of its load.

[0159] After generating a list of interfaces to be optimized, the system extracts the current access permission allocation data for the interfaces in the list and re-evaluates their priority weights based on this data. The evaluation criteria for priority weights include the interface's historical average load, current task type priority, and cache usage trends, which are weighted to form a new scoring model. For example, in a set of weight settings, historical load accounts for 50%, task priority accounts for 30%, and cache usage trends account for 20%. If the SPI interface experiences a rapid increase in cache usage after migration and the task is a high-priority real-time write, its priority weight will increase by approximately 20%, moving it from third to second place in the updated priority ranking table.

[0160] Subsequently, the system dynamically adjusts the access permissions of high-load interfaces based on the updated priority ranking table and interface status change information, forming a new permission allocation scheme. The adjustment strategy follows two principles: first, ensuring that high-priority, high-load interfaces receive sufficient bandwidth; and second, avoiding starvation of low-priority interfaces due to excessive adjustment. In this embodiment, the DDR interface and SPI interface are ranked first and second, respectively, in the updated ranking. The system reduces the time slice ratio of the DDR interface from 60% to 50%, increases the SPI interface to 35%, and reserves 15% as a buffer to cope with sudden tasks.

[0161] Finally, the system applies the adjusted permission allocation scheme to the interface collaborative work process and continuously monitors load fluctuations in the new scheduling cycle. If the detection results show that the interface load distribution is stable and the latency and rate meet the system timing coordination requirements (e.g., latency fluctuations remain within 5% and bus utilization remains around 80%), the optimization is considered complete and the final multi-interface collaborative work configuration is generated. If the fluctuations still exceed the preset standards, the system continues to iterate and optimize until a stable state is reached. Through this dynamic optimization process, the system not only maintains the stability after task redistribution but also adapts to secondary changes in interface load during subsequent operation, achieving continuous improvement in multi-interface collaborative efficiency.

[0162] It should be noted that the priority weight re-evaluation method is used to dynamically adjust the priority position of the interface in the sorting table after task redistribution. The evaluation method adopts a weighted scoring model, which combines three indicators: historical load of the interface, task real-time performance, and cache usage trend. Specifically, historical load reflects the average pressure level of the interface over a period of time and is used to determine its long-term resource requirements; task real-time performance is assigned priority weight according to task type (such as video capture, log storage), with higher real-time tasks having a higher priority; cache usage trend reflects the rate of change of interface pressure, and the weight is dynamically increased when the cache usage rate shows a continuous upward trend.

[0163] For example, let's set the weighting ratios as follows: historical load 50%, task real-time performance 30%, and cache trend 20%. In one evaluation, the DDR interface scored 0.8 for historical load, 0.9 for task real-time performance, and 0.6 for cache trend. Therefore, its overall priority weight is 0.8 × 0.5 + 0.9 × 0.3 + 0.6 × 0.2 = 0.77. In contrast, the SPI interface scored 0.65 overall. In the updated priority ranking table, the DDR interface remains first, while the SPI interface ranks second. This method allows the system to dynamically adjust priorities based on multi-dimensional indicators, avoiding resource allocation imbalances caused by relying on a single parameter.

[0164] It should be noted that the load fluctuation threshold is used to determine whether changes in interface load are sufficient to trigger dynamic optimization of priority parameters. The determination process calculates the magnitude of interface load changes over multiple consecutive sampling periods. When the fluctuation exceeds the threshold, the interface is added to the optimization list. The threshold setting is based on the system's tolerance for task latency and the fluctuation range of the interface's processing capacity. For example, in high real-time systems, the threshold can be set to ±10%, while in more fault-tolerant storage systems, it can be set to ±20%.

[0165] For example, in a video processing system with a sampling period of 10ms, if the load on the DDR interface increases from 60% to 80% within five cycles, with a fluctuation range of 20%, exceeding the preset ±15% threshold, it is determined to be an interface requiring optimization. If the fluctuation range of the SPI interface within the same cycle is only 5%, below the threshold, priority adjustment is not triggered. Through this determination mechanism, the system can accurately capture significant load changes, avoiding scheduling instability caused by frequent optimization triggers due to short-term minor fluctuations.

[0166] In summary, this invention provides a data read / write method and apparatus based on the collaborative use of DDR and SPI interfaces, thereby solving the problem in the prior art that dynamic priority scheduling and bus access optimization cannot be performed based on the real-time status of the interface.

[0167] Reference Figure 2 The second embodiment of the present invention provides a data read / write device based on DDR and SPI interface coordination, comprising:

[0168] The data acquisition module is used to acquire the status data set of each interface, data transmission priority requirements, real-time bus access status, and system timing coordination requirements.

[0169] The load assessment module is used to perform threshold judgment and trend analysis based on the cache occupancy rate characteristics and queue length change characteristics in the status data set, complete the load assessment, and obtain the interface load level classification results.

[0170] The priority sorting module is used to calculate the urgency of bus access and perform priority scheduling based on the classification results and the data transmission priority requirements, so as to obtain the priority sorting sequence of the interfaces.

[0171] The access permission module is used to allocate time slices according to the priority sorting sequence and the real-time bus access status to obtain the bus access permission allocation scheme.

[0172] The resource conflict module is used to execute the access permission allocation scheme, extract the data transmission status of each interface during the execution process, generate performance indicators, and detect resource contention and generate resource conflict resolution strategies based on the performance indicators.

[0173] The task allocation module is used to reallocate tasks according to the resource conflict resolution strategy and the system timing coordination requirements, and obtain the read and write task reallocation results.

[0174] The collaborative configuration module is used to monitor the running status of the interface corresponding to the read / write task reassignment result, obtain interface status change information, and dynamically optimize priority parameters based on the read / write task reassignment result and the interface status change information to obtain the optimized multi-interface collaborative working configuration.

[0175] It should be noted that the data read / write device based on DDR and SPI interface collaboration provided in this embodiment of the invention is used to execute all the process steps of the data read / write method based on DDR and SPI interface collaboration in the above embodiment. The working principles and beneficial effects of the two are one-to-one, so they will not be described again.

[0176] This invention also provides an electronic device. The electronic device includes a processor, a memory, and a computer program stored in the memory and executable on the processor, such as a priority sorting program. When the processor executes the computer program, it implements the steps in the various embodiments of the data read / write method based on DDR and SPI interfaces described above, for example... Figure 1 The step S11 shown. Alternatively, when the processor executes the computer program, it implements the functions of each module / unit in the above-described device embodiments, such as the task allocation module.

[0177] For example, the computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the electronic device.

[0178] The electronic device may be a desktop computer, laptop, handheld computer, or smart tablet, etc. The electronic device may include, but is not limited to, a processor and memory. Those skilled in the art will understand that the above components are merely examples of electronic devices and do not constitute a limitation on the electronic device. It may include more or fewer components than described above, or combine certain components, or different components. For example, the electronic device may also include input / output devices, network access devices, buses, etc.

[0179] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the electronic device, connecting all parts of the electronic device via various interfaces and lines.

[0180] The memory can be used to store the computer programs and / or modules. The processor implements various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory and by calling data stored in the memory. The memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the mobile phone (such as audio data, phonebook, etc.). In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, RAM, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0181] Wherein, if the modules / units integrated in the electronic device are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0182] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0183] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A data read-write method based on cooperation of DDR and SPI interfaces, characterized in that include: Obtain the status data set of each interface, data transmission priority requirements, real-time bus access status, and system timing coordination requirements; Based on the cache occupancy rate characteristics and queue length change characteristics in the state data set, threshold judgment and trend analysis are performed to complete the load assessment and obtain the interface load level classification results. Based on the classification results and the data transmission priority requirements, the urgency of bus access is calculated and priority scheduling is performed to obtain the priority ranking sequence of the interfaces. Based on the priority sorting sequence and the real-time bus access status, time slices are allocated to obtain a bus access permission allocation scheme. The access permission allocation scheme is executed, and the data transmission status of each interface is extracted during the execution process to generate performance indicators. Based on the performance indicators, resource contention is detected and a resource conflict resolution strategy is generated. Based on the resource conflict resolution strategy and the system timing coordination requirements, tasks are reallocated to obtain the read / write task reallocation results. Monitor the running status of the interface corresponding to the read / write task reassignment result, obtain interface status change information, and dynamically optimize the priority parameters based on the read / write task reassignment result and the interface status change information to obtain the optimized multi-interface collaborative working configuration. The step of calculating the urgency of bus access and performing priority scheduling based on the classification results and data transmission priority requirements to obtain a priority ranking sequence for interfaces includes: extracting the data processing latency of each interface based on the load assessment score in the classification results and the data transmission priority requirements; if the data processing latency exceeds a preset processing latency threshold, marking the interface corresponding to the threshold as an urgent scheduling object to obtain an urgent scheduling list; scoring the urgency of bus access for each interface based on the urgent scheduling list, generating adjusted weight values, and determining a temporary priority ranking based on the weight values ​​from high to low; dynamically adjusting the bus resource allocation status based on the temporary priority ranking to obtain an updated resource allocation scheme, and evaluating the response speed of each interface based on the updated resource allocation scheme; if the response speed does not reach a preset response speed threshold, performing a correction of the bus resource allocation ratio to obtain a priority ranking sequence for interfaces. The step of executing the access permission allocation scheme, extracting the data transmission status of each interface during execution, generating performance indicators, and detecting resource contention and generating resource conflict resolution strategies based on the performance indicators includes: executing the access permission allocation scheme, extracting the data transmission performance of each interface, and generating performance indicators; analyzing the resource contention situation and data flow conflict records between interfaces based on the performance indicators, and detecting whether there are multiple interfaces simultaneously requesting access to the same storage area; when an access conflict is detected, generating a resource contention analysis report and sorting the conflicting interfaces according to preset conflict judgment rules to form a temporary access permission management scheme; adjusting the resource allocation ratio based on the temporary access permission management scheme to obtain updated allocation records; tracking the performance changes of the interfaces based on the updated allocation records, determining whether the conflict is completely resolved, and generating resource conflict resolution strategies.

2. The data read / write method based on DDR and SPI interface collaboration according to claim 1, characterized in that, The process involves threshold judgment and trend analysis based on the cache occupancy characteristics and queue length change characteristics in the state data set to complete load assessment and obtain the interface load level classification results, including: Based on the cache occupancy information in the status data set, the cache occupancy of each interface is compared with a preset occupancy threshold. If the cache utilization rate exceeds a preset utilization rate threshold, the interface is marked as a potentially high-load interface, and a preliminary interface list is obtained; Based on the processing queue length data in the preliminary interface list, the changing trend of queue length is detected within a continuous sampling period to obtain a high-load candidate list; Based on the high load candidate list, calculate the load assessment score, determine the interface load level based on the load assessment score, and generate load level classification data; In the load level classification data, an abnormal status identifier is recorded for the interface that is determined to be in a high load state, and the interface load level classification result is obtained.

3. The data read / write method based on DDR and SPI interface collaboration according to claim 1, characterized in that, The step of allocating time slices based on the priority sorting sequence and the real-time bus access status to obtain a bus access permission allocation scheme includes: Based on the priority sorting sequence and the real-time bus access status, the access conditions of high-priority interfaces are determined, and a temporary permission allocation list is generated when the preset idle conditions are met. For the temporary permission allocation list, the access time slices are dynamically adjusted, and an adjusted time slice allocation table is generated in combination with preset allocation rules; Based on the time slice allocation table, the bus access permissions are checked and the time slice allocation is corrected to obtain the permission allocation record; Based on the permission allocation record, the bus status and interface request information are continuously tracked, and the permission allocation scheme is optimized to obtain the bus access permission allocation scheme.

4. The data read / write method based on DDR and SPI interface collaboration according to claim 1, characterized in that, The step of reallocating tasks according to the resource conflict resolution strategy and the system timing coordination requirements to obtain read / write task reallocation results includes: Based on the resource conflict resolution strategy and the system timing coordination requirements, the current workload and processing capacity of each interface are analyzed, and interfaces whose processing capacity exceeds the preset saturation threshold are marked as high-load interfaces, and an interface load distribution mapping table is generated. Based on the interface load distribution mapping table, the data queue to be processed of the high-load interface is split into tasks, and read and write tasks with divisible characteristics are extracted to obtain a set of task packages to be transferred. Based on the set of tasks to be transferred, idle interfaces are matched to identify transferable tasks and establish task transfer paths to form a task redistribution scheme. Based on the task redistribution scheme, the task migration is performed, and the task allocation status record is updated after the migration is completed to obtain the read / write task redistribution result.

5. The data read / write method based on DDR and SPI interface collaboration according to claim 1, characterized in that, The monitoring of the interface running status corresponding to the read / write task reassignment result obtains interface status change information, and based on the read / write task reassignment result and the interface status change information, the priority parameters are dynamically optimized to obtain an optimized multi-interface collaborative working configuration, including: Based on the load fluctuation data and status change records of the read / write task redistribution result monitoring interface, a list of interfaces to be optimized and interface status change information are obtained. Extract the current access permission allocation data from the list of interfaces to be optimized, and re-evaluate the priority weights based on the current access permission allocation data to generate an updated priority ranking table; Based on the priority sorting table and the interface status change information, the access permissions of high-load interfaces are adjusted, and an adjustment permission allocation scheme is formed. The proposed adjustment permission allocation scheme is applied to the interface collaborative work process, and load fluctuations are monitored to obtain an optimized multi-interface collaborative work configuration.

6. A data read / write device based on DDR and SPI interface collaboration, characterized in that, A method for implementing the data read / write method based on DDR and SPI interface collaboration as described in any one of claims 1 to 5 includes: The data acquisition module is used to acquire the status data set of each interface, data transmission priority requirements, real-time bus access status, and system timing coordination requirements; The load assessment module is used to perform threshold judgment and trend analysis based on the cache occupancy rate characteristics and queue length change characteristics in the status data set, complete the load assessment, and obtain the interface load level classification results. The priority sorting module is used to calculate the urgency of bus access and perform priority scheduling based on the classification results and the data transmission priority requirements, so as to obtain the priority sorting sequence of the interfaces. The access permission module is used to allocate time slices according to the priority sorting sequence and the real-time bus access status to obtain the bus access permission allocation scheme. The resource conflict module is used to execute the access permission allocation scheme, extract the data transmission status of each interface during the execution process, generate performance indicators, and detect resource contention and generate resource conflict resolution strategies based on the performance indicators. The task allocation module is used to reallocate tasks according to the resource conflict resolution strategy and the system timing coordination requirements, and obtain the read and write task reallocation results. The collaborative configuration module is used to monitor the running status of the interface corresponding to the read / write task reassignment result, obtain interface status change information, and dynamically optimize priority parameters based on the read / write task reassignment result and the interface status change information to obtain the optimized multi-interface collaborative working configuration.

7. An electronic device, characterized in that, The system includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor, when executing the computer program, implements the data read / write method based on DDR and SPI interface coordination as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program, wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to perform the data read / write method based on DDR and SPI interface coordination as described in any one of claims 1 to 5.

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