Clock synchronization method, clock synchronization device, and high-speed communication device

Abstract

The application discloses a clock synchronization method, a clock synchronization device and high-speed communication equipment, and relates to the technical field of clock synchronization. In the clock synchronization method, first, a current clock input signal is compensated based on a first phase error signal predicted from a previous clock signal; then, a current phase error of the compensated current clock input signal is determined; a first clock adjustment signal for adjusting the current phase error is generated by a first compensation loop, and there is a circuit delay; a second compensation loop predicts a new phase error generated during the circuit delay of the first compensation loop, and generates a second clock adjustment signal for the new phase error; a third clock adjustment signal representing a current real clock phase deviation is calculated and synthesized based on the double clock adjustment signals; and finally, a next clock input signal is adjusted based on the third clock adjustment signal. Through the double compensation loops, the application eliminates the phase lag caused by the circuit delay, and significantly improves the clock synchronization accuracy.

Description

Technical Field

[0001] This application relates to the field of clock synchronization technology, and in particular to clock synchronization methods, clock synchronization devices, and high-speed communication equipment. Background Technology

[0002] With the increasing data rates of high-speed SerDes (Serializer / Deserializer) systems, clock cycles have reached picosecond levels, placing extremely high demands on the phase synchronization of CDR (Clock and Data Recovery) circuits. Some techniques reduce loop processing latency by improving parallel algorithms, but only slightly. Other techniques reduce hardware latency by optimizing chip layout and routing, but the reduction is limited by chip area and process precision constraints. Therefore, eliminating phase lag caused by latency in the CDR loop has become an urgent problem to be solved. Summary of the Invention

[0003] This application provides a clock synchronization method, a clock synchronization device, and a high-speed communication equipment to at least solve the problem of phase lag caused by delay in the CDR loop in the related art.

[0004] This application provides a clock synchronization method, including: Based on the first phase error signal predicted from the previous clock signal, the current clock input signal is compensated to obtain the compensated current clock input signal; Determine the current phase error of the compensated current clock input signal; The current phase error is input into the first compensation loop to obtain the first clock adjustment signal, and the current phase error is input into the second compensation loop to obtain the second clock adjustment signal. The first compensation loop is used to simulate the first clock adjustment signal used to compensate the next clock signal when there is a circuit delay. The second compensation loop is used to simulate the second clock adjustment signal used to compensate the next clock signal when there is no circuit delay. The third clock adjustment signal is obtained by synthesizing the first clock adjustment signal and the second clock adjustment signal through calculation; Adjust the next clock input signal based on the third clock adjustment signal.

[0005] This application also provides a clock synchronization device, including: The clock input compensation module is used to compensate the current clock input signal based on the first phase error signal predicted from the previous clock signal, so as to obtain the compensated current clock input signal. The phase error determination module is used to determine the current phase error of the compensated current clock input signal; The loop adjustment signal module inputs the current phase error into the first compensation loop and the current phase error into the second compensation loop. The first compensation loop is used to generate a first clock adjustment signal to adjust the current phase error. The first compensation loop has a circuit delay. The second compensation loop is used to predict the new phase error generated during the circuit delay of the first compensation loop and generate a second clock adjustment signal for the new phase error. The second phase error generation module is used to synthesize the first clock adjustment signal and the second clock adjustment signal through calculation to obtain the third clock adjustment signal; The next clock adjustment module is used to adjust the next clock input signal based on the third clock adjustment signal.

[0006] This application also provides a high-speed communication device, which includes a clock synchronization device as described in any of the preceding claims.

[0007] In some embodiments of this application, the current clock input signal is compensated based on a first phase error signal predicted from the previous clock signal, and then the current phase error of the compensated clock signal is determined. This current phase error is input into a first compensation loop and a second compensation loop. The first compensation loop generates a first clock adjustment signal to adjust the current phase error, and the second compensation loop predicts a new phase error generated during the circuit delay of the first compensation loop and generates a second clock adjustment signal for the new phase error. Thus, the second compensation loop can reduce the impact of the circuit delay of the first compensation loop. After synthesizing the first and second clock adjustment signals through calculation to obtain a third clock adjustment signal, and adjusting the next clock input signal based on the third clock adjustment signal, the phase lag deviation caused by the delay can be effectively eliminated. This solves the phase lag problem caused by delay in some CDR loops. Attached Figure Description

[0008] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of component interactions in a clock synchronization method according to one embodiment; Figure 2 This is a schematic diagram of component interactions in a clock synchronization method according to one embodiment; Figure 3 A flowchart illustrating a clock synchronization method according to one embodiment; Figure 4This is a schematic diagram of a clock synchronization device according to one embodiment; Figure 5 This is a schematic diagram of a module of an electronic device according to one embodiment. Detailed Implementation

[0010] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0011] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0012] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0013] See also Figure 1 , Figure 1 This diagram illustrates the component interactions in some clock synchronization methods. The CDR loop integrates a phase detector, a loop filter, and a VCO (Voltage-Controlled Oscillator) / phase interpolator. To achieve phase alignment between the clock and data stream, the phase detector first detects the phase error between the current clock and the data stream. This phase error is then passed to the loop filter for smoothing and noise suppression. Finally, the VCO / phase interpolator generates a clock adjustment signal, which is used to adjust the clock input signal to achieve phase alignment between the clock and the data stream.

[0014] exist Figure 1In the existing technology shown, the phase detector, loop filter, and VCO / phase interpolator modules of the CDR loop inevitably have processing delays. This causes the generation of the clock adjustment signal to lag behind the accumulation of the actual phase error, and the adjustment signal is always generated based on the initial error, making it impossible to match the dynamically changing actual deviation in real time. For example, if the initial phase error is "1", the CDR loop first identifies the error through the phase detector, then smooths the error signal through the loop filter, and finally drives the VCO to generate a clock adjustment signal based on the initial phase error "1". The total processing delay of the entire process is 10 clock cycles. Within these 10 clock cycles, due to the accumulation of delay, an additional unit phase error is added each cycle. By the end of the ten cycles, the actual phase error has accumulated from the initial "1" to "11". At this point, the adjustment signal generated based on the initial phase error "1" can only offset 1 unit error and cannot completely eliminate the current deviation.

[0015] In some technical solutions, some techniques shorten the CDR loop processing latency by improving parallel algorithms, but this only reduces the latency slightly; other techniques reduce hardware latency through placement and routing optimization, but the reduction is limited by chip area and process precision constraints. Therefore, how to eliminate the phase lag caused by latency in the CDR loop has become an urgent problem to be solved.

[0016] In view of this, this application provides a clock synchronization method that can solve the above problems. The clock synchronization method can be applied to electronic devices. Electronic devices may include, but are not limited to, tablet computers, laptops, desktop computers, servers, etc. (See also...) Figure 2 and Figure 3 , Figure 2 A schematic diagram of component interactions for a clock synchronization method provided in some embodiments of this application. Figure 3 A flowchart illustrating a clock synchronization method provided for some embodiments of this application. Figure 3 In this context, the clock synchronization method includes the following steps: Step S301: Based on the first phase error signal predicted from the previous clock signal, the current clock input signal is compensated to obtain the compensated current clock input signal.

[0017] Specifically, the first phase error signal refers to the signal characterizing the phase deviation of the clock in the previous cycle, and its magnitude corresponds to the degree of phase deviation between the clock signal and the received data stream. The current clock input signal refers to the original clock signal to be phase-calibrated, which originates from an externally input clock source.

[0018] In this embodiment, the CDR system first retrieves the first phase error signal stored in the previous clock cycle. This signal includes the effect of circuit delay on the clock phase in the previous cycle. Based on the quantization value of the first phase error signal, the phase of the current clock input signal is pre-calibrated.

[0019] Step S302: Determine the current phase error of the compensated current clock input signal.

[0020] Specifically, the current phase error is used to characterize the degree of phase deviation between the compensated current clock input signal and the received data stream, and its magnitude directly reflects the synchronization status of the clock and data.

[0021] Step S303: Input the current phase error into the first compensation loop and input the current phase error into the second compensation loop. The first compensation loop is used to generate a first clock adjustment signal to adjust the current phase error. The first compensation loop has a circuit delay. The second compensation loop is used to predict the new phase error generated during the circuit delay of the first compensation loop and generate a second clock adjustment signal for the new phase error.

[0022] Specifically, the first compensation loop refers to the functional module that simulates the actual circuit delay in the CDR system, allowing the current phase error of the input to undergo a delay process consistent with the actual circuit, ultimately outputting a first clock adjustment signal. The first clock adjustment signal is a clock adjustment signal that carries the effects of circuit delay.

[0023] The second compensation loop is used to capture the circuit delay duration of the first compensation loop in real time, and based on a preset error accumulation law, predict the new phase error caused by path delay during the circuit delay period of the first compensation loop. At the same time, for the predicted new phase error, combined with the initial value of the current phase error, a second clock adjustment signal is generated that can cancel the initial phase error and the new phase error during the delay period, ensuring that the second clock adjustment signal can cover the adjustment lag problem caused by the circuit delay of the first compensation loop.

[0024] In this embodiment, the current phase error is synchronously input into the delay simulation model of the first compensation loop and the prediction model of the second compensation loop, and the first clock adjustment signal and the second clock adjustment signal are output.

[0025] Step S304: The first clock adjustment signal and the second clock adjustment signal are synthesized through calculation to obtain the third clock adjustment signal.

[0026] Specifically, computational synthesis refers to the use of computational logic designed based on the CDR loop delay characteristics to cancel out the circuit delay effect carried by the first clock adjustment signal through mathematical operations, thereby obtaining a third clock adjustment signal used to adjust the phase deviation between the current clock and the data stream. The third clock adjustment signal is used to adjust the actual clock phase deviation between the current clock signal and the data stream, and can remove the interference caused by the delay of the first compensation loop circuit.

[0027] Step S305: Adjust the next clock input signal based on the third clock adjustment signal.

[0028] Specifically, the next clock input signal refers to the clock input signal that needs to be adjusted before entering the next clock cycle. Based on the quantization deviation of the third clock adjustment signal, the phase of the next clock input signal is calibrated to be aligned with the data stream, ensuring that there is no deviation accumulation in the sampling process of the next cycle.

[0029] In summary, in some embodiments of this application, the current clock input signal is compensated based on the first phase error signal predicted from the previous clock signal, and then the current phase error of the compensated clock signal is determined. This current phase error is input into a first compensation loop and a second compensation loop, respectively. The first compensation loop generates a first clock adjustment signal to adjust the current phase error, and the second compensation loop predicts a new phase error generated during the circuit delay of the first compensation loop and generates a second clock adjustment signal for the new phase error. Thus, the second compensation loop can reduce the impact of the circuit delay of the first compensation loop. After calculating the first and second clock adjustment signals to obtain a third clock adjustment signal, and adjusting the next clock input signal based on the third clock adjustment signal, the phase lag deviation caused by the delay can be effectively eliminated. This solves the phase lag problem caused by delay in some CDR loops.

[0030] In some embodiments, determining the current phase error of the compensated current clock input signal in step S102 includes: Based on a preset algorithm, the compensated current clock input signal is processed to obtain the current phase error.

[0031] Specifically, the preset algorithm refers to the phase detection algorithm designed for comparing the phase of the clock signal and the data stream in a high-speed SerDes system. Its function is to capture the phase relationship of the signal transition edges and avoid errors caused by signal distortion. Examples include the Bang-Bang algorithm and the Gardner algorithm.

[0032] In this embodiment, the algorithm calibrates the phase deviation based on the time of the transition between the compensated clock signal and the received data stream, and outputs the current phase error.

[0033] In the above embodiments, by processing the transition times of the compensated current clock input signal and the received data stream based on a preset algorithm, the phase deviation is calibrated and the current phase error is output. This can accurately capture the phase relationship between the clock signal and the data stream, ensuring that the output current phase error can truly reflect the degree of phase deviation between the two, thus improving the accuracy of clock synchronization.

[0034] In some embodiments, the first compensation loop includes a delay simulation model, and step S103, inputting the current phase error into the first compensation loop, includes: The current phase error is input into the delay simulation model to obtain the first clock adjustment signal. The delay simulation model has data storage characteristics, and the output first clock adjustment signal has circuit delay characteristics.

[0035] Specifically, data storage characteristics refer to the attributes that a delay simulation model possesses to reproduce the actual delay of a CDR loop circuit. This means that the model can remain in the storage unit for a specific duration according to a preset delay configuration, and only output the data after the delay requirement has been met. This process is completely consistent with the delay effect caused by signal transmission in a real circuit.

[0036] In this embodiment, the storage unit can be a First-In-First-Out (FIFO) memory. The storage duration can be flexibly adjusted by configuring the FIFO, and the delay accuracy is determined by the system clock frequency. When the signal stays in the FIFO for a preset delay value, the model controls the FIFO to read the signal according to the FIFO rule. The output signal at this time is the first clock adjustment signal carrying the circuit delay characteristics.

[0037] In the above embodiment, by inputting the current phase error into the delay simulation model of the first compensation loop, and then storing the signal in the storage unit to allow it to remain for a specific duration according to a preset delay configuration before outputting it, a first clock adjustment signal with circuit delay characteristics is obtained. This can accurately reproduce the real circuit delay effect of the CDR loop, ensuring that the output first clock adjustment signal is consistent with the signal delay characteristics in the real circuit, laying the foundation for the adjustment of the next clock input signal.

[0038] In some embodiments, step S103, inputting the current phase error into the second compensation circuit, includes: The current phase error is input into the prediction model, which then predicts the second clock adjustment signal. The second clock adjustment signal is used to compensate for the circuit delay of the first compensation loop.

[0039] Specifically, the predictive model refers to a delay-free control path model, which can be implemented using a 16th-order IIR (Infinite Impulse Response) digital filter. Its function is to reproduce the control characteristics of the VCO or phase interpolator under delay-free conditions, that is, the ideal response of the analog clock adjustment unit to the phase error signal when unaffected by delay, thereby outputting a second clock adjustment signal. The difference between the second clock adjustment signal and the first clock adjustment signal output by the first compensation loop is equal to the effect of delay on the adjustment signal.

[0040] In the above embodiment, by inputting the current phase error into the prediction model of the second compensation circuit, the model reproduces the delay-free control characteristics of the VCO / phase interpolator and the ideal response law of the analog clock adjustment unit, thereby predicting the second clock adjustment signal. This generates an ideal adjustment signal that matches the delay-free scenario, ensuring that the difference between the second clock adjustment signal and the first clock adjustment signal output by the first compensation loop is exactly equal to the impact of the delay on the adjustment signal, thus providing a compensation signal for subsequently offsetting the circuit delay of the first compensation loop.

[0041] In some embodiments, step S104, which involves synthesizing the first clock adjustment signal and the second clock adjustment signal through calculation to obtain the third clock adjustment signal, includes: The first clock adjustment signal and the second clock adjustment signal are added together to obtain the third clock adjustment signal; Alternatively, the first clock adjustment signal can be subtracted from the second clock adjustment signal to obtain the third clock adjustment signal.

[0042] Specifically, if the delay causes the adjustment amount to lag behind the actual demand, the first clock adjustment signal and the second clock adjustment signal are added together; if the delay causes the adjustment amount to lead the actual demand, the first clock adjustment signal and the second clock adjustment signal are subtracted.

[0043] In the above embodiments, by adding or subtracting the first clock adjustment signal and the second clock adjustment signal, the circuit delay effect carried by the first clock adjustment signal can be accurately canceled, ensuring that the output third clock adjustment signal can adjust the phase deviation between the current clock and the data stream, thus guaranteeing the accuracy of clock synchronization of the high-speed SerDes system.

[0044] In some embodiments, adjusting the next clock input signal based on the third clock adjustment signal in step S105 includes: The third clock adjustment signal is transmitted to the sampling control unit. Based on the third clock adjustment signal, the sampling control unit drives the analog-to-digital converter to adjust the sampling phase so that the analog-to-digital converter samples at the peak or trough of the analog signal.

[0045] Specifically, an analog-to-digital converter (ADC) is a module in a clock synchronization system that converts analog signals into digital signals, and its sampling phase directly determines the sampling accuracy.

[0046] In this embodiment, if sampling is performed at the transition edge of the analog signal, that is, in the unstable level region, it is easy to misjudge "0" or "1"; if sampling is performed at the peak / trough, that is, in the stable level region, the bit error rate can be reduced. Therefore, the core objective of adjusting the sampling phase is to lock the peak / trough sampling point.

[0047] In the above embodiment, by transmitting the third clock adjustment signal to the sampling control unit, the control unit drives the ADC to adjust the sampling phase based on the signal, so that the ADC samples at the peak or trough of the analog signal. This avoids the transition edges of the analog signal and prevents misjudgments of "0" and "1" due to sampling in unstable regions, laying the foundation for reliable clock synchronization in high-speed SerDes systems.

[0048] In some embodiments, before the current phase error is input to the first compensation loop and the second compensation loop, the method of this application further includes: The current phase error is subjected to loop filtering to obtain the current phase error that meets the preset smoothness condition.

[0049] Specifically, loop filtering refers to the operation of optimizing the current phase error signal. It can suppress high-frequency fluctuations in the signal caused by noise interference and phase detection jitter, making the signal amplitude change smoother and ensuring the accuracy of delay simulation and prediction in the dual-loop system. The filtering technology used in loop filtering needs to be adapted to the real-time requirements of the high-speed SerDes system to ensure the filtering effect.

[0050] In the above embodiments, before the current phase error is input into the first and second compensation loops, a filtering technique adapted to the real-time requirements of the high-speed SerDes system is used to perform loop filtering, resulting in a current phase error that meets preset smoothness conditions. This can simultaneously provide stable input signals for the delay simulation of the first compensation loop and the prediction model of the second compensation loop, improving the reliability of clock synchronization.

[0051] To facilitate understanding, an example will be used as an illustration below.

[0052] Assuming a high-speed SerDes system with a real circuit delay of 10 clock cycles, the signal changes at each stage are as follows: 1) The phase detector receives the data stream converted by the analog-to-digital converter and the current clock signal after compensation in the previous cycle, and outputs the current phase error "1".

[0053] 2) The loop filter filters the signal with the current phase error "1" and outputs a smooth control signal "1".

[0054] 3) Actual path: corresponding Figure 2 The VCO / phase interpolator. In the actual path, the control signal "1" drives the VCO / phase interpolator to perform clock adjustment, but due to the inherent circuit delay of 10 clock cycles, this signal needs to be delayed by 10 clock cycles before being output, that is, the first clock adjustment signal "1" of the actual path is obtained in the 10th clock cycle.

[0055] Predicted path: Corresponding Figure 2The Smith Predictor (SP) includes a no-delay path model and a delayed path model to anticipate future system states and avoid adjustment lag or overshoot caused by delays. Specifically, based on the current phase error signal "1", the no-delay path model, and the delayed path model, the Smith Predictor predicts a phase error of "10" after 10 clock cycles. If a subtraction strategy is used, the preset compensation signal is "10 + 1 = 11", generating a second clock adjustment signal "11"; if an addition strategy is used, the preset compensation signal is "10 - 1 = 9", generating a second clock adjustment signal "9".

[0056] 4) The adaptive calibration circuit performs a delay elimination operation on the first clock adjustment signal "1" which is delayed by 10 cycles from the actual path and the second clock adjustment signal "11" or "9" generated in advance for the predicted path. If it is "11", the result is "11-1=10"; if it is "0", the result is "9+1=10".

[0057] Finally, the third clock adjustment signal "10" reflecting the current true deviation is obtained, and it is used as the first phase error signal of the next cycle to pre-compensate the next clock input signal, ensuring that the deviation of the clock in subsequent cycles has been corrected in advance before the phase comparison.

[0058] Corresponding to the clock synchronization method, this application also provides a clock synchronization device. (See also...) Figure 4 This is a schematic diagram of a clock synchronization device provided in some embodiments of this application. Figure 4 The clock synchronization device includes: The clock input compensation module 401 is used to compensate the current clock input signal based on the first phase error signal predicted from the previous clock signal, so as to obtain the compensated current clock input signal. The phase error determination module 402 is used to determine the current phase error of the compensated current clock input signal; The loop adjustment signal module 403 is used to input the current phase error into the first compensation loop and the current phase error into the second compensation loop. The first compensation loop is used to generate a first clock adjustment signal to adjust the current phase error. The first compensation loop has a circuit delay. The second compensation loop is used to predict the new phase error generated during the circuit delay of the first compensation loop and generate a second clock adjustment signal for the new phase error. The second phase error generation module 404 is used to synthesize the first clock adjustment signal and the second clock adjustment signal through calculation to obtain the third clock adjustment signal; The next clock adjustment module 405 is used to adjust the next clock input signal based on the third clock adjustment signal.

[0059] In some embodiments, the phase error determination module 402 is specifically used for: The phase error detection algorithm unit is used to process the compensated current clock input signal based on a preset algorithm to obtain the current phase error.

[0060] In some embodiments, the loop adjustment signal module 403 is specifically used for: The current phase error is input into the delay simulation model to obtain the first clock adjustment signal. The delay simulation model has data storage characteristics, and the output first clock adjustment signal has circuit delay characteristics.

[0061] In some embodiments, the loop adjustment signal module 403 is specifically used for: The current phase error is input into the prediction model, which then predicts the second clock adjustment signal. The second clock adjustment signal is used to compensate for the circuit delay of the first compensation loop.

[0062] In some embodiments, the second phase error generation module 404 is specifically used for: The first clock adjustment signal and the second clock adjustment signal are added together to obtain the third clock adjustment signal; Alternatively, the third clock adjustment signal can be obtained by subtracting the first clock adjustment signal from the second clock adjustment signal.

[0063] In some embodiments, the next clock adjustment module 405 is specifically used for: This signal is used to transmit the third clock adjustment signal to the sampling control unit. Based on the third clock adjustment signal, the sampling control unit drives the analog-to-digital converter to adjust the sampling phase so that the analog-to-digital converter samples at the peak or trough of the analog signal.

[0064] In some embodiments, the current phase error further includes, before the input delay model unit and the prediction model unit: Used to perform loop filtering on the current phase error to obtain the current phase error that meets the preset smoothness conditions.

[0065] For a description of the features in the embodiment corresponding to the clock synchronization device, please refer to the relevant description in the embodiment corresponding to the sample data processing method, which will not be repeated here.

[0066] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0067] See also Figure 5Embodiments of this application also provide a high-speed communication device 500, which includes... Figure 4 The clock synchronization device shown.

[0068] Because high-speed communication equipment 500 includes Figure 4 A clock synchronization device, therefore, has the same clock synchronization function as... Figure 4 The same beneficial effects as clock synchronization devices are not elaborated here.

[0069] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0070] The clock synchronization method, clock synchronization device, and high-speed communication equipment provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A clock synchronization method, characterized in that, The method includes: Based on the first phase error signal predicted from the previous clock signal, the current clock input signal is compensated to obtain the compensated current clock input signal; Determine the current phase error of the compensated current clock input signal; The current phase error is input into a first compensation loop and a second compensation loop. The first compensation loop is used to generate a first clock adjustment signal to adjust the current phase error. The first compensation loop has a circuit delay. The second compensation loop is used to predict a new phase error generated during the circuit delay of the first compensation loop and generate a second clock adjustment signal for the new phase error. The first clock adjustment signal and the second clock adjustment signal are synthesized by calculation to obtain the third clock adjustment signal; The next clock input signal is adjusted based on the third clock adjustment signal.

2. The method according to claim 1, characterized in that, The determination of the current phase error of the compensated current clock input signal includes: Based on a preset algorithm, the compensated current clock input signal is processed to obtain the current phase error.

3. The method according to claim 1, characterized in that, The first compensation loop includes a delay simulation model; Input the current phase error into the first compensation loop, including: The current phase error is input into the delay simulation model to obtain the first clock adjustment signal, wherein the delay simulation model has data storage characteristics and the output first clock adjustment signal has circuit delay characteristics.

4. The method according to claim 1, characterized in that, The current phase error is input into the second compensation circuit, including: The current phase error is input into the prediction model, which then predicts the second clock adjustment signal. The second clock adjustment signal is used to compensate for the circuit delay of the first compensation loop.

5. The method according to claim 1, characterized in that, The step of synthesizing the first clock adjustment signal and the second clock adjustment signal through calculation to obtain the third clock adjustment signal includes: The first clock adjustment signal and the second clock adjustment signal are added together to obtain the third clock adjustment signal; Alternatively, the third clock adjustment signal can be obtained by subtracting the first clock adjustment signal from the second clock adjustment signal.

6. The method according to claim 1, characterized in that, The adjustment of the next clock input signal based on the third clock adjustment signal includes: The third clock adjustment signal is transmitted to the sampling control unit, which drives the analog-to-digital converter to adjust the sampling phase based on the third clock adjustment signal, so that the analog-to-digital converter samples at the peak or trough of the analog signal.

7. The method according to claim 1, characterized in that, The method further includes the following: The current phase error is input to the first compensation loop and the second compensation loop before it is passed. The current phase error is subjected to loop filtering to obtain a current phase error that meets the preset smoothness condition.

8. A clock synchronization device, characterized in that, The device includes: The clock input compensation module is used to compensate the current clock input signal based on the first phase error signal predicted from the previous clock signal, so as to obtain the compensated current clock input signal. The phase error determination module is used to determine the current phase error of the compensated current clock input signal; The loop adjustment signal module inputs the current phase error into a first compensation loop and inputs the current phase error into a second compensation loop. The first compensation loop is used to generate a first clock adjustment signal to adjust the current phase error. The first compensation loop has a circuit delay. The second compensation loop is used to predict a new phase error generated during the circuit delay of the first compensation loop and generate a second clock adjustment signal for the new phase error. The second phase error generation module is used to synthesize the first clock adjustment signal and the second clock adjustment signal through calculation to obtain the third clock adjustment signal; The next clock adjustment module is used to adjust the next clock input signal based on the third clock adjustment signal.

9. The clock synchronization device according to claim 8, characterized in that, The first compensation loop includes a delay simulation model; the loop adjustment signal module is specifically used for: The current phase error is input into the delay simulation model to obtain the first clock adjustment signal, wherein the delay simulation model has data storage characteristics and the output first clock adjustment signal has circuit delay characteristics.

10. The clock synchronization device according to claim 8, characterized in that, The loop adjustment signal module is specifically used for: The current phase error is input into the prediction model, which then predicts the second clock adjustment signal. The second clock adjustment signal is used to compensate for the circuit delay of the first compensation loop.

11. The clock synchronization device according to claim 8, characterized in that, The second phase error generation module is specifically used for: The first clock adjustment signal and the second clock adjustment signal are added together to obtain the third clock adjustment signal; Alternatively, the third clock adjustment signal can be obtained by subtracting the first clock adjustment signal from the second clock adjustment signal.

12. The clock synchronization device according to claim 8, characterized in that, The next clock adjustment module is specifically used for: The third clock adjustment signal is transmitted to the sampling control unit, which drives the analog-to-digital converter to adjust the sampling phase based on the third clock adjustment signal, so that the analog-to-digital converter samples at the peak or trough of the analog signal.

13. A high-speed communication device, characterized in that, The high-speed communication device includes a clock synchronization device as described in any one of claims 8 to 12.

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