A voltage trim test method combining a lookup table method with full value simulation or dichotomy
By combining the lookup table method with full value simulation or bisection method for voltage trim testing, the problem of balancing high accuracy and low time cost in existing technologies is solved, and efficient testing of voltage, current and frequency trimming is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TIANJIN WEICHI SEMICONDUCTOR TECHNOLOGY CO LTD
- Filing Date
- 2026-02-03
- Publication Date
- 2026-06-12
AI Technical Summary
Existing Trim testing methods cannot simultaneously meet the requirements of high accuracy and low time cost. The accuracy of the lookup table method depends on the precision of the mapping table and is difficult to adapt to individual device differences. The full value simulation method and the binary search method have excessively high testing time and cost when adjusting code values on a large scale.
By combining the lookup table method with full value simulation or binary search, the initial adjustment code value can be quickly located by the lookup table method. After narrowing down the range, full value simulation or binary search is used for precise search. Combined with the synchronous acquisition characteristics of the HDCTO board, the writing of the adjustment code value and voltage acquisition can be carried out synchronously.
While ensuring test accuracy, it significantly reduces test time, making it suitable for voltage, current, and frequency tuning scenarios. It improves test accuracy and keeps test time increase to a very small range.
Smart Images
Figure CN121633797B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor testing technology, specifically a voltage trim test method combining a lookup table method with full value simulation or a binary search method. Background Technology
[0002] In the semiconductor chip production and testing process, the Trim test is a key step to ensure the accuracy of the chip's output parameters. The Trim test adjusts the trim code value of the chip's internal registers to make the chip's output voltage, current, or frequency parameters meet the design specifications.
[0003] Existing Trim testing methods mainly include full value simulation method, least significant bit-based deviation correction method, differential bit weight adjustment method, nonlinear trimming curve fitting method, bisection search method, table lookup method, successive approximation method, and other schemes.
[0004] Among the methods mentioned above, the full-value simulation method, the binary search method, and the successive approximation method have high tuning accuracy and can accurately locate the optimal tuning code value. However, these methods have obvious shortcomings when faced with a large number of tuning code values: the full-value simulation method needs to traverse all possible tuning code values and measure the corresponding output parameters one by one. When the number of tuning code values is large, the test time increases significantly, resulting in a substantial increase in test costs; although the binary search method and the successive approximation method reduce the number of searches, they still require multiple measurement operations, and the overall efficiency needs to be improved.
[0005] The lookup table method establishes a mapping table between the trimming code value and the output parameter in advance, and directly retrieves the trimming code value during testing. It has the advantage of short testing time. However, the accuracy of the lookup table method depends on the precision of the mapping table and is difficult to adapt to individual device differences, resulting in low accuracy. In addition, establishing a high-precision mapping table requires large-scale parameter data acquisition, but in the actual chip testing process, there are often insufficient data collection conditions.
[0006] Therefore, relying solely on any existing Trim testing method is insufficient to simultaneously meet the dual requirements of high accuracy and low time cost. An improved solution that can balance testing efficiency and testing accuracy is needed. Summary of the Invention
[0007] To address the shortcomings of existing technologies, the present invention aims to provide a voltage trim test method that combines a lookup table method with full value simulation or a bisection method. By combining the lookup table method with the precise search method, the test accuracy is guaranteed while reducing the test time cost.
[0008] To achieve the above objectives, the present invention adopts the following technical solution:
[0009] A voltage trim test method combining table lookup and full-value simulation or bisection method includes the following steps:
[0010] By using a lookup table method based on the pre-stored mapping relationship between the adjustment code value and the voltage, an initial adjustment code value that is approximately the adjustment target value is determined.
[0011] Based on the initial modifier code value, a subset of modifier code values including the initial modifier code value and the modifier code values within a preset range before and after it is defined;
[0012] Within the subset of adjustment code values, a target adjustment code value matching the adjustment target value is determined using an exact search method.
[0013] Furthermore, the precise search method is a full-value simulation method, which includes: executing a micro-instruction test pattern through a data acquisition module, and traversing and writing each modifier code value in the modifier code value subset in the micro-instruction test pattern;
[0014] The data acquisition module synchronously acquires the voltage data corresponding to each modifier code value to form a subset voltage mapping set.
[0015] The adjustment code value with the smallest deviation from the adjustment target value is selected from the subset voltage mapping set and used as the target adjustment code value.
[0016] Furthermore, the data acquisition module is an HDCTO board of a semiconductor testing platform, and the microinstruction test pattern is a microinstruction test pattern that includes a trimming code value writing instruction and a voltage acquisition instruction.
[0017] Furthermore, the precise search method is a binary search method, which includes setting the boundary values of the subset of modifier codes as the upper and lower limits of the search interval;
[0018] Calculate the intermediate modifier code value of the search interval, and measure the voltage value corresponding to the intermediate modifier code value;
[0019] The voltage value is compared with the adjustment target value, and the search range is updated based on the comparison result;
[0020] Repeat the steps of calculating intermediate adjustment code values, measuring voltage values, and updating the search interval until the search interval converges to a single adjustment code value, and use that adjustment code value as the target adjustment code value.
[0021] Furthermore, the step of updating the search interval based on the comparison result specifically involves: based on the positive correlation between the adjustment code value and the output voltage value, when the voltage value is less than the adjustment target value, setting the intermediate adjustment code value as a new lower limit value;
[0022] When the voltage value is greater than the adjustment target value, the intermediate adjustment code value is set to a new upper limit value.
[0023] Furthermore, the preset range is determined based on the adjustment accuracy requirements and device characteristics, the value of N is a positive integer from 1 to 20, and the number of the subset of adjustment code values is N adjustment code values before and after the initial adjustment code value.
[0024] Furthermore, when the voltage trim test depends on the pre-trimming result, the method further includes: obtaining the pre-trimming code value generated by the pre-trimming test;
[0025] Each modifier code value in the subset of modifier code values is combined with the preceding modifier code value to generate a combined modifier code value sequence.
[0026] When performing the full-value simulation method, the combined modified code value sequence is used for traversal writing and voltage acquisition.
[0027] Furthermore, each modifier code value in the modifier code value subset is combined with the preceding modifier code value, and the value of the modifier code value written to the vector in the microinstruction test pattern is dynamically modified through the modify function of the HRAM module of the semiconductor test platform.
[0028] Furthermore, the criterion for determining the target adjustment code value that matches the adjustment target value is: the absolute deviation between the voltage value corresponding to the target adjustment code value and the adjustment target value is the smallest among all voltage values corresponding to the subset of adjustment code values.
[0029] The beneficial effects of this invention are as follows:
[0030] This invention combines the lookup table method with the full value simulation method or the binary search method. The lookup table method is used to quickly locate the initial adjustment code value, narrowing the range of precise search. Then, the full value simulation method or the binary search method is used to perform precise search within the narrowed range, which not only ensures the accuracy of the test, but also significantly reduces the test time.
[0031] This invention fully utilizes the feature of the HDCTO board that can directly acquire voltage values in the micro-instruction test pattern, and integrates the main part of the adjustment test into the process of configuring the pattern adjustment register, realizing the synchronous writing of adjustment code value and voltage acquisition, and further reducing the test time.
[0032] The combination of lookup table method and full value simulation provided by this invention can handle complex scenarios where the current adjustment depends on the previous adjustment result. By dynamically modifying the microinstruction test pattern through the HRAM's modify function, flexible adjustment code value combination is achieved.
[0033] The combination of lookup table method and binary search method provided by this invention has a wider range of applications, not only applicable to voltage adjustment, but also to current adjustment and frequency adjustment scenarios.
[0034] Actual testing has verified that the method of this invention significantly improves the test accuracy (CPK value) and increases the test time by about 5 milliseconds (testing 8 test bits simultaneously), achieving the goal of low time cost while ensuring high accuracy. Attached Figure Description
[0035] Figure 1 This is an overall flowchart of the voltage trim test method provided in the embodiments of the present invention;
[0036] Figure 2 The flowchart of the combination of table lookup method and full value simulation method provided in the embodiments of the present invention is as follows:
[0037] Figure 3 The flowchart of the combined lookup table method and binary search method provided in the embodiments of the present invention is as follows:
[0038] Figure 4 This is a flowchart of the full-value simulation method for voltage acquisition provided in an embodiment of the present invention;
[0039] Figure 5 This is a test flowchart that depends on the results of prior adjustments, as provided in an embodiment of the present invention. Detailed Implementation
[0040] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0041] like Figure 1 As shown, the present invention provides a voltage trim test method that combines a lookup table method with full value simulation or a bisection method, which includes three stages: initial positioning stage, range delineation stage, and precise search stage.
[0042] In the initial positioning stage, an initial adjustment code value that is close to the adjustment target value is determined by a lookup table method based on the pre-stored adjustment code value and voltage mapping relationship. The lookup table method is based on a pre-established adjustment code value-voltage mapping table, which records the typical voltage output values corresponding to different adjustment code values. When the adjustment target value is given, the lookup table method searches for the voltage value that is closest to the target value in the mapping table and returns the corresponding adjustment code value as the initial adjustment code value. The advantage of the lookup table method is that the lookup speed is fast and the initial positioning can be completed in a very short time.
[0043] During the range definition stage, based on the initial adjustment code value, a subset of adjustment code values is defined that includes the initial adjustment code value and the preset range before and after it. The preset range is determined according to the adjustment accuracy requirements and device characteristics, and is usually set to N adjustment code values before and after the initial adjustment code value. For example, if the initial adjustment code value is 100 and the preset range is 5 before and after, the subset of adjustment code values includes 11 adjustment code values from 95 to 105. By defining the subset of adjustment code values, the range of full value simulation or binary search is narrowed from the full range of adjustment code values to a finite subset range, which significantly reduces the workload of subsequent accurate search.
[0044] In the precise search phase, within the subset of adjustment code values, the target adjustment code value that matches the adjustment target value is determined by the precise search method. The precise search method includes two implementation methods: full value simulation method and binary search method, which can be selected according to the test scenario and resource configuration.
[0045] Example 1: Combination of table lookup method and full value simulation method
[0046] like Figure 2 As shown, this embodiment provides a specific implementation process for the combination of the lookup table method and the full value simulation method, which is applicable to voltage Trim test scenarios and requires the voltage measurement pin to be connected to the HDCTO acquisition resources of the semiconductor test platform.
[0047] First, perform the table lookup and positioning step. Based on the pre-stored adjustment code value-voltage mapping table, input the adjustment target voltage value and look up the table to obtain the initial adjustment code value that is closest to the target value.
[0048] Next, the subset delineation step is performed. Taking the initial modifier code value as the center, a preset number of modifier code values are expanded forward and backward to form a subset of modifier code values. For example, if the expansion range is set to 8 modifier code values before and after, and the initial modifier code value is 50, then the subset includes 17 modifier code values from 42 to 58.
[0049] Then, perform the full-value simulation steps, such as... Figure 4 As shown, the micro-instruction test pattern is executed through the HDCTO board. Each trimming code value in the trimming code value subset is written sequentially in the pattern. The HDCTO board synchronously collects the voltage value corresponding to each trimming code value. After all the encoding is completed, a subset voltage mapping set is formed. This mapping set records the one-to-one correspondence between each trimming code value and its corresponding voltage value in the subset.
[0050] The HDCTO board is a high-speed data acquisition module of the J750 semiconductor test platform. It has the ability to acquire analog signals in real time during the execution of the micro-instruction test pattern. By integrating the trimming code value writing instruction and the voltage acquisition instruction into the same micro-instruction test pattern, it realizes the synchronous execution of trimming code value setting and voltage measurement, avoiding the time overhead of additional measurement operation required after setting the trimming code value in the traditional method.
[0051] Finally, the target selection step is performed, traversing the subset voltage mapping set, calculating the absolute deviation between each voltage value and the trimming target value, and selecting the trimming code value with the smallest absolute deviation as the target trimming code value. The target trimming code value is the final result of this Trim test and will be written into the chip's trimming register.
[0052] Example 2: Combination of table lookup method and binary search method
[0053] like Figure 3 As shown, this embodiment provides a specific implementation process for the combination of the lookup table method and the binary search method, which has a wider range of applications and can be used for voltage Trim, current Trim and frequency Trim testing scenarios.
[0054] First, the lookup table is executed, which is the same as in Example 1, to obtain the initial adjustment code value based on the pre-stored mapping table.
[0055] Next, the subset delineation step is performed, which is the same as in Example 1, using the initial modifier code value as a basis to delineate the modifier code value subset.
[0056] Then, perform a binary search step, setting the minimum value of the subset of modifier values as the lower limit of the search interval (Low), and the maximum value as the upper limit of the search interval (High). Calculate the middle modifier value (Mid) of the search interval using the following formula:
[0057] ;
[0058] in, This represents the lower limit modifier value of the current search range. This indicates the upper limit of the current search range, and the modifier value. This represents the calculated intermediate trimming code value. This indicates the floor function.
[0059] Adjust the intermediate code value Write to the chip's trim register and measure the corresponding voltage value. The measured voltage value With adjustment target value Compare them.
[0060] like This indicates that the voltage corresponding to the current adjustment code value is too low, and it is necessary to search towards a larger adjustment code value to adjust the intermediate adjustment code value. Set as the new lower limit value, i.e. .
[0061] like This indicates that the voltage corresponding to the current trimming code value is too high, and it is necessary to search towards smaller trimming code values to adjust the intermediate trimming code value. Set as the new upper limit value, i.e. .
[0062] like This indicates that a perfect match for the modifier code value has been found, and the modifier code can be directly applied. As the target modifier code value.
[0063] Repeat the steps of calculating intermediate values, measuring voltage, and comparing and updating until the search interval converges. At this point, comparison and The deviation between the corresponding voltage value and the target value is used to select the correction code value with the smaller deviation as the target correction code value.
[0064] The number of searches in the binary search method is logarithmically related to the size of the subset of modified code values. If the subset contains Each modification code value requires a maximum of The search can be completed in one iteration, where This represents the floor function, which, compared to the full value simulation method, requires traversing all values. The individual adjustment code value and the binary search method significantly reduce the number of measurements, making it suitable for scenarios with higher requirements for test time.
[0065] Example 3: Test Scenario Relying on Pre-tuning Results
[0066] like Figure 5 As shown, in actual chip testing, some trimming parameters are dependent on each other. The current Trim test depends on the results of the previous Trim test. For example, the chip's output voltage trimming may require the reference voltage trimming to be completed first. The current voltage trimming result will be affected by the reference voltage trimming code value. In this scenario, it is impossible to determine in advance the fixed value that needs to be written to the trimming register. It needs to be dynamically adjusted according to the actual results of the previous trimming.
[0067] This embodiment provides a specific solution for handling scenarios that depend on the results of a prior adjustment test. First, a prior adjustment test is performed to obtain the prior adjustment code value generated by the prior adjustment test. Then, the table lookup and subset delineation steps are performed to obtain the initial adjustment code value and the subset of adjustment code values.
[0068] Next, each adjustment code value in the adjustment code value subset is combined with the previous adjustment code value to generate a combined adjustment code value sequence. The combination method is determined according to the structure of the chip adjustment register. Usually, the previous adjustment code value is written into the high-order field of the register, and the current adjustment code value is written into the low-order field of the register.
[0069] The combination process is implemented through the HRAM module of the semiconductor test platform. The HRAM module has a modify function, which can dynamically modify the value of a specified vector in the pattern before the microinstruction test pattern is executed. Specifically, the modifier code value is set in the microinstruction test pattern in advance and written into the placeholder of the vector. Before the test is executed, the HRAM modify function replaces the placeholder with the actual combination modifier code value.
[0070] After generating the combined adjustment code value sequence, the full value simulation step is executed. The pattern is tested by the HDCTO microinstruction. Each combined value written in the combined adjustment code value sequence is traversed, and the corresponding voltage data is collected to form a subset voltage mapping set. The combined adjustment code value with the smallest deviation from the adjustment target value is selected from the mapping set, and the current adjustment code value part is extracted as the target adjustment code value.
[0071] The technical solution of this embodiment can flexibly handle complex scenarios with multi-level adjustment dependencies, ensuring test accuracy under dynamic conditions.
[0072] Example 4: Verification of Test Results
[0073] The method of this invention is used to perform voltage trim testing on a certain type of chip. The testing platform is an automatic testing device (such as J750). The test items include adjustment tests of multiple voltage parameters.
[0074] Test results show that the process capability index (CPK) of each test item is significantly improved after adopting the method of this invention. Taking the VBG_chop_af_meas test item as an example, the CPK value was 1.08 before modification and increased to 2.59 after modification. The CPK value of the VBG_v1p0_ov_af_meas test item increased from about 2.18 to about 7.02, and the CPK value of the hirc_meas_af_ac test item increased from about 0.18 to about 1.27. The improvement in CPK value indicates that the consistency and accuracy of the test results are significantly improved.
[0075] Regarding testing time, the overall testing time increases by about 5 milliseconds (testing 8 test bits simultaneously) after adopting the method of this invention. Compared with the significant time increase caused by the pure full-value simulation method which requires traversing all the adjustment code values, this invention reduces the search range in advance by using a lookup table method, keeping the time increment within a very small range, thus achieving a balance between high accuracy and low time cost.
[0076] In summary, the voltage trim test method provided by this invention combines the advantages of rapid positioning of the lookup table method with the high accuracy of the full value simulation method and the binary search method, and combines the synchronous acquisition characteristics of the HDCTO board to achieve dual optimization of test efficiency and test accuracy. It has good practical value and prospects for widespread application.
Claims
1. A voltage trim test method combining table lookup method with full value simulation or bisection method, characterized in that, Includes the following steps: By using a lookup table method based on the pre-stored mapping relationship between the adjustment code value and the voltage, an initial adjustment code value that is approximately the adjustment target value is determined. Based on the initial modifier code value, a subset of modifier code values including the initial modifier code value and the modifier code values within a preset range before and after it is defined; Within the subset of adjustment code values, a target adjustment code value matching the adjustment target value is determined using an exact search method; The exact search method is either full value simulation or binary search.
2. The voltage trim test method according to claim 1, characterized in that, The precise search method is a full-value simulation method, which includes: The microinstruction test pattern is executed by the data acquisition module, and each modifier code value in the modifier code value subset is traversed and written in the microinstruction test pattern. The data acquisition module synchronously acquires the voltage data corresponding to each modifier code value to form a subset voltage mapping set. The adjustment code value with the smallest deviation from the adjustment target value is selected from the subset voltage mapping set and used as the target adjustment code value.
3. The voltage trim test method according to claim 2, characterized in that, The data acquisition module is the HDCTO board of the semiconductor test platform, and the microinstruction test pattern is a microinstruction test pattern that includes a trimming code value writing instruction and a voltage acquisition instruction.
4. The voltage trim test method according to claim 1, characterized in that, The exact search method is a binary search method, which includes: Set the boundary values of the subset of modifier codes as the upper and lower limits of the search interval; Calculate the intermediate modifier code value of the search interval, and measure the voltage value corresponding to the intermediate modifier code value; The voltage value is compared with the adjustment target value, and the search range is updated based on the comparison result; Repeat the steps of calculating intermediate adjustment code values, measuring voltage values, and updating the search interval until the search interval converges to a single adjustment code value, and use that adjustment code value as the target adjustment code value.
5. The voltage trim test method according to claim 4, characterized in that, The specific steps for updating the search interval based on the comparison results are as follows: Based on the positive correlation between the adjustment code value and the output voltage value, when the voltage value is less than the adjustment target value, the intermediate adjustment code value is set as a new lower limit value. When the voltage value is greater than the adjustment target value, the intermediate adjustment code value is set to a new upper limit value.
6. The voltage trim test method according to claim 1, characterized in that, The preset range is determined based on the adjustment accuracy requirements and device characteristics. The value of N is a positive integer from 1 to 20. The number of the subset of adjustment code values is N adjustment code values before and after the initial adjustment code value.
7. The voltage trim test method according to claim 2, characterized in that, When the voltage trim test depends on the result of a prior adjustment, the method further includes: Obtain the pre-tuning code value generated by the pre-tuning test; Each modifier code value in the subset of modifier code values is combined with the preceding modifier code value to generate a combined modifier code value sequence. When performing the full-value simulation method, the combined modified code value sequence is used for traversal writing and voltage acquisition.
8. The voltage trim test method according to claim 7, characterized in that, The modifier values in the subset of modifier values are combined with the preceding modifier values, and the values of the modifier values written to the vector in the microinstruction test pattern are dynamically modified by the modify function of the HRAM module of the semiconductor test platform.
9. The voltage trim test method according to claim 1, characterized in that, The criterion for determining the target correction code value that matches the correction target value is: the absolute deviation between the voltage value corresponding to the target correction code value and the correction target value is the smallest among all voltage values corresponding to the subset of correction code values.