An edge algorithm network coordination scheduling system for high-speed rail platform end security response sinking

Abstract

The application relates to the technical field of electric digital data processing, and discloses an edge algorithm network cooperative scheduling system for high-speed rail platform end safety response sinking, which comprises a processor core used for processing a safety task; a data acquisition module used for acquiring a video data stream; a scheduling and distribution module used for calculating a bit rate change parameter and predicting a load, and used for issuing a storage isolation control word containing a task identifier and a space index when a burst condition is met; a memory management module used for intercepting an addressing request and modifying a page table item memory attribute bit to configure a private address domain; and a cache consistency filtering module used for identifying a memory access state, and used for shielding a cache line state sniffing request generated by a consistency protocol at a hardware level; the application eliminates micro-architecture level performance attenuation caused by inter-core consistency protocols through physical layer silence isolation, and ensures the predictability of safety algorithm processing delay in a complex interference environment.

Description

Technical Field

[0001] This invention relates to an edge computing network collaborative scheduling system for the security response sinking at the end of high-speed railway platforms, belonging to the field of electronic digital data processing technology. Background Technology

[0002] Currently, edge computing nodes are widely deployed in the field of security monitoring at high-speed railway platforms in electronic digital data processing systems. They are used to handle concurrent tasks such as video decoding, background modeling, and boundary crossing detection. The general operating system kernel scheduler allocates processor resources through a fair scheduling strategy to balance the performance of multi-task operation.

[0003] The security scenario at high-speed railway platforms is characterized by strong data sparsity and suddenness. When there are no trains entering or exiting or any abnormal intrusions, the system's computational load is low. However, once an abnormality occurs, the entropy of the image data surges instantaneously. Because general task scheduling methods are difficult to perceive the security semantics of the application layer, the allocation of computing power often lags behind the rate at which physical risks occur. Constrained by the bus bandwidth between the edge device's video memory and main memory, task switching under high load is accompanied by cache invalidation. In a multi-core parallel environment, the inter-core cache coherence protocol generates a large number of bus sniffing signals when non-security cores process high-frequency memory access tasks, forcing the security core to check the cache line status. This instruction execution pause induced by the hardware microarchitecture causes nonlinear jitter in image frame processing time, compromising the real-time response of the entire link. The platform environment is complex, and relying solely on front-end sensing... Hardware adjustments, such as the placement of known equipment, are insufficient to withstand environmental noise and signal attenuation. Software control also has shortcomings. For example, Chinese invention patent application CN120735826A discloses an intrusion detection and early warning alarm system for high-speed rail platform areas. While this system enhances recognition accuracy by constructing a multimodal environmental rhythm baseline and actively injecting micro-perturbations, its core operating mechanism still relies on a general computing framework. It cannot penetrate the operating system kernel to achieve preemptive physical isolation of processor resources. Because it fails to address hardware resource contention at the microarchitecture level, it still suffers from impaired end-to-end response time due to frequent cache line flips and kernel scheduling delays in the face of sudden computational leaps. This makes it difficult to meet the requirement of absolutely predictable processing latency in security algorithms under extreme interference environments.

[0004] Therefore, the technical problem to be solved by this invention is how to implement preemptive scheduling of processor resources based on the characteristics of security data flow, and avoid hardware resource contention interference from the microarchitecture level to ensure deterministic response. Summary of the Invention

[0005] To address the problems mentioned in the background art, the technical solution of the present invention is as follows: An edge computing network collaborative scheduling system for security response decentralization at the end of high-speed railway platforms, comprising:

[0006] The data acquisition module is used to acquire video data streams from the security monitoring area at the end of the high-speed railway platform and input the video data streams into the security task.

[0007] The scheduling and allocation module is used to obtain the bit rate change parameters of the video data stream, perform load prediction based on the mapping relationship between the bit rate change parameters and the preset risk threshold, and generate and send a storage isolation control word containing a task identifier and address space index to the memory management module when it is determined that the preset burst access conditions are met.

[0008] The memory management module is used to receive storage isolation control words, intercept virtual address access requests from security tasks, and modify the memory attribute control bits in the physical page table entries corresponding to the security tasks according to the task identifier and address space index, so as to configure the physical storage space mapped by the security tasks as the private address domain of the processor core.

[0009] The cache coherence filtering module, integrated into the processor bus controller, is used to identify the memory access status of private address domains and, at the hardware logic level, shield the cache line status sniffing requests generated by the inter-core coherence protocol on the processor cores performing security tasks.

[0010] Preferably, the scheduling and allocation module includes: a monitoring unit for acquiring the bitrate gradient value of the video data stream; and a logic determination unit for triggering the logic of sending the storage isolation control word when the bitrate gradient value exceeds a preset risk slope threshold.

[0011] Preferably, the system further includes a bus arbitration module, used to inject a bus occupancy wait period into the processor core executing non-security tasks during the security task execution cycle, so as to create access gaps for non-security tasks at the physical bus layer.

[0012] Preferably, the system further includes a power management module for locking the dynamic frequency adjustment logic of the processor core during the period when the storage isolation control word is in effect, so as to suppress clock cycle jitter of the edge computing node during load fluctuations.

[0013] Preferably, the memory management module is also used to perform shadow page table preheating processing, calculate the shadow page table pre-storage depth by obtaining the second-order rate of change of the video data stream bit rate, and, in conjunction with the memory attribute control bit settings in the physical page table entries, preload address translation entries at the moment of security task switching.

[0014] Preferably, the calculation of the shadow page table pre-store depth is based on acceleration parameters. acceleration parameters The calculation logic is as follows: ,in, For the real-time bitrate of the video data stream, Sampling time, its dimension is The memory management module determines the speedup parameters based on the memory management parameters. The numerical value adjusts the number of preloaded entries in the shadow page table warm-up process.

[0015] Preferably, the memory management module is also used to perform cache index conflict suppression processing. By performing physical page table address remapping on non-security processes, the physical memory access address of non-security processes is avoided from the cache index bit of the processor core executing security tasks, so as to eliminate cache line replacement competition under the set-associative mapping rule.

[0016] Preferably, the system further includes an edge gateway module, used to obtain the difference in computing power load between the edge computing node and the cloud server, and to migrate subtasks in the security task whose computing density exceeds a preset floating-point operation threshold to a preset edge execution node.

[0017] Preferably, when performing signal masking, the cache consistency filtering module is also used to intercept bus invalidation broadcast signals generated by write tasks performed by non-security cores, so as to keep the cache line corresponding to the security task in an exclusive modification state.

[0018] Preferably, the processor core includes multiple physical cores, and the scheduling and allocation module adjusts the number of online physical cores participating in the execution of security tasks based on the instantaneous change in the feature entropy of the video data stream; the feature entropy is obtained by statistically analyzing the pixel probability distribution of key frames in the video data stream.

[0019] Compared with the prior art, the beneficial effects of the present invention are:

[0020] 1. In the edge computing network for security response, by establishing a direct mapping relationship between the underlying physical characteristics of security data streams and processor instruction set scheduling, the security task is moved from data-driven to hardware execution layer with zero latency intervention. The system monitors the first derivative of the bit rate at the bottom layer of the transmission protocol stack in real time, and uses the nonlinear step of the video stream compression residual as a trigger signal to move the security task instruction set into and latch it in the first-level cache, so that the starting point of instruction execution is moved forward to the protocol stack driver layer. This eliminates the nonlinear latency caused by context switching and semantic waiting in traditional solutions, and ensures that security tasks receive immediate computing power allocation in case of emergencies.

[0021] 2. Through multi-dimensional collaboration of instruction space latching, bus bandwidth quota adjustment, and processor frequency minimum lock, a highly deterministic physical execution environment is constructed for security tasks in both time and space dimensions. While triggering computing power preemption, the system injects bus wait cycles into the memory access controller, artificially creating access gaps for non-security tasks at the hardware level to ensure the transmission bandwidth of security data streams on the system bus. Combined with the forced suspension of dynamic voltage regulation and frequency reduction logic by the power management unit, this solution eliminates the clock reference collapse of edge devices under extreme load and heat-limited conditions, transforming the processing latency of security algorithms from statistical stability to a quasi-constant physical level, achieving predictability of the end-to-end response under complex interference environments.

[0022] 3. By using a silent inter-core consistency mechanism based on dynamic modification of page table attributes, implicit interference in multi-core parallel environments is eliminated at the microarchitecture level. By modifying the memory sharing control bit in the physical page table entry of the security task, the corresponding physical memory region is marked as the private exclusive domain of the current processor core. At the hardware level, the inter-core consistency protocol's state sniffing requests to the security core cache line are blocked. This method eliminates the bus sniffing transaction interference caused by non-security cores executing background transactions, prevents frequent cache line state flips, and enables the security core to achieve silent isolation at the physical level. Attached Figure Description

[0023] Fig. 1 This is a flowchart of the security task hardware isolation control process of the edge computing network collaborative scheduling system of the present invention;

[0024] Fig. 2 This is a schematic diagram of the edge computing node hardware resource isolation and cloud-edge collaborative architecture of the present invention. Detailed Implementation

[0025] The following detailed description of the edge computing network collaborative scheduling system for security response at the end of high-speed railway platforms, in conjunction with the accompanying drawings and specific embodiments, further illustrates the present invention. It should be noted that, unless otherwise specified, the following embodiments and features can be combined with each other, and the following embodiments are only used to explain the present invention and do not constitute a limitation on the scope of protection of the present invention.

[0026] This invention provides an edge computing network collaborative scheduling system for security response at high-speed railway platform ends, comprising a processor core, a data acquisition module, a scheduling and allocation module, a memory management module, and a cache consistency filtering module. The processor core executes security identification algorithm instructions. The data acquisition module acquires video data streams from the monitoring area at the high-speed railway platform end and inputs them into the security task. The scheduling and allocation module monitors the bit rate variation characteristics of the video data stream in real time and calculates the load prediction value. When a sudden access condition is met, it generates a storage isolation control word containing a task identifier and an address space index. The memory management module receives the storage isolation control word and modifies the memory attribute control bits in the physical page table entry corresponding to the security task. The cache consistency filtering module identifies the memory access status of private address domains and blocks bus sniffing requests generated by the inter-core consistency protocol. To cope with the instantaneous step increase in computational load caused by sudden changes in lighting or target intrusion in the high-speed railway platform end scenario, the monitoring unit in the scheduling and allocation module uses a preset sampling period. Real-time bitrate of video data stream acquisition The logic decision unit determines the outcome based on the formula. Calculate the bit rate gradient value ; This is the bit rate gradient value, in units of ; This represents the change in bit rate within the sampling period, in units of... ; The sampling period is expressed in units of 10 ... When the bit rate gradient value Exceeding the preset risk slope threshold When the system determines that the burst access condition is met, the scheduling and allocation module reads the memory region structure in the process descriptor corresponding to the security task through the system bus, and extracts the physical page frame number pre-allocated in the linear address space for the security task. The logic determination unit maps the physical page frame number to a hardware address mask with a fixed offset, and fills the storage isolation control word with the hardware address mask as an address space index, so that the memory management module can lock the physical storage page whose attributes are to be modified during the memory access phase of instruction execution based on the address space index.

[0027] To address the execution pauses induced by cache coherence protocols in multi-core parallel environments, the memory management module receives the storage isolation control word, intercepts virtual addressing requests from security tasks, and modifies the memory attribute control bits in the physical page table entries corresponding to the security task based on the address space index. This configures the physical storage space mapped to the security task as a private address domain for the processor core. The cache coherence filtering module integrated into the processor bus controller identifies the memory access status of this private address domain and, at the hardware logic level, shields the cache line status sniffing requests generated by the inter-core coherence protocol on the processor core executing the security task. Simultaneously, it intercepts bus invalidation broadcast signals generated by write tasks executed by non-security cores to maintain the cache line corresponding to the security task in an exclusive modification state. Through this hardware isolation mechanism based on dynamic modification of physical page table attributes, the system eliminates the implicit interference of multi-core resource contention at the microarchitecture level, transforming the response latency of the security identification task into a quasi-constant value at the physical level. The scheduling and allocation module determines the bit rate gradient value. Exceeding the preset risk slope threshold At that time, a storage isolation control word containing a task identifier and an address space index is issued to the memory management module through a dedicated hard core register interface. The hardware logic directly modifies the memory attribute control bits of the page table entries in the conversion detection buffer. The physical storage space corresponding to the security task is configured as the private address domain of the processor core. Physical address redirection is performed during the instruction memory access phase to avoid timing uncertainties caused by the software layer address space management logic during the task preemption phase.

[0028] Before the cache consistency filtering module enables the masking logic, it executes instructions to write back and invalidate physical page frame cache lines for private address domains. Non-security cores retain dirty data in the L2 or L3 cache and synchronize it to the physical storage medium. The processor bus controller intercepts sniffing requests matching the task identifier and sends back a clean state response, masking the bus arbitration occupancy caused by the inter-core consistency protocol on the processor core executing security tasks, ensuring that the security core maintains an exclusive cache line modification state during the execution cycle. To eliminate addressing pauses caused by virtual address translation failures during security task preemption transients, the memory management module performs shadow page table preheating processing, which obtains the second-order rate of change of the video data stream bitrate and calculates acceleration parameters. ;in, For acceleration parameters, the unit is... , For real-time bit rate, For sampling time, the memory management module determines the time based on acceleration parameters. The shadow page table pre-store depth is adjusted by magnitude, and before the security core executes the context switch, the target page table entries are pre-loaded into the conversion detection buffer and the path latching process is performed. At the same time, after the power management module detects that the storage isolation control word is in effect, it locks the dynamic frequency adjustment logic of the processor core, fixes the core frequency at the rated highest frequency point, and cooperates with the bus arbitration module to inject bus occupancy wait cycles into the cores executing non-security tasks, thereby artificially creating memory access gaps at the physical bus layer and constructing a physical execution environment that is deterministic in both time and space dimensions.

[0029] The feature entropy extraction process is transformed into a physical statistical process of video pixel level changes. The scheduling and allocation module has a built-in Gaussian probability density integrator to capture the distribution density of pixel brightness values ​​in key video frames in real time. During system initialization, the optical zoom ring of the surveillance camera needs to be mechanically adjusted to ensure that the pixel coverage density of the target intrusion area on the imaging plane is not less than 120 pixels / square meter. When an intrusion occurs, the level fluctuation of the image signal causes the statistical envelope output by the integrator to shift. The system defines this shift as an information complexity step. At this time, the scheduling and allocation module does not perform abstract calculations, but activates the processor physical cores in a low-power suspended state in sequence through a step-by-step current injection logic. If the level distribution deviates from the initial static reference range of 25% to 40%, the system automatically connects the power gates of the second group of four physical cores and sets a voltage stabilization settling time of 3.5 microseconds to ensure that the operating frequency of the newly added core is locked at more than 98% of the rated highest frequency point before executing the security algorithm, thereby eliminating the impact of core switching. The logic gate delay fluctuations; the memory isolation process is manifested as hardware-level electrical signal path redirection. The memory management module (MMU) integrates a set of hard-core registers composed of logic gate circuits, which are specifically used to store isolation control words. When the scheduling and allocation module recognizes a burst access signal and issues a control word, the system directly pulls up the level signal of the 62nd bit (reserved attribute bit) in the corresponding physical page table entry. The flip of this level signal will directly control the tri-state buffer gate circuit inside the bus controller, so that it cuts off the sniffing request path of the non-security processor core to this address segment at the physical layer. In this architecture, the establishment process of the private address domain is accompanied by the physical latching action of the L1 cache line. By forcibly clamping the MESI protocol status bit of the memory in this area to the exclusive modification state, the system establishes a logic shield with zero thickness at the hardware level. This change in physical attributes makes the cache line unaffected by electromagnetic interference or protocol contention of external cross-core bus signals during the execution of security identification tasks, ensuring that the physical atomicity latency of data access is controlled within 12 clock cycles.

[0030] Example 1: In the security deployment at the edge of a high-speed railway platform in a large transportation hub, the edge computing network collaborative scheduling system continuously collects ultra-high-definition video surveillance streams from the platform edge area. When a moving target intrudes into the monitored area, causing video residual fluctuations, the data acquisition module obtains the real-time bit rate. exist Sampling period Internally Step to That is, bit rate gradient value achieve The burst level, the logical judgment unit in the scheduling and allocation module determines the bit rate gradient value. Exceeding the preset risk slope threshold Subsequently, a storage isolation control word containing a task identifier and an address space index is generated, thereby directly translating security business requirements into underlying storage isolation instructions. The memory management module receives the storage isolation control word and intercepts the physical addressing requests of the processor core during the execution of security identification tasks. By modifying the memory attribute control bits in the page table descriptor corresponding to the physical storage space mapped by the security task, the memory access attribute is switched from shared to private address domain attribute. This attribute change triggers the cache consistency filtering module in the bus controller to enable the hardware interception mechanism, so that the high-frequency cache sniffing requests generated by non-security cores when executing system backup tasks are blocked by hardware logic before entering the first-level cache of the security core. The physical feature monitoring of the underlying front-end video stream provides a trigger signal for the hardware isolation of the back-end, eliminating the microarchitectural level execution pauses induced by the cache consistency protocol in a multi-core parallel environment.

[0031] When the bit rate shows an accelerating upward trend and the acceleration parameter greater than When the value is in the high range, the memory management module uses the formula... The calculated second-order gradient value is used to dynamically adjust the preheating depth of the shadow page table. This means that before the processor core officially executes the security task switch, the page table entries required for the next stage are preloaded into the translation detection buffer. The address translation prefetching mechanism, combined with the aforementioned privatization of physical page table attributes, constructs an exclusive environment for the processor cache the instant the security task enters the running state. This solves the response latency fluctuations caused by address translation failures and cache line invalidation in multi-core resource contention scenarios for edge computing devices, reducing the single-frame processing latency of security alarm signals from... Reduce and stabilize to Within this framework, by mapping the characteristic parameters of the security video stream to the storage isolation attributes of the underlying hardware, an independent execution channel for security tasks is established at the physical bus level. By using deterministic hardware resource allocation to replace uncertain application-layer software scheduling, the security response is pushed down to the hardware execution layer, ensuring the stability of the time window for issuing security early warning commands under extreme load conditions.

[0032] Example 2: When the system faces a deterministic response verification scenario caused by high-volume memory access contention at the high-speed railway platform end, this experiment constructs an edge computing network collaborative scheduling system based on a high-speed railway platform end security response decentralization under background load to evaluate the performance of such a system under background load. And has A multi-core processor simulation platform with one physical core, whose core model follows a periodically precise computing power allocation logic, wherein the instruction cache and data cache sizes are respectively set to [size missing]. The second-level cache is set to And the three-level shared cache is set to This experiment, designed to simulate the hardware boundaries of edge computing nodes, utilizes random memory access processes to generate bus pressure and superimposes a signal-to-noise ratio of [value missing] on the video bitrate acquisition link. Gaussian white noise is used to simulate physical disturbances, with a sampling period of The setting follows the trade-off logic between the Nyquist sampling theorem and system interrupt overhead. When the upper limit of the characteristic frequency of the security video stream is within... In this state, to capture the bit rate gradient value The step and suppress data processing load, sampling period Set as .

[0033] To verify the synergistic effect and parameter boundaries of the physical isolation mechanism, an experimental design included a control system comprising the sample group of this invention, control group 1, control group 2, and an out-of-range control group. Control group 1 employed the Completely Fair Scheduling Algorithm; control group 2, while retaining the scheduling logic, disabled the hardware interception logic of the cache consistency filtering module; and the out-of-range control group had a preset risk slope threshold. Set as The sample of this invention adopts page table attribute modification and inter-core consistency silent procedure, and sets a preset risk slope threshold. for The experiment constructed a problem intensity gradient by adjusting the memory access intensity of non-security processes. Specific data are shown in Table 1.

[0034] Table 1: Performance Test Comparison Data of Edge Computing Network Collaborative Scheduling System

[0035]

[0036] See Table 1, when bus memory access conflicts occur from Increase to At that time, the standard deviation of the time delay in control group 1 was changed from Increase to This reflects the nonlinear growth of response fluctuations; however, after the sample of this invention triggers the storage isolation control word upon meeting the judgment conditions, it modifies the page table entry attributes through the memory management module and intercepts the bus sniffing signal using the cache consistency filtering module, causing the security core to enter the private address domain execution state, even when the bus load reaches Under normal operating conditions, the single-frame response latency remains at [value missing]. And the standard deviation of the delay remains at Within this range, it confirms that the synergistic effect of page table isolation and bus interception mechanisms creates a physical execution environment, ensuring that the processing cycle of security tasks is no longer interfered with by external memory access. Analysis of the out-of-range control group data shows that when the preset risk slope threshold... Set as At that time, the system was unable to generate the memory isolation control word in time during the initial stage of the bit rate increase, causing the processor core to be vulnerable before the risk occurred. The system is still in a multi-core contention state, which triggers a latency jump; this experiment obtains the second-order rate of change of the video data stream bitrate and calculates the acceleration parameters. In determining acceleration parameters When the memory management module exhibits a non-linear increasing trend, it adjusts the memory management module according to the acceleration parameters. The measured values ​​will preload the shadow page table into the depth by Adjusted to This process compensates for the addressing pause caused by the lack of address translation entries during the moment of task preemption, and ultimately achieves the capture of sudden intrusion behavior at the end of the high-speed rail platform.

[0037] Example 3: This example combines Figs. 1-2 This document describes an edge computing network collaborative scheduling system for the decentralization of security response at high-speed railway platform ends, such as... Fig. 1 As shown, the process begins with the data acquisition module receiving video data streams from the security monitoring area at the end of the high-speed rail platform. On one hand, it performs the operation of acquiring video data streams and inputting them into security tasks. On the other hand, it is responsible for monitoring bit rate change parameters and passing the extracted bit rate change parameters to the scheduling and allocation module. The scheduling and allocation module performs logical operations to calculate the bit rate gradient and load prediction based on the input parameters. When the conditions are met, it generates a storage isolation control word containing a task identifier and index and sends it to the memory management module. The memory management module then performs operations to intercept virtual address access requests and modify the memory attribute control bits of page table entries. The resulting branch paths directly modify physical page table entries to act on the processor core. On the other hand, it sends a signal to configure private address domain attributes to the cache consistency filtering module. The module identifies the private address domain memory access status and performs operations to block inter-core consistency protocol sniffing requests. Finally, by combining the control flow that blocks sniffing requests with the data stream of the input video data stream, the processor core can safely execute security tasks under the protection of the private address domain.

[0038] like Fig. 2 As shown, the system's front end sends burst video streams from surveillance cameras to the edge. The core processing unit is an edge computing node integrated machine, which is logically divided into a regular processing area and an isolation area. The regular processing area runs non-security business background processes and hardware resource isolation and scheduling engines, integrating functional modules for load prediction, addressing interception, and cache filtering. It is connected to the physical isolation domain of security tasks on the right through isolation commands and dedicated channels. The security processing core in exclusive execution state and private address domain memory are deployed in the regular processing area to achieve physical isolation at the hardware level. In addition, the edge computing node maintains a connection with the cloud server through the computing power collaboration link at the bottom to support cloud-edge collaborative computing power scheduling.

[0039] Example 4: When the system faces a situation where drastic changes in ambient lighting at a high-speed railway platform cause physical noise interference to the video encoding bitrate, the edge computing network collaborative scheduling system executes the environmental benchmark calibration procedure. Within a preset silent period after startup, the system acquires the initial video data stream of the security monitoring area through the data acquisition module. The monitoring unit in the scheduling and allocation module then... Sampling period Continuous data collection Real-time bit rate per sample point The logic decision unit calculates the standard deviation of the bit rate gradient of the sample points. To quantize the background noise intensity, where the real-time bit rate The unit is Bit rate gradient standard deviation The unit is The system is based on the formula Determine the risk slope threshold ; This is the risk slope threshold, and its unit is... ; The static risk slope benchmark value is [value to be filled in]. ; This is the noise suppression factor, and its value is... ; The standard deviation of the bit rate gradient during the silent period; the scheduling and allocation module calculates the bit rate gradient value in real time during the security task execution cycle. and compare it with the calibrated risk slope threshold. Perform quantitative comparison, when judged And bit rate gradient value Exceeding the risk slope threshold The state lasts longer than During each sampling period, the system determines that the preset burst access conditions are met. The scheduling and allocation module generates and sends a storage isolation control word containing a task identifier and address space index to the memory management module. The memory management module receives the storage isolation control word, intercepts the physical addressing transactions of the processor core during the execution of the security identification task, and modifies the memory attribute control bits in the physical page table entry to activate the hardware interception logic of the cache consistency filtering module. In the execution of the environmental benchmark calibration procedure, the monitoring unit collects 100 consecutive sample points of real-time bit rate during the initialization period. And calculate the standard deviation of the bit rate gradient. The logic decision unit determines the outcome based on the formula. Determine the risk slope threshold ; This represents the risk slope threshold, in Mbps / s. The static risk slope baseline is 400 Mbps / s; This is a noise suppression factor with a value of 3.0; The standard deviation of the bit rate gradient during the silent period is expressed in Mbps / s. This is the real-time bit rate, measured in Mbps.

[0040] After the power management module detects that the storage isolation control word is active, it clamps the core power supply voltage within the range of 1.15V to 1.25V by writing to the control register. This suppresses clock reference jitter caused by cross-frequency regulation and maintains the stability of the security core at its rated highest frequency. Simultaneously, the memory management module, according to the formula... The calculated acceleration parameters Determine the pre-store depth of the shadow page table; For acceleration parameters, the unit is... ; For real-time bit rate; For sampling time; when the acceleration parameter Not greater than At that time, the memory management module sets the shadow page table preload depth to 1. Page entries, when acceleration parameters Greater than and not greater than At that time, the shadow page table preload depth is set to Page entries, when acceleration parameters Greater than At that time, the shadow page table preload depth is set to Page table entries; the memory management module performs address translation preheating, which latches pre-selected security algorithm virtual address mapping entries in a preset path of the translation detection buffer, eliminating pipeline stalls caused by missing page table entries during context switching transients of the processor core. Simultaneously, after the power management module detects the storage isolation control word being active, it suspends the processor core's deep sleep switching logic and maintains the core voltage at no less than... The operating level is adjusted to suppress clock phase shift caused by cross-frequency regulation. The memory access instruction stream of the security algorithm obtains priority authorization weights through the bus arbitration module, which are determined by the default. Upgraded to The system establishes a noise compensation mechanism for the physical characteristics of security data streams and a quantitative mapping relationship for computing power requirements. It constructs an exclusive access channel for security tasks at the physical storage architecture level, enabling edge computing nodes to maintain physical consistency of security response latency under light and shadow interference.

[0041] Example 5: In the pre-parametric calibration scenario for deployment on a new hardware platform, the edge computing network collaborative scheduling system executes the physical execution environment sensitivity test logic. It generates a computational load with a fixed gradient by loading a synthetic video stream. The scheduling and allocation module collects the execution time of the security identification algorithm during the alternating operation cycles of the processor core in isolated and non-isolated states. And the transaction wait delay recorded by the bus arbitration module The system uses formula Calculate the normalized memory access impact factor. ; This is a memory access impact factor, used to characterize the physical sensitivity of the hardware architecture to memory access conflicts; The execution duration is expressed in units of... ; The delay for waiting for transactions is expressed in units of 1. The memory management module considers memory access impact factors. Based on the distribution characteristics, obtain the pre-stored depth of the shadow page table. The corresponding rate of change of the memory access impact factor, and the rate of change approaching Determine the shadow page table pre-store depth at time The segmented mapping intervals convert the physical addressing costs under different microarchitectures into a quantitative quota of address space indexes in the storage isolation control word.

[0042] When performing frequency-locked boundary detection in the power management module, the critical stable voltage that satisfies the timing constraints of the security identification task is determined by progressively reducing the processor core's operating voltage and monitoring the instruction exit clock cycles of the instruction pipeline. ; The critical steady voltage, in units of In determining the critical steady voltage Subsequently, the power management module superimposes it with a preset temperature drift compensation term to serve as the sustain level during the effective period of the storage isolation control word. Simultaneously, the bus arbitration module calculates the sustain level based on the average memory access density generated by each processor core when performing non-security tasks, using a formula... Determine the priority authorization weight for security tasks ;in, As a priority authorization weight, This is the preset proportional adjustment coefficient. These are the aforementioned factors affecting memory access.

[0043] Example 6: In the initialization scenario of a security cluster at a high-speed railway station platform with heterogeneous computing resources and multiple edge computing nodes, the computing network resource benchmark calibration procedure is executed, and the monitoring unit collects the computing load difference between the edge computing nodes and adjacent computing nodes. Among them, the difference in computing power load The difference between the number of uncompleted floating-point instructions per unit time is determined by the logic decision unit according to the formula. Calculate the load imbalance ;in, For load imbalance; The rated peak computing power of an edge computing node, in units of When the load is unbalanced Exceeding the preset migration threshold When the edge gateway module extracts computational density exceeding the preset floating-point operation threshold... The security subtasks are encapsulated into data packets with task affinity tags and forwarded to the execution node with the lowest computing load. A task migration triggering procedure is established through quantized mapping of physical layer load density, eliminating queuing latency caused by single-node instruction backlog. Based on this, the edge gateway module executes a hardware resource feature matching procedure, calculating the computing power normalization coefficient of each execution node by obtaining the processor core architecture feature code of each node and the local physical memory access latency benchmark. ; This is the computing power normalization coefficient, used to mitigate performance differences between heterogeneous hardware; the edge gateway module uses the formula... Adjust the expected cost of the migration task; where This is the corrected load forecast value. To achieve the original computational density, the system eliminates the nonlinear drift in response delay caused by hardware generation differences at edge nodes by establishing an equivalent computing power model.

[0044] When the system performs adaptive calibration of bus injection latency for different microarchitecture processors, the bus arbitration module obtains the real-time bandwidth requirements of the security data stream. Observation bandwidth of non-security data streams and using the formula Determine the number of wait cycles injected by the hardware arbitrator. ; Number of injected clock cycles; The preset proportional adjustment coefficient has a value of [value missing]. The bus arbitration module inserts the number of wait cycles into the hardware arbitration window. This creates access gaps at the physical bus layer to ensure that the effective bandwidth of the security core is not lower than the rated value under multi-core bus contention. Meanwhile, when the power management module detects that the system clock frequency deviates from the preset center frequency, it triggers the auxiliary clock source switching logic and maintains the core voltage at [the specified value]. To suppress physical layer data transmission jitter, this process ensures the consistency of the edge computing network collaborative scheduling system under different physical load intensities by establishing a closed-loop adjustment model of the hardware operation boundary.

[0045] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. An edge computing network collaborative scheduling system for security response decentralization at high-speed railway platform ends, characterized in that, include: The data acquisition module is used to acquire video data streams from the security monitoring area at the end of the high-speed railway platform and input the video data streams into the security task. The scheduling and allocation module is used to obtain the bit rate change parameters of the video data stream, perform load prediction based on the mapping relationship between the bit rate change parameters and the preset risk threshold, and generate and send a storage isolation control word containing a task identifier and address space index to the memory management module when it is determined that the preset burst access conditions are met. The memory management module is used to receive storage isolation control words, intercept virtual address access requests from security tasks, and modify the memory attribute control bits in the physical page table entries corresponding to the security tasks according to the task identifier and address space index, so as to configure the physical storage space mapped by the security tasks as the private address domain of the processor core. The cache coherence filtering module, integrated into the processor bus controller, is used to identify the memory access status of private address domains and, at the hardware logic level, shield the cache line status sniffing requests generated by the inter-core coherence protocol on the processor cores performing security tasks. The scheduling and allocation module includes: a monitoring unit for acquiring the bitrate gradient value of the video data stream; and a logic determination unit for triggering the logic of issuing the storage isolation control word when the bitrate gradient value exceeds the preset risk slope threshold. The logic determination unit reads the memory region structure in the process descriptor corresponding to the security task through the system bus and extracts the physical page frame number pre-allocated in the linear address space for the security task. The logic determination unit maps the physical page frame number to a hardware address mask with a fixed offset and fills the hardware address mask into the storage isolation control word as an address space index. When performing signal masking, the cache consistency filtering module is also used to intercept bus invalidation broadcast signals generated by write tasks performed by non-security cores, so as to keep the cache line corresponding to the security task in an exclusive modification state.

2. The edge computing network collaborative scheduling system for security response at the end of high-speed railway platforms according to claim 1, characterized in that, The system also includes a bus arbitration module, which injects a bus occupancy wait period into the processor core executing non-security tasks during the security task execution cycle, so as to create access gaps for non-security tasks at the physical bus layer.

3. The edge computing network collaborative scheduling system for security response at the end of high-speed railway platforms according to claim 1, characterized in that, The system also includes a power management module, which locks the dynamic frequency regulation logic of the processor core during the storage isolation control word to suppress clock cycle jitter of edge computing nodes during load fluctuations.

4. The edge computing network collaborative scheduling system for security response at the end of high-speed railway platforms according to claim 1, characterized in that, The memory management module is also used to perform shadow page table preheating. It calculates the shadow page table pre-store depth by obtaining the second-order rate of change of the video data stream bit rate, and, in conjunction with the memory attribute control bit settings in the physical page table entries, preloads address translation entries at the moment of security task switching.

5. The edge computing network collaborative scheduling system for security response decentralization at high-speed railway platform ends according to claim 4, characterized in that, The calculation of shadow page table pre-store depth is based on acceleration parameters. acceleration parameters The calculation logic is as follows: ,in, For the real-time bitrate of the video data stream, The sampling time; the memory management module determines the sampling time based on the acceleration parameters. The numerical value adjusts the number of preloaded entries in the shadow page table warm-up process.

6. The edge computing network collaborative scheduling system for security response decentralization at high-speed railway platform ends according to claim 1, characterized in that, The memory management module is also used to perform cache index conflict suppression processing. By remapping the physical page table addresses of non-security processes, it avoids the cache index bits of the processor core executing security tasks, thereby eliminating cache line replacement competition under the set-associative mapping rule.

7. The edge computing network collaborative scheduling system for security response decentralization at high-speed railway platform ends according to claim 1, characterized in that, The system also includes an edge gateway module, which is used to obtain the difference in computing power load between edge computing nodes and cloud servers, and to migrate subtasks in security tasks whose computing density exceeds a preset floating-point operation threshold to preset edge execution nodes.

8. The edge computing network collaborative scheduling system for security response decentralization at high-speed railway platform ends according to claim 1, characterized in that, The processor core includes multiple physical cores. The scheduling and allocation module adjusts the number of online physical cores participating in the execution of security tasks based on the instantaneous change in the feature entropy of the video data stream. The feature entropy is obtained by statistically analyzing the pixel probability distribution of key frames in the video data stream.

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