Software method and system for simulating SSD NAND operation logic

Abstract

The invention provides a software method and system for simulating SSD NAND operation logic, and belongs to the technical field of solid state disks. The method comprises the steps that received operation commands are dynamically graded and scheduled, emergency read commands are distributed to a high-priority queue, and write commands and erase commands are distributed to a low-priority queue; according to a preset NAND time sequence model, carrying out dynamic simulation on the busy waiting time and the error bit rate of the NAND operation; instruction issuing, busy waiting, state detection and data transmission processes are controlled based on the operation state machine; the current operation is suspended when the low-priority operation is executed, and the suspended operation is recovered after the high-priority operation is completed; and a simulation error state is injected before the operation is completed and is used for software algorithm debugging. The software algorithm development process is greatly shortened.

Description

Technical Field

[0001] This invention relates to a software method and system for simulating the operation logic of an SSD NAND flash memory, belonging to the field of solid-state drive technology. Background Technology

[0002] The development of enterprise-level SSDs currently faces severe challenges: with the increase in the number of 3D NAND layers and the application of new media such as QLC, hardware complexity is growing exponentially, causing software debugging cycles to account for more than 70% of product development time. There are three main factors: First, there is strong hardware coupling, and debugging depends on the physical NAND chip and the prototype of the SSD product board. However, the delivery of wafer fab samples and the development and debugging of product boards may be delayed by 4-6 months, and hardware errors (such as timing violations) need to be repeatedly iterated and verified, with a single debugging cycle exceeding 2 weeks. Second, the internal state of NAND (such as the RD_STAGE_CHK_STS stage status code and the actual value of busy_time) cannot be captured in real time. Engineers can only infer faults by reverse engineering through FTL logs, and it takes an average of 3 person-days to locate a LUN-level deadlock problem. Finally, hardware emulators (FPGA prototypes) can only simulate basic commands and cannot reproduce complex scenarios (such as context disorder during suspension and resumption), causing software defects to emerge in the mass production stage, which may cost more than one million.

[0003] With the rapid development of information technology, the demand for data storage has exploded. As high-performance data storage devices, the development and optimization of enterprise-grade SSDs have become crucial. In recent years, the number of 3D NAND layers has been continuously increasing, and new media such as QLC have been widely used in SSDs, leading to an exponential increase in hardware complexity. Against this backdrop, enterprise-grade SSD development faces numerous severe challenges, among which excessively long software debugging cycles have become a key factor restricting rapid product launches and reducing development costs. Statistics show that software debugging cycles account for more than 70% of the total product development time, seriously impacting the market competitiveness of enterprises.

[0004] Strong hardware coupling: In enterprise-level SSD development, software debugging is highly dependent on the physical NAND chips and the prototype SSD product board. However, the wafer foundry sample delivery and the product board development and debugging process are often fraught with uncertainty, potentially resulting in delays of 4-6 months. Moreover, hardware errors, such as timing violations, require repeated iterative verification, with a single debugging cycle exceeding two weeks. This high dependence on hardware and the complex handling of hardware issues significantly slows down the software debugging process.

[0005] The internal state of NAND flash memory is difficult to capture in real time: NAND flash memory contains various states, such as the RD_STAGE_CHK_STS stage status code and the actual value of busy_time, but engineers currently cannot obtain this information in real time. During actual debugging, engineers can only infer the cause of the fault by working backward from the FTL logs. This indirect fault location method is inefficient; locating a single LUN-level deadlock problem takes an average of three person-days, severely impacting software debugging efficiency.

[0006] Hardware emulators have limited functionality: While commonly used in enterprise SSD development to simulate hardware behavior, they have significant limitations. Hardware emulators can only simulate basic commands and are unable to effectively reproduce complex scenarios, such as contextual errors during suspension and resumption. This leads to many software defects only becoming apparent in mass production, at which point the cost of resolving them can exceed millions, causing substantial economic losses for the enterprise.

[0007] In summary, existing enterprise-level SSD development and debugging technologies suffer from problems such as strong hardware coupling, difficulty in real-time capture of NAND internal states, and limited hardware emulator functionality, resulting in excessively long software debugging cycles and high costs. Therefore, there is an urgent need for a new technical approach that can accurately simulate SSD NAND operational logic without relying on hardware, enabling early debugging of software algorithms, thereby shortening the development process and reducing development costs. Summary of the Invention

[0008] The purpose of this invention is to provide a software method and system for simulating the operation logic of SSD NAND, which enables debugging of SSD algorithm functions and performance, as well as error handling strategies, without the need for wafer fab sample delivery and product boards, thus greatly shortening the software algorithm development process.

[0009] To achieve the above objectives, the present invention employs the following technical solution: A software method for simulating SSD NAND operation logic, comprising: The received operation commands are dynamically classified and scheduled, with urgent read commands assigned to high-priority queues and write and erase commands assigned to low-priority queues. Based on the preset NAND timing model, the busy wait time and error bit rate of NAND operations are dynamically simulated. The system controls the issuance of operational state machine commands, busy waiting, state detection, and data transmission. It suspends the current operation when a low-priority operation is executed and resumes the suspended operation after the high-priority operation is completed. It injects simulated error states before the operation is completed for software algorithm debugging.

[0010] Preferably, the dynamic hierarchical scheduling specifically includes: When a high-priority command arrives, if its target logic unit is in a busy state executing a low-priority command, a NAND suspend operation is triggered to interrupt the low-priority command and the high-priority command is executed immediately. Low-priority commands are suspended when high-priority commands arrive, and their operation context is recorded, which includes the command type of the suspended operation and the remaining busy wait time.

[0011] Preferably, a suspend counter is maintained for each logical unit. When the number of suspends for the same logical unit exceeds a preset threshold, the issuance of new high-priority commands to that logical unit is paused until the currently suspended low-priority commands are completed.

[0012] Preferably, the NAND timing model includes: Read operation latency is generated using a Gaussian distribution; Write operation latency The calculation formula is as follows: The number of erase / write cycles is dynamically adjusted. , in, This refers to the number of erase / write cycles; Error bit rate Simulation is based on the following formula: , in, This refers to the chip's original bit error rate. This refers to the nominal number of erase / write cycles.

[0013] Preferably, the operating state machine includes: Read operations first check the high-priority queue and the corresponding Plane status; if there are no conflicts, the operation is immediately sent. Write or erase operations check the low-priority queue and the status of the corresponding logical unit. If the logical unit is busy, it waits. During the busy waiting period, the status query command can be issued repeatedly; After the busy waiting period ends, the operation is confirmed to be complete through status detection, and a data output command is issued.

[0014] Preferably, the error injection includes: After the NAND operation state machine detects a ready state, it replaces the operation success status code with a predefined error status code; or it injects a simulated hardware error state into the operation process, which includes error correction failure, empty page read, or data transmission error.

[0015] A software system simulating SSD NAND operation logic, comprising: The multi-level dynamic scheduling module is used to dynamically schedule commands based on their priority. This includes setting up high-priority queues and low-priority queues. High-priority commands can interrupt the execution of low-priority commands, and a suspend counter is introduced to ensure the completion of low-priority commands when the number of suspends exceeds a threshold. The NAND model module is used to simulate the operation timing and behavior of NAND flash memory through a parametric physical behavior engine; The error injection module is used to automatically inject errors into the state machine layer or operation status code of the NAND model module to verify the robustness of the system.

[0016] As a refinement of the above embodiments, the multi-level dynamic scheduling module implements a priority-based hierarchical design for commands. The P0 level is for urgent read commands and has the highest preemption privilege. It can interrupt the P2 level write command or the P3 level erase command through the NAND suspend operation. The P1 level is for regular read commands, which allow deep queuing but cannot be preempted. The P2 and P3 level commands support context saving and recovery.

[0017] Preferably, when a P0-level command arrives, the status of its corresponding logical unit is detected in real time; if the target logical unit is in the LUN_BUSY state and is performing a write or erase operation, the current operation is interrupted and the P0-level read command is executed immediately.

[0018] The advantages of this invention are: based on this method, important aspects such as SSD algorithm function and performance debugging and error handling strategy debugging can be performed without the need for wafer fab sample delivery and product boards, which greatly shortens the software algorithm development process. Attached Figure Description

[0019] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0020] Figure 1 This is a schematic diagram of the method flow of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Example 1 This invention constructs a fully software-defined NAND behavior model, fundamentally solving the aforementioned problems. First, it provides accurate simulation of NAND behavior independent of hardware, such as NAND busy time, which can be arbitrarily configured according to project requirements. It can also simulate specific NAND operations, such as multiplane, singleplane, and PlaneIndependentRead, allowing for normal algorithm functionality and performance debugging even without hardware boards. Second, it enables automated error injection, such as layered fault injection, including instruction-level injection and operation state injection. Finally, it allows for advanced fault testing strategies, including timing-related fault chains and coverage guarantee mechanisms. All of these ensure early algorithm debugging without hardware involvement, significantly shortening the subsequent development process.

[0023] like Figure 1 As shown, a software method for simulating SSD NAND operation logic includes: S1: Dynamically classify and schedule the received operation commands, assigning urgent read commands to the high-priority queue and write and erase commands to the low-priority queue; S2: Based on the preset NAND timing model, dynamically simulate the busy wait time and error bit rate of NAND operations; S3: Based on the operation state machine, control the instruction issuance, busy waiting, state detection and data transmission process; suspend the current operation when executing a low-priority operation, and resume the suspended operation after the high-priority operation is completed; inject simulated error state before the operation is completed for software algorithm debugging.

[0024] As a refinement of the above embodiments, the dynamic hierarchical and scheduling specifically includes: When a high-priority command arrives, if its target logic unit is in a busy state executing a low-priority command, a NAND suspend operation is triggered to interrupt the low-priority command and the high-priority command is executed immediately. Low-priority commands are suspended when high-priority commands arrive, and their operation context is recorded, which includes the command type of the suspended operation and the remaining busy wait time.

[0025] Specifically, read operations are prioritized by default. First, it checks if there is an available slot in the high-priority queue. If there is an available slot, it checks if the Plane corresponding to the read command is currently performing a read operation. If not, the read command is issued immediately, and the system enters a busy-wait state in NAND. If the Plane is currently performing a read operation, the read command must wait for the previous read operation to complete before it is issued.

[0026] Write and erase operations have low priority by default. First, check if there is an available slot in the low priority queue. If there is an available slot, check if the LUN corresponding to the write / erase operation is in a busy state. For example, if a plane in the LUN is currently performing a read operation, then the LUN is in a busy state and cannot perform a write / erase operation.

[0027] When a LUN or plane is in a write / erase operation and is in a busy state, if a high-priority read operation arrives, the write / erase operation needs to be suspended until the read operation completes, at which point the write / erase operation continues to wait for completion. During the suspension, the operation context needs to be saved, including the command code (write / erase) of the suspended operation and the remaining busy time. Once the high-priority read operation is complete, the resumption operation is performed, and the suspended operation continues.

[0028] As a refinement of the above embodiments, a suspend counter is maintained for each logic unit. When the number of suspends for the same logic unit exceeds a preset threshold, the issuance of new high-priority commands to that logic unit is suspended until the currently suspended low-priority commands are completed.

[0029] As a refinement of the above embodiments, the NAND timing model includes: Read operation latency is generated using a Gaussian distribution; Write operation latency The calculation formula is as follows: The number of erase / write cycles is dynamically adjusted. , in, This refers to the number of erase / write cycles; Error bit rate Simulation is based on the following formula: , in, This refers to the chip's original bit error rate. This refers to the nominal number of erase / write cycles.

[0030] As a refinement of the above embodiments, the operation state machine includes: Read operations first check the high-priority queue and the corresponding Plane status; if there are no conflicts, the operation is immediately sent. Write or erase operations check the low-priority queue and the status of the corresponding logical unit. If the logical unit is busy, it waits. During the busy waiting period, the status query command can be issued repeatedly; After the busy waiting period ends, the operation is confirmed to be complete through status detection, and a data output command is issued.

[0031] After the command is successfully issued, the busy waiting time required for the read is immediately calculated according to the busy time simulation formula. During the NAND busy waiting period, the status check command can be continuously issued to query the status (busy or ready) of the read, but the read status will always return busy.

[0032] When the NAND busy wait is about to end, multiple status detection commands can be issued continuously. The command specifies that the NAND busy wait should return to the busy state before it ends and return to the ready state after the end time is reached. Based on the status detection timing settings, the read / write performance of the SSD software algorithm can be tested.

[0033] Once the status is detected as ready, a data output command can be sent. The data transmission time is calculated based on the reserved NANDIO rate and the amount of data to be read / written. After the data transmission time is delayed, the operation is returned as successful.

[0034] As a refinement of the above embodiments, the error injection includes: After the NAND operation state machine detects a ready state, it replaces the operation success status code with a predefined error status code; or it injects a simulated hardware error state into the operation process, which includes error correction failure, empty page read, or data transmission error.

[0035] Example 2 A software system simulating SSD NAND operation logic, comprising: The multi-level dynamic scheduling module is used to dynamically schedule commands based on their priority. This includes setting up high-priority queues and low-priority queues. High-priority commands can interrupt the execution of low-priority commands, and a suspend counter is introduced to ensure the completion of low-priority commands when the number of suspends exceeds a threshold. The NAND model module is used to simulate the operation timing and behavior of NAND flash memory through a parametric physical behavior engine; The error injection module is used to automatically inject errors into the state machine layer or operation status code of the NAND model module to verify the robustness of the system.

[0036] As a refinement of the above embodiments, the multi-level dynamic scheduling module has two types of queues: high-priority queues and low-priority queues. It uses a priority-based hierarchical design for commands. P0-level emergency read commands have the highest preemption privileges and can interrupt P2 (write) and P3 (erase) level operations using the NAND suspend operation. P1-level regular read commands allow deep queuing but cannot be preempted. P2 / P3 level commands support context saving and restoration.

[0037] When a P0 command arrives, the status of the LUN with that command is monitored in real time. If the target LUN is in LUN_BUSY and the operation is write / erase, a NANDsuspend operation is triggered, interrupting the write / erase operation and immediately executing the P0 read command. If there are many P0 commands, the write / erase operation may remain interrupted and unable to complete. Therefore, a suspension counter is introduced. When the number of suspensions for the same LUN exceeds a threshold, no further priority commands are issued, ensuring that the write / erase command is completed within the set time window.

[0038] As a refinement of the above embodiments, the NAND model module mainly simulates the behavior of NAND flash memory, and is used to accurately simulate the flash memory operation timing in an environment without physical chips, including physical timing simulation, erase, write, read, suspend, multiplane / singleplane, PIR and other functional operations.

[0039] Among them, a parametric physical behavior engine is used for precise timing modeling, including busy time simulation, which generates random delays according to a Gaussian distribution (e.g., mean 40μs, variance 3μs); error bit count simulation, which gradually increases the number of error bits per read based on the number of erase and write operations, while also increasing the time consumption of some read operations; it can also perform state machine driven modeling, which strictly follows the flow of each operation state such as erase, write, and read in NAND flash memory, and the transition time between each state also needs to be strictly configured according to NAND flash memory.

[0040] As a refinement of the above embodiments, the error injection module is used to automatically inject NAND exceptions to verify system robustness. Based on the deterministic nature of NAND operations, errors are primarily injected at the state machine level, forcing jumps between different state machines, from a valid state to an invalid state code (0xFF), triggering a state machine context verification failure. Errors can also be injected into the operation state code, triggering error exception handling for that operation, forcing entry into a software decoding process or a RAID data recovery process, etc.

[0041] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A software method for simulating SSD NAND operation logic, characterized in that, Includes the following steps: The received operation commands are dynamically classified and scheduled, with urgent read commands assigned to high-priority queues and write and erase commands assigned to low-priority queues. Based on the preset NAND timing model, the busy wait time and error bit rate of NAND operations are dynamically simulated. The process of controlling command issuance, busy waiting, status detection, and data transmission based on the operation state machine; Suspend the current operation while performing a low-priority operation, and resume the suspended operation after the high-priority operation is completed; A simulated error state is injected before the operation is completed for software algorithm debugging.

2. The software method for simulating SSD NAND operation logic according to claim 1, characterized in that, The dynamic hierarchical and scheduling mechanism specifically includes: When a high-priority command arrives, if its target logic unit is in a busy state executing a low-priority command, a NAND suspend operation is triggered to interrupt the low-priority command and the high-priority command is executed immediately. Low-priority commands are suspended when high-priority commands arrive, and their operation context is recorded, which includes the command type of the suspended operation and the remaining busy wait time.

3. The software method for simulating SSD NAND operation logic according to claim 2, characterized in that, Maintain a suspend counter for each logical unit. When the number of suspends for the same logical unit exceeds a preset threshold, suspend issuing new high-priority commands to that logical unit until the currently suspended low-priority command is completed.

4. The software method for simulating SSD NAND operation logic according to claim 1, characterized in that, The NAND timing model includes: Read operation latency is generated using a Gaussian distribution; Write operation latency The calculation formula is as follows: The number of erase / write cycles is dynamically adjusted. ， in, This refers to the number of erase / write cycles. Error bit rate Simulation is based on the following formula: ， in, This refers to the chip's original bit error rate. This refers to the nominal number of erase / write cycles.

5. The software method for simulating SSD NAND operation logic according to claim 1, characterized in that, The operational state machine includes: Read operations first check the high-priority queue and the corresponding Plane status; if there are no conflicts, the operation is immediately sent. Write or erase operations check the low-priority queue and the status of the corresponding logical unit. If the logical unit is busy, it waits. During the busy waiting period, the status query command can be issued repeatedly; After the busy waiting period ends, the operation is confirmed to be complete through status detection, and a data output command is issued.

6. The software method for simulating SSD NAND operation logic according to claim 1, characterized in that, The error injection includes: After the NAND operation state machine detects a ready state, it replaces the operation success status code with a predefined error status code; or it injects a simulated hardware error state into the operation process, which includes error correction failure, empty page read, or data transmission error.

7. A software system for simulating SSD NAND operation logic, characterized in that, A software method for executing the simulated SSD NAND operation logic of any one of claims 1-5, comprising: The multi-level dynamic scheduling module is used to dynamically schedule commands based on their priority. This includes setting up high-priority queues and low-priority queues. High-priority commands can interrupt the execution of low-priority commands, and a suspend counter is introduced to ensure the completion of low-priority commands when the number of suspends exceeds a threshold. The NAND model module is used to simulate the operation timing and behavior of NAND flash memory through a parametric physical behavior engine; The error injection module is used to automatically inject errors into the state machine layer or operation status code of the NAND model module to verify the robustness of the system.

8. The software system for simulating SSD NAND operation logic according to claim 7, characterized in that, The multi-level dynamic scheduling module implements a priority-based hierarchical design for commands. Level P0 commands are urgent read commands with the highest preemption privileges and can interrupt Level P2 write commands or Level P3 erase commands through NAND suspend operations. Level P1 commands are regular read commands, which allow deep queuing but cannot be preempted. Level P2 and Level P3 commands support context saving and recovery.

9. The software system for simulating SSD NAND operation logic according to claim 7, characterized in that, When a P0-level command arrives, the status of its corresponding logical unit is monitored in real time. If the target logical unit is in the LUN_BUSY state and is performing a write or erase operation, the current operation is interrupted and the P0-level read command is executed immediately.

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